Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, Kobe, 2005, pp.910-911
C-9-2
Integration of ultra shallow junctions in PVD TaN
nMOS transistors with Flash Lamp Annealing
S. Severia,b, K. De Meyera,b, B. J. Pawlakc, R. Duffyc, C. Kernera, S. McCoyd, J. Gelpeyd, T. Selingerd, L-Å Ragnarssona,
P. P. Absila, M. Jurczaka, S. Biesemansa
a)
IMEC, Kapeldreef 75, BE 3001 Leuven Belgium, b) Katholieke Universiteit.Leuven, ESAT-INSYS, Kasteelpark Arenberg 10,3001
Leuven, c) Philips Research Leuven, Kapeldreef 75, BE-3001 Heverlee, BE, d) Mattson Technology Canada, Vancouver, Canada
Abstract
We demonstrate that the use of Flash annealing to achieve ultra
shallow junctions leads to strong suppression of the Short Channel
Effects (SCE) without compromising device performance in PVD
TaN nMOS transistors. We show that a deep Ge implantation at the
gate edges can be an excellent solution for further improvement in
the B halo activation. The junction overlap length, the S\D resistance
and the device performance are found to be dependent on the defects
evolution as a function of the Flash peak temperature.
Introduction
Ultra shallow and abrupt junctions are one of the major requirements for further scaling of planar CMOS transistors. Several techniques such as low temperature processing [1], and high temperature
Flash annealing [2], [3] have demonstrated great potential for improving the junction profiles and for increasing the dopant activation
above the solid solubility equilibrium limit. However, many integration problems both in pMOS [4] and nMOS transistors have prevented an extensive use of these advanced techniques
We investigate the integration of PVD TaN nMOS transistors
with 25nm depth diffusion-less junctions targeting 45nm gate length.
A deep amorphous layer is created at the gate edges to improve the
halo activation and to move away the End Of Range (EOR) defects
region from the extension junction depletion region. We studied the
defects evolution as a function of the Flash peak temperature and
during post annealing both in the EOR and in the junction overlap
region. The impact of the Flash peak temperature on the defects and
on the transistors characteristics is investigated.
Experimental
The transistors are processed (Fig. 1) with a standard Shallow
Trench Isolation (STI) module. The gate stack consists of 1.4nm
SiON, 17nm PVD TaN and 100 nm of poly silicon. A metal gate
electrode eliminates problem with poly depletion due to insufficient
diffusion of dopants. The suitability of PVD TaN on 1.4nm SiON
has already been demonstrated [5]. B halo implantation with the
same dose is performed on all the wafers. A low dose Ge implantation allows for a deep amorphous layer formation before the As extension junction implantation. A low temperature spacer is formed
without re-growing the amorphous Si layer. The Flash lamp annealing tool used for the junctions doping activation is 3000 times faster
in ramp up and ramp down than the conventional Spike RTA annealing. The chamber reaches an intermediate temperature of 700oC
(iRTA) before ramping up to a Flash peak temperature (fRTA) of
maximum 1300oC for few milliseconds. The a-Si region created
during the As and Ge implantations re-crystallizes during the iRTA
and the doping is activated. NiSi completes the FEOL process.
Results and Discussion
After Silicon re-crystallization at 700oC, we observe the
formation of defects (stacking faults of micro-twins) in the junction
to gate overlap region, as shown in Fig. 2. The stress induced during
the re-growth between the S/D amorphous region and the c-Si under
the gate creates a plane mismatch. Nevertheless, based on the electrical characterization data presented in this paper, these defects
vanish at the interface after the fRTA at 1300oC.
The SIMS As junction profiles implemented in the nMOS
transistors are shown in Fig. 3. The junction depth does not signifi-
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cantly change with increasing Flash peak temperature. At 1300oC
fRTA the As diffuses towards the Si interface. Furthermore a shoulder at a concentration of 5E20 cm-3, not present in the SIMS profile
for lower temperature annealing, indicates a high doping activation.
In fact, despite an unchanged junction depth, the sheet resistance
drops as a function of the fRTA, as shown in Fig. 4.
In Fig. 5, we analyze the stability of the Flash annealed
junctions as a function of post annealing temperature in a range between 600oC and 950oC. The junction sheet resistance degrades
starting from a temperature of 750oC even for the junction annealed
with the highest 1300oC Flash peak temperature. This demonstrates
that the high As doping activation is meta-stable. The defects in the
junction depletion region increase the junction leakage, as shown in
Fig. 6. The leakage, measured directly in transistors, is controlled by
the deep S/D junction with a much larger area compared to the shallow extension junction. At 1100oC the junction leakage further increases compared to 700oC as the B doping reaches higher activation. Due to a partial dissolution of the defects, the leakage drops by
more than one order of magnitude at 1300oC.
The deep Ge pre-amorphization at the gate edges provides
high meta-stable B halo activation to occur during the re-growth of
the a-Si layer. Therefore, even with low temperature annealing, a
good Vt control down to 50nm gate length devices is obtained, as
shown in Fig. 7. A high Flash peak temperature further increases the
B halo doping activation allowing for a significant improvement in
SCE over the spike reference devices. Nevertheless Fig. 8 reveals
that the device performance depends on the Flash peak temperature.
As a consequence of the defects located in the junction to gate overlap region, the overlap resistance strongly increases. High Flash peak
temperature solves this problem allowing for As doping re-activation
while dissolving the defects at the interface. At a fixed off state current of 0.1nA, the device performance is equal for Flash and spike
annealed transistors but the Lmin reduces by 50nm with Flash annealing, as shown in Fig 9. The overlap length significantly decreases for Flash anneal, as shown in Fig. 10. Furthermore for higher
Flash peak temperature the overlap length increases. This is a confirmation of what was explained above. The S\D resistance extraction, presented in Fig. 11, enlightens an improvement going towards
high Flash peak temperature when the overlap length increases. A
further analysis of the off state gate current (Fig. 12) shows a current
decrease for the Flash annealed devices over the spike ones related
to a reduced overlap length.
Conclusion
We have demonstrated that Flash annealing can lead to considerable
reduction in SCE without degradation in Ion. A deep amorphous
layer at the gate edges allows for high doping activation. The defects
introduced during the implantation and during the re-growth can be
removed by high temperature Flash annealing. The overlap and S/D
junctions resistance as well as the transistors performance also improves with increased Flash peak temperature.
References
[1]R. Lindsay et al., IJWT 2004, [2]T. Ito et al., VLSI Tech. Dig. 2003,
[3]A. Satta et al. , MRS 2004, [4]S. Severi et al., IEDM Tech. Dig.2004,
[5]K. Henson et al., IEDM 2004, [6]S.Severi et al., ESSDERC 2004
•
STI isolation +VT-adjust (Boron)
•
Gate stack:
o
o
o
o
•
•
•
•
•
•
10
1.4nm SiON
17nm TaN deposited by PVD
100nm polysilicon
193nm litho + gate etch
NiSi
Nitride
spacer
Boron pockets implant
Germanium pre-amorphization (optional)
Extension implant As 5keV 1e15cm-2
Spacer (400 oC) + As deep S/D implant
Flash annealing
NiSi formation on S/D areas and gate
Flash annealing
380
As 5keV 1e15 cm
o
Flash 700oC+1300oC
5
10
15
Depth (nm)
20
25
Fig. 3 SIMS profiles of As 5keV 1e15 cm-2
for different Flash annealing temperatures.
o
-9
10
Flash 1100 C
o
Flash 700 C
o
Flash 700 C
-10
10
o
340 Flash 1100 C
-11
Flash 1300 C
10
320
300 Flash 1300 C
280
600
280
-12
10
o
800 1000 1200 1400
o
Temperature ( C)
Fig. 4 Sheet resistance versus Flash peak
temperature.
o
500
-0.1
-12
0.25
Fig. 7 Vt sat. measured at Vd=1V for nMOS
transistors with Flash or spike RTA annealing.
20
0
Spike 1050C
Flash 700C
1.2
Flash 1300C
1.3
1.4
1.5 1.6
Vg (V)
1.7
50
90
99
99.99
750
o
Flash 1300 C
o
Spike 1050 C
700
Flash 1100 C
o
Flash 1300 C
650
600
Fix Ioff=0.1nA
o
Flash 1100 C
550
0
200
I
400
ON
600
(µ
µA/µ
µm)
800
450
50
1000
Fig. 8 Performance of nMOS transistors after
Flash annealing at different temperatures.
o
Flash 700 C
500
Vdd=1.2V
EOT=1.2nm
60
70
80
90 100 110 120 130
Lgate minimum (nm)
Fig. 9 Ion versus LMIN for different Flash
annealing temperature
-7
10
No Halo
implanted
-8
400
10
Spike 1050C
Flash 700C
Flash 1100C
Flash 1300C
Metal gate
300
200
-9
o
10
Spike 1050 C
o
Flash 1100C
-40
10
800
o
500
20nm
15nm
7nm
2nm
-20
-13
1
Fig. 6 Junction leakage measured on transistors with Vd=1V. B pockets are implanted.
o
600
No halo
implanted
.01
Cumulative probability (%)
-10
-11
0.2
10
1000
-9
0
0.1 0.15
Lgate (µ
µ m)
900
Flash 700 C
-8
Spike 1050 C
0.05
o
o
-7
o
0
800
Spike 1050 C
-6
o
0.1
700
Fig. 5 Sheet resistance of Flash annealed
junctions after post annealing for 1 minutes.
-5
Flash 1100 C
0.3 Flash 700oC
0.2
600
o
Spike 1050 C
-13
Temperature ( C)
Flash 1300 C
0.4
40
o
Flash 700 C+1100 C
10-8
-2
300
-0.2
10
19
o
320
0.5
20
SPER 700oC 1 min.
360
340
0.6
10
0
420
400
&
360
Poly-silicon
Fig. 2 TEM picture of metal gate nMOS transistors annealed at 700oC with Ge implantation.
-2
380
Defects
(stacking faults,
or micro twins)
25nm
As 5keV 1e15 cm
-2
As 5keV 1e15 cm
SIMS
TaN
Fig. 1 Process flow for the PVD TaN
gated transistors with Flash annealing.
400
21
1.8
Fig. 10 Junction overlap lengths extracted
from IB in inversion versus LPOLY
100
Flash 700 C
o
0
0.5
Vd=1V
As 5keV 1e15 cm-2
o
Flash 1100 C
Flash 1300 C
1
1.5
-10
2
Vg (V)
2.5
3
3.5
Fig. 11 S/D junctions resistances extracted from
RTOT versus LEFF for small LGATE.
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10
.01
1
10
50
90
99
99.99
Cumulative probability (%)
Fig. 12 Gate overlap currents for equal junction implant and different Flash temperature.