Recall: Arithmetic -- addition
ENG241
Digital Design
Binary addition is similar to decimal arithmetic
No carries
Week #5
Arithmetic Circuits
1 0
1 1 0 0
0 1 1 0 0
1
0 1 1 0
+ 1 0 0 0 1
+ 1
0 1 1 1
Carries
1 0 1 1 0 1
1 1 1 0 1
Remember:
1+1 is 2 (or (10)2), which results in a carry
1+1+1 is 3 (or (11)2) which also results in a carry
4
Topics
Half Adder (One bit adder)
Binary Adders
Binary Ripple Carry Adder
1’s and 2’s Complement
Binary Subtraction
Binary Adder-Subtractors
Binary Multipliers
BCD Arithmetic
o
o
S = XY’ + X’Y
=X⊕Y
C = X.Y
2
5
Resources
Full Adder
x
y
Chapter #5, Mano Sections
5.2
5.3
5.4
5.5
5.7
Binary Adders
Binary Subtraction
Binary Adders-Subtractors
Binary Multiplications
HDL Representations -- VHDL
o
Z
Two outputs:
Sum
Cout
3
Z
S
Three inputs:
X
Y
Third is Cin
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Full Adder
Cout
Implementation?
6
1
Any Alternatives?
Straight Forward Implementation:
K Map for S
o
S
Z
o
What is this?
Try to make use of hierarchy to design
a 1-bit full adder from two half adders.
Also, try to share logic between the
Sum output and Carry output.
Full Adder
S=X⊕Y⊕Z
C = XY + XZ + YZ
Half Adder
S=X⊕Y
C = XY
7
10
A Different Way to Represent C
Straight Forward Implementation:
K Map for C
XYZ
YZ
X
X
00
01
11
10
1
1
1
1
X
Y
0
C
Z
1
XY
XYZ
C = XY + XZ +YZ
C = XY + XYZ + XYZ
Y
Z
C = XY + Z (XY + XY)
8
Implementation Issues
11
Two Half Adders (and an OR)
How many Gates
do we need?
C = XY + XZ +YZ
o
If we try to implement the Optimized
Boolean functions directly we will need
how many gates?
o
Can we do better?
YES!!
Seven AND gates and two OR Gates!!
o
x
Share Logic
Hierarchical Design.
C
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y
Full Adder
S
Z
12
2
VHDL Half Adder (DATA FLOW)
Binary Ripple-Carry Adder
A Parallel binary adder is a digital circuit that
produces the arithmetic sum of two binary
numbers using only combinational logic.
The parallel adder uses “n” full adders in
parallel, with all input bits applied simultaneously
to produce the sum.
The full adders are connected in cascade, with
the carry output from one full adder connected to
the carry input of the next full adder.
entity half_adder is
port (x,y: in std_logic;
s,c: out std_logic);
end half_adder;
architecture dataflow of half_adder is
begin
s <= x xor y;
c <= x and y;
end dataflow
13
Binary Ripple-Carry Adder
16
VHDL Full Adder (Structural)
entity full_adder is
port (x, y, z: in std_logic;
s, c: out std_logic);
end full_adder;
architecture struc_dataflow of full_adder is
component half_adder
port (x, y : in std_logic;
s, c : out std_logic);
end component;
signal hs, hc, tc: std_logic;
begin
HA1: half_adder
port map (x, y, hs, hc);
HA2: half_adder
port map (hs, z, s, tc);
c <= tc or hc;
end struc_dataflow
Straightforward – connect full adders
Carry-out to carry-in chain
C0 in case this is part of larger chain,
maybe just set to zero
hs
tc
hc
14
Hierarchical 4-Bit Adder
17
Any Problems with this Design?
We can easily use hierarchy here
1.
2.
3.
Design half adder
Use TWO half adders to create full adder
Use FOUR full adders to create 4-bit adder
Delay
Approx how much?
Imagine a 64-bit adder
Look at carry chain
VHDL CODE?
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3
Carry Propagation & Delay
BCD Arithmetic
8
1000 Eight
+5
+0101 Plus Five
13
1101 is 13 (> 9)
Note that the result is MORE THAN 9, so must be
represented by two digits!
To correct the digit, add 6
8
1000 Eight
+5
+0101 Plus 5
13
1101 is 13 (> 9)
+0110 so add 6
carry = 1 0011 leaving 3 + cy
0001 | 0011 Final answer (two digits)
One problem with the addition of binary numbers is the length
of time to propagate the ripple carry from the least significant
bit to the most significant bit.
The gate-level propagation path for a 4-bit ripple carry adder of
the last example:
Note: The "long path" is from A0 or B0 through the circuit to S3.
A3
B3
A2
C3
A1
B2
C2
B1
A0
C1
B0
C0
C4
S3
S2
S1
S0
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ENG241/Digital Design
BCD Addition
22
BCD Addition Circuit
One decimal digit + one decimal digit
Design a BCD Adder that adds two BCD digits.
Constraints:
Use 4-bit Binary Adders
Hints:
A detection circuit that detects invalid BCD
digits will need to be designed.
● If the result is 1 decimal digit ( ≤ 9 ), then it is a simple
binary addition
Example:
5
0101
+ 3
+ 0011
8
1000
● If the result is two decimal digits ( ≥ 10 ), then binary
addition gives invalid combinations
Example:
0001 0000
5
0101
+ 5
+ 0101
10
1010
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23
BCD Addition
BCD Addition
If the binary result
is greater than 9,
correct the result by
adding a “6”
5
0101
+ 5
+ 0101
10
1010
Augend
Addend
4-bit binary adder
Carry
+ 0110
0001 0000
Multiple Decimal Digits
Output
Carry
351
Input
Detection
Circuit for
Invalid BCD
0 or 6
Two Decimal Digits
4-bit binary adder
0011 0101 0001
BCD Sum
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ENG241/Digital Design
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4
BCD Addition
Z3 Z2 Z1 Z0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Complements of Decimal System
The 9’s complement of a decimal number is
obtained by subtracting each digit from 9.
Example: The 9’s complement of 546700 is
999999 – 546700 = 453299
The 10’s complement is obtained by adding 1
to the 9’s complement:
Example: The 10’s complement of 546700 is
999999 – 546700 = 453299 + 1 = 453300
Or, 1000000 – 546700 = 453300
Or, leave all least significant 0’s unchanged, subtract
the first nonzero LSD from 10, and subtract all higher
significant digits from 9.
25
Subtraction
28
Unsigned Decimal Subtraction
Example #1
72532 – 3250 = 69282
Use 10’s complement to perform the subtraction
M = 72532 (5-digits), N = 3250 (4-digits)
We managed to design an Adder easily.
For subtraction, we will also need to design a
Subtractor!!
Can we perform subtraction using the Adder
Circuit we designed earlier?
YES, we can use the concept of Complements.
X=Y–Z
Since N has only 4 digits append a zero N=03250
What is the 10’s complement of N (03250)?
99999 – 03250 = 96749 + 1 = 96750
Now add M to the 10’s comp of N
72532 + 96750 = 169282 (carry occurred)
X = Y + complement(Z)
The occurrence of the end carry indicates that M > N
Discard end carry (169282 – 100000 = 69282)
26
Complements?
29
Unsigned Decimal Subtraction
Example #2
There are two types of complements for each
base-r system
The radix complement, the (r’s) complement.
The diminished radix complement, (r-1)’s comp.
For Decimal System
3250 - 72532 = - 69282 (HOW??)
Compare the numbers, exchange their positions, …
Use 10’s complement to perform the subtraction
M = 3250 (4-digits), N = 72532 (5-digits)
Since M has only 4 digits append a zero M=03250
What is the 10’s complement of N (72532)?
10’s complement
9’s complement
99999 – 72532 = 27467 + 1 = 27468
For Binary Systems
Now add M to the 10’s comp of N
2’s complement
1’s complement
03250 + 27468 = 30718 (There is no end carry!)
No end carry indicates that M < N (make correction!!)
Answer: -(10’s complement of 30718) = -69282
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5
2’s Complement
Binary Subtraction
2’s Complement (Radix Complement)
OR
We’ll use unsigned subtraction to
motivate use of complemented
representation
● Take 1’s complement then add 1
● Toggle all bits to the left of the first ‘1’ from the right
Example:
10110000
Number:
10110000
1’s Comp.: 0 1 0 0 1 1 1 1
+
1
01010000
01010000
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31
2’s Complement: Example
1’s Complement
1’s Complement (Diminished Radix Complement)
● All ‘0’s become ‘1’s
2n
1
0
0
0
0
0
0
● All ‘1’s become ‘0’s
Example (10110000)2
(01001111)2
-N
0
1
1
0
0
1
1’s Comp
1
0
0
1
1
0
2’s Compl.
1
0
0
1
1
1
If you add a number and its 1’s complement …???
Notice that the 2’s complement of the number 011001 can
be obtained by complementing each bit and adding 1.
10110000
+ 01001111
11111111
32
1’s Complement: Example
1
0
1
0
1
0
1
35
Example: Incorrect Result
0
Minuend is smaller than Subtrahend
0
1
0
1
0
1
0
Borrow
1
Notice that the 1’s complement of the number
10101010 can be obtained by complementing each bit
(N) Subtrahend
Difference
2n - 1
1
1
1
1
1
1
-N
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
1
19 – 30 = 21 !!!!!
How can we know if the result is incorrect? How to fix the problem?
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-
1
1
Incorrect Result!!
1
1’s Compl.
1
(M) Minuend
36
6
How to get rid of Subtraction Operation?
Example
Borrow
1
(M) Minuend
(N) Subtrahend
-
Difference
Correct Diff
-
1
1
0
0
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
1
If no borrow, then result is
non-negative (minuend >=
subtrahend).
Any
Idea?
Since there is borrow, result
must be negative.
The result must be
corrected to a negative
number.
Use complements of numbers to replace the
subtraction operation with addition only.
19 – 30 = -11
Procedure?
37
40
Subtraction of Unsigned Numbers
Using Complements
Algorithm: Subtraction of two n-digit
Numbers M-N can be done as follows
Subtract N from M
1.
!
2.
3.
M – N Equivalent to M + (2’s complement of N)
Add (2’s complement of N) to M
1.
If no borrow, then M ≥ N and result is OK
Otherwise, N > M so result must be
subtracted from 2n and a minus sign
should be appended
NOTE: Subtraction of a binary
number from 2n to obtain an n-digit
result is called 2’s complement
Circuit?
2.
This is M + (2n – N) = M – N + 2n
Notice we are using addition to achieve subtraction.
If M ≥ N, will generate carry!
3.
Result is correct
Simply discard carry
Result is positive M - N
•
•
If M < N, no end carry will be generated!
4.
•
•
Make Correction
Take 2’s complement of result
Place minus sign in front
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41
Example
Adder/Subtractor Circuit!!
o
o
Binary Adder
o
Binary Subtractor
EXPENSIVE!!
X = 1010100 minus Y = 1000011
Notice that X > Y
The 2’s complement of Y=1000011
is obtained first by getting the 1’s
complement
0111100 and then
adding 1
(0111101)
X
1
0
1
0 1 0 0
+ 2’s comp Y
0
1
1
1 1 0 1
0
0
1
0
Sum
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1
0 0 1
42
7
Design
Example 2
Y = 1000011 minus X = 1010100
Notice Y < X
Y
1
0
0
0 0 1 1
+ 2’s comp X
0
1
0
1 1 0 0
Sum
1
1
0
1
S low for add,
high for subtract
Inverts each bit
of B if S is 1
1 1 1
No end carry
Answer: - (2’s complement of Sum)
- 0010001
Adds 1 to
make 2’s
complement
We said numbers are unsigned. What does this mean?
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46
Negative Numbers
Adder-Subtractor
Computers Represent Information in ‘0’s and ‘1’s
I.
II.
III.
By using 2’s complement approach
we were able to get rid of the design
of a subtractor.
Need only adder and complementer
for input to subtract
Need selective complementer to
make negative output back from 2’s
complement
● ‘+’ and ‘−’ signs have to be represented in ‘0’s and ‘1’s
3 Systems
● Signed Magnitude
● 1’s Complement
● 2’s Complement
All three use the left-most bit to represent the sign:
♦ ‘0’
positive
♦ ‘1’
negative
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44
Signed Binary Numbers
Selective 1’s Complementer?
First review signed representations
Signed magnitude
Left bit is sign, 0 positive, 1 negative
Other bits are number
0 0001001
+9
1 0001001
-9
When X = 0 we transfer
Y to output
2’s complement
1’s complement
Control
When X = 1 we
complement Y
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8
Signed Magnitude Representation
2’s Complement Representation
Magnitude is magnitude, does not change with sign
S
Positive numbers are represented in “Binary”
Magnitude (Binary)
(+3)10
( 0 0 1 1 )2
(−3)10
( 1 0 1 1 )2
0
Magnitude (Binary)
Negative numbers are represented in “2’s Comp.”
1
Sign Magnitude
Code (2’s Comp.)
(+3)10
(0 011)2
(−3)10
(1 101)2
There is 1 representation for ‘0’ 1’s Comp.
(+0)10
(−0)10
1111
(0 000)2
+
(0 000)2
1 0000
1
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52
1’s Complement Representation
2’s Complement Range
Positive numbers are represented in “Binary”
0
Magnitude (Binary)
+7
+6
+5
+4
+3
+2
+1
+0
−1
−2
−3
−4
−5
−6
−7
−8
4
2 = 16 Combinations
Negative numbers are represented in “1’s Comp.”
1
Decimal 2’s Comp.
4-Bit Representation
− 8 ≤ Number ≤ + 7
Code (1’s Comp.)
3
3
−2 ≤ Number ≤ + 2 − 1
(+3)10
(0 011)2
n-Bit Representation
(−3)10
(1 100)2
−2
n−1
≤ Number ≤ + 2
n−1
−1
There are 2 representations for ‘0’!!!!!!
(+0)10
(0 000)2
(−0)10
(1 111)2
0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000
50
Convert 2’s Complement to Decimal
1’s Complement Range
4
2 = 16 Combinations
− 7 ≤ Number ≤ + 7
3
3
−2 +1 ≤ Number ≤ +2 − 1
n-Bit Representation
−2
n−1
bit index
Decimal 1’s Comp.
4-Bit Representation
+1 ≤ Number ≤ +2
n−1
−1
+7
+6
+5
+4
+3
+2
+1
+0
−0
−1
−2
−3
−4
−5
−6
−7
0111
0110
0101
0100
0011
0010
0001
0000
1111
1110
1101
1100
1011
1010
1001
1000
6
5
4
3
2
1
0
bit weighting -27 26
25
24 23
22
21
20
Example
0
1
0
1
0
Decimal
7
0
bit weighting
0
64
+
16
7
6
5
4
3
-27
26
25
24
23
1
0
1
0
x-27
0x26
1x25
0x24
Example
Decimal
1
0x-27 1x26 0x25 1x24 0x23 0x22 1x21 0x20
bit index
1
-128
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+
32
+
+
2
=
2
1
0
22
21
20
1
1
1
0
1x23
1x22
1x21
8
+ 4
+ 2
82
0x20
=
-82
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9
Number Representations
Advantages/Disadvantages
4-Bit Example
Range
Unsigned
Binary
Signed
Magnitude
1’s Comp.
2’s Comp.
0 ≤ N ≤ 15
-7 ≤ N ≤ +7
-7 ≤ N ≤ +7
-8 ≤ N ≤ +7
0
Positive
Binary
Negative
0
Binary
1
X
Binary
☺
0
Binary
i.e arithmetic operations are easy
Binary
1
1
1’s Comp.
2’s Comp.
Signed magnitude has problem that
we need to correct after subtraction
One’s complement has a positive
and negative zero
Two’s complement is most popular
55
58
Signed Magnitude Representation
Example in 8-bit byte
Magnitude is magnitude, does not change with sign
S
Represent +9 in different ways
Signed magnitude
1’s Complement
2’s Complement
00001001
00001001
00001001
(+3)10
Same!
( 0 0 1 1 )2
( 1 0 1 1 )2
Sign Magnitude
Can’t include the sign bit in ‘Addition’
0 0 1 1 (+3)10
Represent -9 in different ways
Signed magnitude
1’s Complement
2’s Complement
(−3)10
The
Magnitude (Binary)
10001001
11110110
11110111
+ 1011
(−3)10
1110
(−6)10
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56
Observations
Signed Magnitude Representation
The signed-magnitude system is used in
ordinary arithmetic, but is awkward
when employed in computer arithmetic
(Why?)
All positive
numbers are the
same
1’s Comp and
Signed Mag have
two zeros
2’s Comp has more
negative than
positive
All negative
numbers have 1 in
high-order bit
1.
2.
Therefore the signed complement (1’s
complement and 2’s complement
number representations) is normally
used.
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We have to separately handle the sign
Perform the correction if necessary!!
60
10
Binary Subtraction Using 2’s Comp. Addition
Signed Magnitude Arithmetic
Complex Rules!!
The addition of two numbers M+N in the sign
magnitude system follows the rules of ordinary
arithmetic:
Change “Subtraction” to “Addition”
If the signs are the same, we add the two magnitudes and
give the sum the sign of M.
If the signs are different, we subtract the magnitude of N
from the magnitude of M.
The absence or presence of an end borrow then determines:
The sign of the result.
Whether or not a correction is performed.
Example: (0 0011001) + (1 0100101)
0011001 – 0100101 = 1110100
End borrow of 1 occurs,
M < N!!
Sign of result should be that of N,
Also correct result by taking the 2’s complement of result
If “Carry ” = 1
ignore it, and the
result is positive
(in Binary )
If “Carry ” = 0
then the result
is negative
(in 2’s Comp .)
(5)10 – (1)10
(5)10 – (6)10
(+5)10 + (-1)10
(+5)10 + (-6)10
0101
+ 1111
0101
+ 1010
1 0100
0 1111
+4
−1
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61
Binary Subtraction Using 1’s Comp. Addition
Examples from Book
Change “Subtraction” to “Addition”
If “Carry ” = 1
then add it to the
LSB, and the result
is positive
(in Binary )
The numbers below should be in 2’s comp representation
(5)10 – (1)10
(5)10 – (6)10
(+5)10 + (-1)10
(+5)10 + (-6)10
Addition
0101
+ 1110
0101
+ 1001
1 0011
+
0 1110
(+6)
(-6)
(+6)
(-6)
0100
1110
+4
−1
If “Carry ” = 0
then the result
is negative
(in 1’s Comp .)
13
13
(- 13)
(-13)
Subtraction
(-6) - (-13)
(+6) - (-13)
62
Two’s Complement
65
Addition of Two Positive Numbers
To Add:
Addition
Easy on any combination of positive
and negative numbers
To subtract:
Also easy!
Take 2’s complement of subtrahend
Add
This performs A + ( -B), same as A – B
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+
+
+
+
(+6) + 13 = +19
00000110
+6
+00001101
+13
-------------00010011
+19
If a carry out appears it should be
discarded.
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11
Circuit for 2’s complement Numbers
Addition of :
a Positive and Negative Numbers
Addition
(-6) + 13 = +7
11111010 (this is 2’s comp of +6)
+00001101
-------------1 00000111
The carry out was discarded
No Correction is needed if the signed numbers
are in 2’s complement representation
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70
Subtraction of Two Numbers
Sign Extension
The subtraction of two signed binary
numbers (when negative numbers are in
2’s complement form) can be
accomplished as follows:
1.
2.
3.
Sign extension is the operation, in computer arithmetic,
of increasing the number of bits of a binary number while
preserving the number’s sign (positive/negative) and
value.
This is done by appending digits to the most significant
side of the number
Examples:
2’s complement (6-bits
8-bits)
Take the 2’s complement of the subtrahend
(including the sign bit)
Add it to the minuend.
A Carry out of the sign bit position is
discarded.
00 1010
0000 1010
2’s complement (5-bits
10001
8-bits):
1111 0001
68
Overflow
Subtraction of Two Numbers
In order to obtain a correct answer when
adding and subtracting, we must ensure
that the result has a sufficient number
of bits to accommodate the sum.
If we start with two n-bit numbers and we
end up with a number that is n+1 bits, we
say an overflow has occurred.
Subtraction
(+6) – (+13) = -7
00000110
00000110
- 00001101
+ 11110011 (2’s comp)
-----------------------11111001
What is 11111001?
Take its 2’s complement=>
The magnitude is 7
So it must be -7
00000111
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12
Overflow
Circuit for Overflow Detection
Condition is that either Cn-1 or Cn is
high, but not both
Two cases of overflow for addition of
signed numbers
Two large positive numbers overflow into
sign bit
Not enough room for result
Two large negative numbers added
Same – not enough bits
Carry out can be OK
73
Examples
76
Recall: Arithmetic -- multiplication
Two signed numbers +70 and +80 are stored in
8-bit registers.
The range of binary numbers, expressed in
decimal, that each register can accommodate is
from +127 to -128.
Since the sum of the two stored numbers is 150, it
exceeds the capacity of an 8-bit register.
The same applies for -70 and -80.
1 0 1 1
X
1 0 1
1 0 1 1
0 0 0 0
1 0 1 1
1 1 0
1 1 1
74
Overflow Detection
Multiplier
Carries: 0 1
Carries: 1 0
+70
0 1000110
-70
1 0111010
+80
0 1010000
-80
1 0110000
--------------------------------+150
1 0010110
-150 0 1101010
1.
The addition of +70 and +80 resulted in a negative
number!
2.
The addition of -70 and -80 also resulted in an
incorrect value which is positive number!
3.
An overflow condition can be detected by
observing the carry into the sign bit position
and the carry out of the sign bit position.
4.
If the the carry in and carry out of the sign
bit are not equal an overflow has occurred.
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Multiply by doing single-bit multiplies and shifts
Combinational circuit to accomplish this?
78
13
Combinational Multiplier
AND
computes
A0 B0
Half adder
computes
sum. Will
need FA for
larger
multiplier.
79
Larger Multiplier: Resources
Carry Look ahead Adder
For J multiplier bits and K multiplicand
bits we need
o
o
JxK
AND gates
(J-1) K-bit
adders to produce a
product of J+K bits.
Note that add itself just 2 level
Idea is to separate carry from adder
function
Then make carry approx 2-level all way
across larger adder
80
83
Larger Multiplier
One-bit Subtractor
Inputs:
A k=4-bit by j=3-bit
Binary Multiplier.
Borrow in,
minuend
subtrahend
Outputs: Difference, borrow out
Truth Table?
J=3
K=4
Jxk = 12 AND Gates
(J-1) Adders
S
1-bit sub
Bin
D
Of k bits each
81
School of Engineering
M
Bout
84
14
Correcting Result
Borrow
1
Minuend
Subtrahend
1
1
-
Difference
1
0
0
0
Correcting Result
0
1
1
1
1
1
1
0
1
0
1
0
1
What, mathematically, does it
mean to borrow?
It means that M < N
If borrowing at digit i-1 you are
adding 2i
100000
-
10101
01011
85
Correcting Result
88
Designs Aren’t Like This
If M is minuend and N subtrahend of
numbers length n, difference was
(2n + M) – N
What we want is magnitude of N-M with
minus sign in front
We can get the correct result by
subtracting previous result from 2n
That’s why people use complemented
interpretation for signed numbers
2’s complement
1’s complement
N - M = 2n – (M – N + 2n)
86
Interpretation of the incorrect result
Borrow
1
Minuend
Subtrahend
Difference
-
1
1
0
0
100000
2’s Complement
25
+ 10011 M
1
0
0
1
1
1
1
1
1
0
- 11110
1
0
1
0
1
10101
89
100000
-
10101
N
01011
The 2’s complement of 10101 is 01011
(2n + M) – N
The circuit that performs this is a complementer
87
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90
15
1’s Complement
Four-bit Carry Look Ahead Reference
Given: binary number N with n digits
1’s complement defined as
Adder function
separated from
carry
(2n – 1) - N
Note that (2n – 1) is number with n
digits, all of them 1
For n = 4, (2n – 1) = 1111
Notice adder has A, B, C in
and S out, as well as G,P out.
91
2’s Complement
94
BCD Addition
A3
Given: binary number N with n digits
2’s complement defined as
B3
CO FA
2n – N for N ≠ 0
0 for N = 0
CI
S
Exception is so that the result will always
have n bits
2’s complement is just a 1 added to 1’s
complement
11XX
A2
1X1X
B2
CO F A
S3
CI
A1
B1
CO FA
CI
A0
CI
CO FA
S
S
S2
S1
ENG241/Digital Design
B0
CO FA
S
S
CO F A
Cout
92
A1
A2
CI
Cin
S
CI
0
S0
95
Still Remember?
Unsigned Arithmetic Subtraction
Minuend
0 0 1
No borrows
1 0 1 1 0
-
1 0 0 1 0
0 0 1 0 0
Subtrahend
1
1 1 1 1 0
-
Borrows
1 0 0 1 1
0
1 0
1
1
0 - 1 results in a borrow
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