Dr. Cherif Salama
Faculty of Media Engineering
and Technology
CSEN 402 Computer Organization
and System Programming
Summer 2014
Assignment 1
Deadline: Monday, August 11, 2014
To be submitted as a hard copy at the office of your own TA
Exercise 1:
Represent the following conditional control statement by two register transfer statements
with control functions:
If (T = 0) then (R1 ← R2) else if (Y=1 and Z= 1) then (R1 ← R3+R2)
Solution:
T’: R1 ← R2
TYZ: R1 ← R3+R2
Exercise 2
Draw a block diagram for the hardware that implements the following statement. Include
the logic gates for the control function. Assume that registers are connected point to point
and not through a common bus.
X’T0 + yT2: R3 ← 0, R2← R2 - R3
If the values stored in the Registers just before this clock cycle as follows: R1 = 9, R2 =
7, R3 = 3. State the values stored in the Registers by the end of the clock cycle
represented by the above RTL statement.
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Solution:
X
T0
R3
R2
LD
CLR
Y
n
n
T2
1
Cin
n-bit adder
n
The values stored by the end of the clock cycle as follows:
R1 = 9
R2 = 4
R3 = 0
Exercise 3:
A digital computer has a common bus system for 24 registers of 8 bits each.
3-1) If the bus is constructed with multiplexers.
a. How many multiplexers are there in the bus?
b. What size of multiplexers is needed?
c. How many selection inputs are there in each multiplexer?
3-2) If the bus is constructed with three state buffers
a. How many three state buffers are needed?
b. How many decoders are needed?
c. What is the size of decoders needed?
Solution:
3-1) If the bus is constructed with multiplexers.
a. 8 multiplexers, one for each bit of the registers.
b. 32 × 1 multiplexers.
c. 5 selection lines to select one of 24 registers.
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Exercise 4:
Design an arithmetic circuit with one selection variable S and two three-bit data inputs A
and B, the circuit generates the following arithmetic operations: assuming that the Cin
of the full adder for the least significant bit is in all cases zero:
S
0
1
Operation
Output = A + B’
Output = A – 1
Solution:
S
C0
A0
B0’
1
0
1
S
2×1 MUX
X0
Y0
FA
Output0
C1
C1
A1
B1’
1
0
1
S
2×1 MUX
X
C1
FA
Output1
Y1
C2
C2
1
C
Exercise 5:
a. Starting from an initial value of R = 01110001, determine the sequence of binary
values in R after a circular shift-right, followed by a logical shift left, followed by
a logical shift right and a circular shift right.
b. Starting from an initial value of R = 11010011, determine the binary value of R
after an arithmetic shift right, followed by an arithmetic shift left. State whether
an overflow occurs or not.
Solution:
a. R = 01111001
Circular shift-right: 10111100
Logical shift left: 01111000
Logical shift right: 00111100
Circular shift right: 00011110
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b. R = 11000011
Arithmetic shift right: 11100001
Arithmetic shift left: 11000010, No overflow, the number was a negative number
and remained negative.(sign bit didn’t change).
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