RM0345
Reference manual
SPC563M64CAL144
calibration adapter board for SPC563M64xx devices
Introduction
The SPC563M64CAL144 (rev.B) system is designed to enable the use of new enhanced
automotive calibration and debug tools on the SPC563M64xx family of automotive
microcontrollers.
The SPC563M64CAL144 (rev.B) can be fitted onto the application printed circuit board
(PCB) in place of the standard SPC563M64xx family microcontroller in LQFP144 package.
SPC563M64CAL144 (rev.B) hardware is designed to support two standardized tool
connectors, allowing a variety of calibration and debug hardware to be connected and
reused
Figure 1.
SPC563M64CAL144 (rev.B)
*$3*5,
Table 1.
September 2013
Board summary
Order code
On board device
Target footprint
SPC563M64CAL144
SPC563M64xx
QFP144
Doc ID 024080 Rev 3
1/38
www.st.com
Contents
RM0345
Contents
1
Calibration system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Features overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Reset and configuration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Calibration bus interface and External Memory . . . . . . . . . . . . . . . . . . 12
4.1
External memory specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
SRAM supply and data retention function . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Calibration bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
Development connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6
Calibration connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Tool IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
Calibration software compatibility and configuration . . . . . . . . . . . . . 22
9.1
9.2
Calibration bus sw configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.1
Cal Bus PCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9.1.2
Cal Bus ECCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9.1.3
Cal Bus EBI Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Example Configuration CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Appendix A Calibration base footprints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Appendix B Mechanical constrains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Appendix C Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Appendix D Options placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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RM0345
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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List of tables
RM0345
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
4/38
Board summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
J15, J2 and J14 option cut traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset and configuration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
J11 configuration of SRAM supply for retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
J3, J5 and J10 option cut traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Nexus signals on AMP 38 Mictor connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Nexus signals on AMP 38 Mictor connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
J12, J13 FlexCAN interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
J6, J17 and J7 FlexCAN interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
CAN transceiver operating voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Calibration bus signals configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
EBDF field definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
EBI_MCR register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
EBI_CAL_BRx register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
EBI_CAL_BOx register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 024080 Rev 3
RM0345
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
SPC563M64CAL144 (rev.B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Supply signals from the QFP144 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Test points on J4 connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Supply signals on SPC563M64xx CSP496 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SRAM supply circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SRAM schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
JP1 development connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
AMP 38 Mictor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
J9 Calibration connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Calibration triggers TOOL_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
CAN schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TQPACK144SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Top and side view drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Side and bottom view drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Complete system side view drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SPC563M64xx in CSP package schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Polypod-TQ144 connector schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Memory, CAN and connectors schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Options placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Calibration system overview
1
RM0345
Calibration system overview
The Calibration Adapter board features 2 Mbytes of SRAM in order to substitute to the
SPC563M64xx internal Flash during calibration.
A voltage regulator is also integrated upon the board to generate, from selectable 5 V
source, the 3.3 V voltage for the RAM and the calibration bus interface.
Development connector (Mictor AMP38) is providing the interface for the debug and trace
tools.
A calibration connector (ERNI 154819) is providing an interface optimized for calibration
usage.
A high speed CAN transceiver is connected to the FlexCAN of the mcu device.
The components chosen in the design of this board are automotive qualified to allow system
evaluation over the full automotive evaluation range (-40 °C to 125 °C).
1.1
Features overview
calibration systems include these distinctive features:
6/38
●
Use 100% production silicon, ensuring full hardware and software compatibility
between production and calibration systems;
●
Support LQFP144 MCU production package allowing calibration systems to be built
without requiring modifications to the standard production system housing;
●
2MByte static RAM organized as 1024K words by 16 bits;
●
On-board latch providing a 16-bit de-multiplexed bus interface from the SPC563M64xx
16-bit multiplexed calibration interface;
●
Support for Nexus-based debug tools even if application PCB does not include Nexus
connector;
●
Nexus functionality with 12 Message Data Out (MDO) signals;
●
Support for full-feature calibration tools, via availability of comprehensive set of device
signals available on the connectors;
●
ERNI 154819 connector optimized for calibration;
●
High speed CAN transceiver with signals protection;
●
Allows system calibration without impacting standard MCU I/O resources;
●
Allows system calibration regardless of availability of standard MCU external bus;
●
Uses tried and tested technology.
Doc ID 024080 Rev 3
RM0345
Power supply
The Calibration boards requires a +5 V to supply the on board CAN transceiver and a
+3.3 V to supply the SPC563M64xx calibration bus interface and for the external RAM.
The 3.3 V supply is generated on the SPC563M64CAL144 (rev.B) via the very low drop
voltage regulator by using the +5V. A LED (D1) will light when the board is powered.
Power supply
5
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2
Power supply
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*$3*5,
By default the 5V is taken from the target application through the VDDREG supply level
(supply input for the internal voltage regulators of the SPC563M64xx). Gauge J14 enables
the powering from the application board. Table 2 shows its option configuration.
In case that no additional power loading could be applied to the application system during
calibration, the +5V can be supplied externally via J4 connector (+5V test point, see
Figure 4) and the gauge J14 (see Figure 3) must be open.
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Power supply
RM0345
QFP144 footprint
Figure 3.
Supply signals from the QFP144 footprint
VDDEH1.A
VDDEH1B
VDDEH1
C
VDDE
H1B
VDDEH
VDDE
H6A4
VDDEH6A
VDDEH6B
VDDEH7
VDDEH7
VDDPLL
VDDREG
VRC33
VRCCTL
VSSPLL
VSSA0
VSTBY
VDDA0
VSUP
24
VDDEH1A
34
VDDEH1B
46
61
VDDEH6A
78
93
VDDEH6B
102
VDDEH7
113
74
VDDSYN
10 VDDREG
13
11 VRCCTL
77
7
12 VSTBY
6
VDDA0
79
+5V
J14
Default = CLOSE
J15
Default = CL
C46
1uF
VSSA VSSSYN
GND
GND
GAPGRI00341
Figure 4.
Test points on J4 connector
-
9
9
9' '
&21
*1'
*$3*5,
All power signals and voltage references of the SPC563M64xx QFP144 footprint from the
application board are directly connected to the respective calibration device signals.
The VDDE12 supply used to power the dedicated SPC563M64xx calibration bus interface is
connected to the upon board +3.3 V voltage regulator.
8/38
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RM0345
'
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+
-
/
/
/
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0
1
3
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9''(+
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Supply signals on SPC563M64xx CSP496
0
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9
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7
.
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Power supply
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The VRC33 signal of the CSP496 is connected to its respective signal of the QFP144 target
application via the J15 cut trace option.
The VRC33 can be also connected to the on board +3.3V by closing the J2 gauge. In this
case the gauge J15 must be open (Table 2).
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Power supply
RM0345
Table 2.
Option
name
J15, J2 and J14 option cut traces(1)
Function
Value
open
J15
J2
VRC33
VRC33
VRC33 signal is connected to the target
application board
open
(default)
VRC33 signal is disconnected from the on board
+3.3V signal
open
+5V supply
VRC33 signal is disconnected from the target
application board
close
(default)
close
J14
Note
close
(default)
VRC33 signal is connected to the on board
+3.3V signal
+5V is powered from J4 connector
+5V is powered from target application via
VDDREG pin of the QFP144 target footprint
1. Refer to Chapter Appendix D: Options placement for layout Jumper placement
10/38
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RM0345
3
Reset and configuration signals
Reset and configuration signals
Calibration and debug tools may use the reset signals included in the connectors to have
visibility of when the SPC563M64xx device has been reset. Debug tools may also require
the ability to force device reset.
All signals of the SPC563M64xx QFP144 footprint from the application board are directly
connected to the respective calibration device signals. This includes the following signals on
the Table 3.
Table 3.
Reset and configuration signals
Signal name
Function
Notes
Reset / Configuration (5)
/RESET
/RSTOUT
BOOTCFG[1]
PLLREF
WKPCFG
External reset input
The /RESET pin is an active low input. The
RESET pin is asserted by an external device
during a power-on or external reset. The
internal reset signal asserts only if the RESET
pin asserts for 10 clock cycles. Assertion of
the RESET pin while the device is in reset
causes the reset cycle to start over.
External reset output
The RSTOUT pin is an active low output that
uses a push/pull configuration. The RSTOUT
pin is driven to the low state by the MCU for all
internal and external reset sources. There is a
delay between initiation of the reset and the
assertion of the RSTOUT pin.
Boot configuration input
The BOOTCFG field holds the value of the
BOOTCFG[1] pin that was latched on the last
negation of the RSTOUT pin. The BOOTCFG
field is used by the BAM program to
determine the location of the Reset
Configuration Word.
FMPLL Mode Selection
PLLREF is used to select whether the
oscillator operates in xtal mode or external
reference mode from reset.
If RSTCFG is 0, External reference clock
selected.
If RSTCFG is 1, Xtal oscillator mode is
selected
Weak Pull Configuration
The signal on the WKPCFG pin determines
whether weak pull up or pull down devices are
enabled after reset on the eTPU and eMIOS
pins.
0: Weak pulldown applied to eTPU and
eMIOS pins at reset
1: Weak pullup applied to eTPU and eMIOS
pins at reset.
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Calibration bus interface and External Memory
4
RM0345
Calibration bus interface and External Memory
The SPC563M64xx features a 16-bit de-multiplexed calibration bus interface that is
connected to an external 2Mbyte SRAM thanks to an on board latch.
4.1
External memory specification
The
calibration board provides a SRAM with the following characteristics:
–
2Mbyte static RAMs organized as 1024K words by 16 bits;
–
16-bit data width;
–
Fully static operation: no clock or refresh required;
–
3.3V input supply;
–
/CE power-down;
–
High-speed access time (10ns);
–
Full automotive temperature range;
–
Lead-free.
When /CE is HIGH (deselected), the device assumes a standby mode at which the power
dissipation can be reduced down with CMOS input levels.
4.2
SRAM supply and data retention function
The circuitry in Figure 6 has been implemented on the calibration board to protect the
memory and to guarantee that the Working Page is valid after a power fail of the target
application by putting the SRAM in standby powered.
The 3.3 V supply of the SRAM (Vmem) is gated by the RESET and RSTOUT signals of the
SPC563M64xx.
The memory enable is driven via the SPC563M64xx chip select C_CS0 “and” the RESETs
signals combination.
12/38
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RM0345
Calibration bus interface and External Memory
SRAM supply circuitry
R1
+5V
U2
1
330
C34
C35
4.7uF
100n
OUT
STT5PF20V
Vmem
3
C31
C36
C37
2.2uF
100n
Q1
2
D1
LED
+3.3V
LF33CDT-TRY
IN
GND
Figure 6.
1uF
GND
GND
5
Vmem
/RSOUT
2
/RESET
1
U7
4
3
74V1G00CTR
GND
5
Vmem
U8
2
4
/CE_RAM
1
74V1G32CTR
3
/CS0
GND
ECU_Vstby
1
+3.3V
2
3
J11
D2
20CJQ060
VSTBY
GAPGRI00344
The jumper J11 (see Figure 6) allows to select the standby operation of the SRAM.
The standby voltage can be selected between:
●
SPC563M64xx Vstby pin: same standby voltage as the internal RAM;
●
the 3.3V generated on the
●
ECU_Stby supplied by the calibration connector J9 (see Figure 10).
Table 4.
calibration board;
J11 configuration of SRAM supply for retention mode
J11
SRAM standby supply source
all open
ECU_Stby: standby voltage on J9 calibration connector
1-2 closed
Upon the board +3.3V generated
2-3 closed
VSTBY input pin of the SPC563M64xx from the target application
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Calibration bus interface and External Memory
4.3
RM0345
Calibration bus interface
The calibration bus is made up of address bus, data bus, and bus control signals, and is
used on the calibration board to access the upon board memory.
The calibration board supports a 16-bit de-mulitplexed calibration bus. This is derived from
the multiplexed bus on the SPC563M64xx, where the majority of address lines are derived
from the data lines (CAL_DATA on SPC563M64 device), by using an onboard external latch
controlled by the C_TS signal. The ALE functionality of this signal indicates to the external
latch when to capture the address signals
Figure 7.
SRAM schematic diagram
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/DWFKB4
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/DWFKB4
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/DWFKB4
/DWFKB4
/DWFKB4
/DWFKB4
/DWFKB4
/DWFKB4
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/DWFKB4
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The Section 9: Calibration software compatibility and configuration shows the necessary
software configuration of the SPC563M64xx calibration interface.
14/38
Doc ID 024080 Rev 3
RM0345
Development connector
The JTAG signals and Nexus functionality with 12 Message Data Out (MDO) signals are
available on the JP1 development connector (Nexus connector).
A hardware control bit in the SPC563M64xx Nexus port controller, is used to control whether
the added signals for full width trace port are routed to the MDO[4:11] signals, or the
CAL_MDO[4:11] signals. This control bit is set by the cut trace J1 (default close) on the
NEXUSCFG pin of the SPC563M64xx device, as on the calibration board the
CAL_MDO[4:11] signals are routed to the JP1 development connector.
JP1 development connector
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The option cut trace J3, J5 and J10 are listed on Figure 5.
Table 5.
option
name
J3
J5
J3, J5 and J10 option cut traces
Function
CLKOUT
VSTBY
Value
Note
open
CLKOUT signal is disconnected to the Nexus JP1
connector
close
(default)
CLKOUT signal is connected to the Nexus JP1
connector
open
VSTBY signal is disconnected to the Nexus JP1
connector
close
(default)
open
J10
BOOTCFG1
close
(default)
VSTBY signal is connected to the Nexus JP1
connector
BOOTCFG1 signal is disconnected to the Nexus
JP1 connector
BOOTCFG1 signal is connected to the Nexus
JP1 connector
Doc ID 024080 Rev 3
15/38
Development connector
RM0345
Figure 6 shows the mapping of the development connector that provides Debug, Nexus
trace and calibration signals. The port connector is an AMP 38 pin Mictor style.
Figure 9.
AMP 38 Mictor
SLQQ
*$3*5,
Table 6.
Nexus signals on AMP 38 Mictor connector
Pin
Description
Pin
Descriptio
1
nc
2
nc
3
nc
4
nc
5
C_MDO9
6
CLKOUT*
7
BOOTCFG1*
8
C_MDO8
9
/RESET
10
C_EVTI
11
TDO
12
+3.3V
13
C_MDO10
14
RDY
15
TCK
16
C_MDO7
17
TMS
18
C_MDO6
19
TDI
20
C_MDO5
21
JCOMP
22
C_MDO4
23
C_MDO11
24
C_MDO3
25
nc
26
C_MDO2
27
10K pull down resistor
28
C_MDO1
29
TOOL_IO1
30
C_MDO0
31
VDDEH1A
32
C_EVTO
33
VDDEH1A
34
C_MCKO
35
TOOL_IO0
36
C_MSEO1
37
VSTBY*
38
C_MSEO0
*) signal is connected via cut trace option
16/38
Doc ID 024080 Rev 3
RM0345
6
Calibration connector
Calibration connector
The board is equipped with an ERNI connector to give a more robust solution in terms of
physical connectivity for Calibration purpose.
Figure 10. J9 Calibration connector
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calibration signals. The port connector is an ERNI 154819 style.
Table 7.
Nexus signals on AMP 38 Mictor connector
Pin
SPC563M64xx
routing
standard function
Pin
SPC563M64xx
routing
standard function
B1
nc
nc
A1
nc
nc
B2
nc
nc
A2
JCOMP
JTAG interface
B3
/RSOUT
/RSOUT
A3
CAL Wakeup
12V output for Wakeup
functionality
B4
GND
GND
A4
C_EVTI
JTAG interface
B5
GND
GND
A5
TDO
JTAG interface
B6
GND
GND
A6
TMS
JTAG interface
B7
GND
GND
A7
TCK
JTAG interface
B8
GND
GND
A8
TDI
JTAG interface
B9
GND
GND
A9
Vmem
VDDSBRAM (Backup
Voltage of ECU
Standby RAM)
B10
/RESET
/RESET
A10
nc
nc
B11
GPIO[207]
(@3.3V)
GPIO Pins for startup
handshake and
triggering
A11
RSVDx
reserved Input,
connect pin to a solder
pad
Doc ID 024080 Rev 3
17/38
Calibration connector
Table 7.
Nexus signals on AMP 38 Mictor connector (continued)
Pin
SPC563M64xx
routing
standard function
B12
GPIO[207]
(@3.3V)
GPIO Pins for startup
handshake and
triggering
ECU_Vsby
VDDSBRAM Supply
(Backup Voltage of
ECU Standby RAM)
B13
18/38
RM0345
Pin
SPC563M64xx
routing
standard function
A12
MDO 0
Detect that the PLL is
locked
+5V
VDDP Comparator
Input (Supply of
microcontroller
Interface Pins)
A13
Doc ID 024080 Rev 3
RM0345
Tool IO
The SPC563M64xx in CSP496 package provides 2 signals, GPIO[206] & GPIO[207], that
are not available in the QFP144 standard production package. They can be used by the
calibration tools to implement triggers and handshakes. On the calibration board, these
signals are available on the JP1 development connector and J9 calibration connector.
By default GPIO[206] & GPIO[207] are powered by VDDEH at 5V. A level shifter (see
Figure 11) does the translation between the 5v and the 3.3V. This is because the calibration
tools operates at 3.3V that is the voltage level of the JTAG and Nexus interfaces.
Calibration triggers TOOL_IO
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Doc ID 024080 Rev 3
19/38
CAN interface
8
RM0345
CAN interface
The calibration board is equipped with one ST L9616 High-Speed Transceiver. It provides
the Controller Area Network (CAN) communication interface through the SPC563M64xx
CAN interface for calibration via CAN. This serial communication can reach speeds up to
1Mbps.
Figure 12. CAN schematic diagram
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Two jumpers (J12 and J13), allow to select between the two FlexCAN interfaces of the
SPC563M64xx mcu.
Table 8.
J12, J13 FlexCAN interface selection
J12 pin configuration
J13 pin configuration
TX select
RX select
FlexCAN A
2-3
2-3
FlexCAN C
2-1
2-1
FlexCAN interface
The CAN channel is terminated with a 120 ohms resistor. Moreover, a protection circuitry
has been designed to protect the CAN transceiver in high-speed and fault tolerant networks
from ESD and other harmful transient voltage events (see Figure 12).
The L9616 CAN transceiver has an Adjustable Slope Control (ASC) feature that sets the
slope speed using its ASC pin. This feature select the modes of operation:
●
low speed (CAN baud rate up to 250kBaud)
●
high speed (CAN baud rate from 250kBaud to 1000kBaud)
This pin can be put to high or to low by the cut trace options J6, J17 & J7 as described in
Table 9.
20/38
Doc ID 024080 Rev 3
RM0345
CAN interface
Table 9.
J6, J17 and J7 FlexCAN interface selection
J6 (or J17 if 3.3V)
J7
FlexCAN interface
closed
open
low speed operation (default)
(CAN baud rate up to 250kBaud)
open
closed
high speed operation
(CAN baud rate from 250kBaud to 1000kBaud)
The cut trace options J6, J17, J18 and J19 has been put in the design of this board to select
the supply of the CAN transceiver between 5 V and 3.3 V. By this option is possible to
replace the ST L9616 High-Speed Transceiver mounted on board by default, with a different
transceiver that operates at 3.3 V.
Table 10.
Note:
CAN transceiver operating voltage selection
CAN Transceiver
J6
J17
J18
J19
5V - ST L9616 High-Speed
Transceiver
Adjustable
Slope Control
open
open
close
3.3V - CAN transceiver
open
Adjustable
Slope Control
close
open
Refer to Section Appendix D: Options placement for layout options placement.
Doc ID 024080 Rev 3
21/38
Calibration software compatibility and configuration
9
RM0345
Calibration software compatibility and configuration
The calibration board uses standard production silicon packaged in the CSP (Chip Scale
Package). Therefore, all production silicon features exist and are identical on the calibration
board.
The required initialization code may be as simple as the configuration of the EBI and its
related pins in the SIU, and it could be integrated into standard application software.
The calibration bus and the SIU can also be configured by an external tool connected to the
debug port, removing the need of specific configuration functions in the application software.
9.1
Calibration bus sw configuration
A 16-bit calibration bus is implemented on the board. In multiplexed mode the CAL_DATA
signals will output the address signals during the address phase by using an onboard
external latch controlled by the CAL_TS signal. The CAL_ALE may be used to drive an
external latch when an asynchronous memory is in use.
There are few steps to configure the SPC563M64xx Calibration Bus
9.1.1
–
SIU PCR (Pad Configuration Register)
–
SIU ECCR (External Clock Control Register)
–
External Bus Interface (EBI)
Cal Bus PCR Settings
The SIU PCR registers used to configure the calibration bus are shown in theTable 11 The
table also shows the recommended PA field setting.
Table 11.
Calibration bus signals configuration
signal name
SPC563M64xx
mcu signal name
Function
P
A
G
PCR
PA
field
(1)
(2)
PCR
(3)
Address/Data Bus (44)
C_DATA[0:15]
CAL_DATA[0:15]
Calibration
data bus
-
-
341
C_ADDR[12:15]
CAL_ADDR[12:15]
Calibration
address bus
-
-
340
C_ADDR[16:31]
CAL_ADDR[16:31]
Calibration
address bus
-
-
345
C_CS[0]
CAL_CS[0]
Calibration
chip select
-
-
336
C_CS[1]
Not Connected
CAL_CS[2]
Calibration
chip select
P
1
CAL_ADDR[10]
Calibration
address bus
A
0
C_CS[2]
22/38
Doc ID 024080 Rev 3
338
Notes
RM0345
Calibration software compatibility and configuration
Table 11.
Calibration bus signals configuration (continued)
signal name
SPC563M64xx
mcu signal name
Function
P
A
G
PCR
PA
field
(1)
(2)
PCR
CAL_CS[3]
Calibration
chip select
P
1
CAL_ADDR[11]
Calibration
address bus
A
0
C_OE
CAL_OE
Calibration
Output enable
-
-
342
C_RD_WR
CAL_RD_WR
Calibration
Read/write
-
-
342
C_WE[0:1]
CAL_WE[0:1]
Calibration
write/byte
enable
-
-
342
CAL_TS
Calibration
transfer start
P
1
CAL_ALE
Address Latch
enable
A
0
P
01
C_CS[3]
C_TS
Notes
(3)
339
343
Clock Synthesizer (1)
C_CLKOUT
Note:
9.1.2
System clock
output
CLKOUT
229
Clock output
signal from MCU
1
The P/A/G column indicates the position a signal occupies in the muxing order for a pin:
Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO. Signals are selected by setting the
PA field value in the appropriate PCR register in the SIU module. The PA field values are as
follows: P - 0b0001, A1 - 0b0010, A2 -0b0100, A3 - 0b1000, or G - 0b0000. Depending on
the register, the PA field size can vary in length. For PA fields having fewer than four bits,
remove the appropriate number of leading zeroes from these values.
2
The Pad Configuration Register (PCR) PA field is used by software to select pin function.
3
Values in the PCR No. column refer to registers in the System Integration Unit (SIU). The
actual register name is “SIU_PCR” suffixed by the PCR number.
Cal Bus ECCR Settings
The SIU ECCR registers used to control the timing relationship between the system clock
and the external clock CLKOUT.
The external bus clock (CLKOUT) divider can be programmed to divide the system clock by
one, two or four based on the settings of the EBDF bit field.
Table 12.
EBDF field definition
Register
EBDF field
External Bus Division Factor
00
1
01
2
10
reserved
11
4
SIU_ECCR
Doc ID 024080 Rev 3
23/38
Calibration software compatibility and configuration
9.1.3
RM0345
Cal Bus EBI Settings
For using the calibration bus with an external memory the user must configure the bus for
multiplexed operation. These settings are located in two registers:
–
EBI Module Configuration Register (EBI_MCR)
–
EBI Calibration Base Register (EBI_CAL_BRx)
–
EBI Calibration Option Register (EBI_CAL_ORx)
The EBI Module Configuration Register contains bits which configure various attributes
associated with EBI operation. In the EBI_MCR register, the D16_31, AD_MUX and DBM
fields need to be configured.
Table 13.
bit
field
29
EBI_MCR register setting
Name
Description
D16_31
Data Bus 16_31 Select
The D16_31 bit controls whether the EBI uses the
DATA[0:15] or DATA[16:31] signals, when in 16-bit Data
Bus Mode (DBM=1) or for chip-select accesses to a 16bit port (PS=1).
value
0b0
1 = DATA[16:31] signals are used for 16-bit port accesses
0 = DATA[0:15] signals are used for 16-bit port accesses
30
31
AD_MUX
Address on Data Bus
Multiplexing Mode
DBM
Data Bus Mode
The AD_MUX bit controls whether non-chip-select
accesses have the address driven on (or sampled from
for external master transfers) the data bus in the address
phase of a cycle.
0b1
1 = Address on Data Multiplexing Mode is used for nonCS accesses.
0 = Only Data on data pins for non-CS accesses.
The DBM bit controls whether the EBI is in 32-bit or 16-bit
Data Bus Mode.
1 = 16-bit Data Bus Mode is used
0 = 32-bit Data Bus Mode is used
0b1
In the EBI_CAL_BRx register there are few fields that need to be configured, these are
detailed in the Table 14 .
24/38
Doc ID 024080 Rev 3
RM0345
Calibration software compatibility and configuration
Table 14.
bit
field
0-16
20
EBI_CAL_BRx register setting
Name
Description
value
BA
Base address
These bits are compared to the corresponding
unmasked address signals among ADDR[0:16] of the
internal address bus to determine if a memory bank
controlled by the memory controller is being accessed by
an internal bus master
Note: An MCU may have some of the upper bits of the
BA field tied to a fixed value internally in order to restrict
the address range of the EBI for that MCU. Refer to the
device-specific documentation to see which bits are tied
off, if any, for a particular MCU. Tied-off bits can be read
but not written. These bits are ignored by the EBI during
the chip-select address comparison. However, the
internal bridge of the MCU most likely requires that the
chipselect banks be located in memory regions
corresponding to the fixed values chosen
-
PS
Port Size
The PS bit determines the data bus width of transactions
to this chip-select bank.
Note: In the case where the DBM bit in EBI_MCR is set
for 16-bit Data Bus Mode, the PS bit value is ignored and
is always treated as a ’1’ (16-bit port).
0b1
1 = 16-bit port
0 = 32-bit port
24
AD_MUX
Address on Data Bus
Multiplexing
26
WEBS
Write Enable / Byte
Select
30
BI
Burst Inhibit
The AD_MUX bit controls whether accesses for this chip
select have the address driven on the data bus in the
address phase of a cycle
1 = Address on Data Multiplexing Mode is enabled for
this chip select.
0 = Address on Data Multiplexing Mode is disabled for
this chip select.
0b1
This bit controls the functionality of the WE[0:3]/BE[0:3]
signals.
1 = The WE[0:3]/BE[0:3] signals function as BE[0:3]
0 = The WE[0:3]/BE[0:3] signals function as WE[0:3]
This bit determines whether or not burst read accesses
are allowed for this chipselect bank. The BI bit is ignored
(treated as 1) for chip-select accesses with external TA
(SETA=1).
0b1
0b1
1 = Disable burst accesses for this bank. This is the
default value out of reset (or when SETA=1).
0 = Enable burst accesses for this bank]
Doc ID 024080 Rev 3
25/38
Calibration software compatibility and configuration
Table 14.
bit
field
31
RM0345
EBI_CAL_BRx register setting
Name
V
Valid bit
Description
The user writes this bit to indicate that the contents of
this Base Register and Option Register pair are valid.
The appropriate CS signal does not assert unless the
corresponding V-bit is set.
value
0b1
1: This bank is valid
0: This bank is not valid
The EBI Option Registers are used to define the address mask and other attributes for the
corresponding chip select.The SCY field of the EBI_CAL_BOx register is detailed in the
Table 15.
Table 15.
bit
field
0-16
24-27
29-30
26/38
EBI_CAL_BOx register setting
Name
Description
value
AM
Address Mask
This field allows masking of any corresponding bits in the
associated Base Register.
Masking the address independently allows external
devices of different size address ranges to be used. Any
clear bit masks the corresponding address bit. Any set
bit causes the corresponding address bit to be used in
comparison with the address pins.
Address mask bits can be set or cleared in any order in
the field, allowing a resource to reside in more than one
area of the address map. This field can be read or
written at any time.
-
SCY
Cycle length in clocks
This field represents the number of wait states (external
cycles) inserted after the address phase in the single
transfer case, or in the first beat of a burst, when the
memory controller handles the external memory access.
Values range from 0 to 15 and its depends on the RAM
connected on top board.
This is the main parameter for determining the length of
the cycle. These bits are ignored when SETA=1.
The total cycle length for the first beat (including the TS
cycle) = (2+SCY) external clock cycles.
-
BSCY
Burst beats length in
clocks
This field determines the number of wait states (external
cycles) inserted in all burst beats except the first, when
the memory controller starts handling the external
memory access and thus is using SCY[0:3] to determine
the length of the first beat.
These bits are ignored when SETA=1.
The total memory access length for each beat is (1 +
BSCY) external clock cycles.
The total cycle length (including the TS cycle) = (2+SCY)
+ (#beats(h)-1) * (BSCY+1).
-
Doc ID 024080 Rev 3
RM0345
9.2
Calibration software compatibility and configuration
Example Configuration CODE
The following code is used to configure the calibration bus for 16bit de-multiplexed mode.
//--------------------------------------------------// SIU PCR (Pad Configuration Register) setup
// (Cal BUS bommon drive strength = 20pF, DSC = 0b01)
//---------------------------------------------------
SIU.PCR[336].R = 0x0040;//CAL_CS[0]DSC=20pF (0b01)
SIU.PCR[338].R = 0x0440;//CAL_CS[2] (PA=0b1),DSC=20pF (0b01)
SIU.PCR[339].R = 0x0040;//CAL_ADDR[11] (PA=0b0), DSC=20pF (0b01)
SIU.PCR[340].R = 0x0040;//CAL_ADDR[12..15], DSC=20pF (0b01)
SIU.PCR[345].R = 0x0040;//CAL_ADDR[16..30], DSC=20pF (0b01)
SIU.PCR[341].R = 0x0040;//CAL_DATA[0..15], DSC=20pF (0b01)
SIU.PCR[342].R = 0x0040;//CAL_RD/WR, CAL_WE[0-1], CAL_OE, DSC=20pF
(0b01)
SIU.PCR[343].R = 0x0040;//CAL_ALE, DSC=20pF (0b01)
//-------------------------------------------------// SIU ECCR (External Clock Control Register) setup
//--------------------------------------------------
SIU.ECCR.R = 0x1000//External Bus Division Factor = 1 (EBDF=0b00)
//-------------------------------------------------// EBI Registers setup
//-------------------------------------------------//----------------------------------------------------------------// EBI MCR setup for 16-bit bus configuration:
//
// EARP = 01 (Equal priority);
// D16_31 = 0 (DATA[0:15] signals are used for 16-bit port accesses);
// AD_MUX = 1 (Addr on Data Multiplexing Mode is used for non-CS acc.);
// DBM = 0 (32-bit Data Bus Mode is used);
EBI.MCR.R = 0x802;
//-----------------------------------------------------// EBI Base Register setup for 16-bit bus configuration:
//
// Base Address = 0x20000000;
// PS = 1 (16-bits port size)
// AD_MUX = 1 (Address on Data Multiplexing Mode is enabled for this chip select);
// WEBS = 1 (Use BE function);
// BI = 1 (Disable burst accesses for this bank);
// V = 1 (Valid CS Bank)
EBI.CAL_CS[0].BR.R = 0x200008A3;
Doc ID 024080 Rev 3
27/38
Calibration software compatibility and configuration
//----------------------------------------// EBI Option Register setup:
//
// Address mask = 0xefe00000;
// Wait state = 0 (set 0 wait states);
EBI.CAL_CS[0].OR.R = 0xffe00000;
28/38
Doc ID 024080 Rev 3
RM0345
RM0345
Calibration base footprints
Appendix A
Calibration base footprints
SPC563M64CAL144 (rev.B) calibration board had footprint compatible with QFP144
production package version of SPC563M64xx devices, ensuring that they can be fitted to an
application PCB that has been designed to accept standard QFP144 packaged
SPC563M64xx devices.
Bases can be supplied with solder footprints, to allow direct and permanent soldered
connection to an application PCB, or with pin adapter connectors fitted, allowing connection
and removal from an application PCB that is fitted with a compatible receiver socket.
Figure 13. TQPACK144SD
DOOGLPHQVLRQDUHLQPP
all dimension are in mm
*$3*5,
Doc ID 024080 Rev 3
29/38
Mechanical constrains
Appendix B
RM0345
Mechanical constrains
Figure 14. Top and side view drawing
6OJUTNN
*$3*5,
30/38
Doc ID 024080 Rev 3
RM0345
Mechanical constrains
Figure 15. Side and bottom view drawing
3LQ
;
8QLWVPP
*$3*5,
Doc ID 024080 Rev 3
31/38
Mechanical constrains
RM0345
Figure 16. Complete system side view drawing
8QLWVPP
*$3*5,
32/38
Doc ID 024080 Rev 3
Doc ID 024080 Rev 3
+3.3V
1
TP1
1
R3
10K
J1
DEFAULT=CLOSE
G8
M3
L3
L2
H9
M2
K3
K2
G9
L5
J3
J2
G10
K5
H3
K1
H10
J5
G3
J1
H11
F3
H2
G2
H5
G5
E3
F1
F2
E1
E2
Y24
Y27
U26
V24
F26
E26
F27
E28
E27
JCOMP
TMS
TDO
TDI
TCK
MDO1
MDO0
MCKO
EVTO
EVTI
C24
C25
H26
G27
G26
NEXUSCFGG18
/MSEO1 H24
/MSEO0 G24
MDO3
C23
MDO2
B21
M26
N27
M27
T28
R28
R27
N28
P28
T27
PCS_B5
PCS_B4
PCS_B3
PCS_B2
PCS_B1
PCS_B0
SOUT_B
SIN_B
SCK_B
CNRX_C Y26
CNTX_C W24
CNRX_A AG22
CNTX_A AF22
RXD_B
TXD_B
RXD_A
TXD_A
EMIOS.0 AD17
EMIOS.1 AD21
EMIOS.2 P21
EMIOS.4 AD18
EMIOS.8 N21
EMIOS.9 AD23
EMIOS.10 N22
EMIOS.11AG18
EMIOS.12 M21
EMIOS.13 AF18
EMIOS.14AH19
EMIOS.15 M22
EMIOS.23 AF21
ETPUA.1
ETPUA.2
ETPUA.3
ETPUA.4
ETPUA.5
ETPUA.6
ETPUA.7
ETPUA.8
ETPUA.9
ETPUA.10
ETPUA.11
ETPUA.12
ETPUA.13
ETPUA.14
ETPUA.15
ETPUA.16
ETPUA.17
ETPUA.18
ETPUA.19
ETPUA.20
ETPUA.21
ETPUA.22
ETPUA.23
ETPUA.24
ETPUA.25
ETPUA.26
ETPUA.27
ETPUA.28
ETPUA.29
ETPUA.30
ETPUA.31
ETPUA.0.N5 N5
ETPUA.0.M5M5
NEXUSCFG
MSEO1
MSEO0
MDO3
MDO2
MDO1
MDO0
MCKO
EVTO
EVTI
JCOMP
TMS
TDO
TDI
TCK
PCSB5
PCSB4
PCSB3
PCSB2
PCSB1
PCSB0
SOUTB
SINB
SCKB
CNRXC
CNTXC
CNRXA
CNTXA
RXDB
TXDB
RXDA
TXDA
EMIOS0
EMIOS1
EMIOS2
EMIOS4
EMIOS8
EMIOS9
EMIOS10
EMIOS11
EMIOS12
EMIOS13
EMIOS14
EMIOS15
EMIOS23
ETPUA0
ETPUA0
ETPUA1
ETPUA2
ETPUA3
ETPUA4
ETPUA5
ETPUA6
ETPUA7
ETPUA8
ETPUA9
ETPUA10
ETPUA11
ETPUA12
ETPUA13
ETPUA14
ETPUA15
ETPUA16
ETPUA17
ETPUA18
ETPUA19
ETPUA20
ETPUA21
ETPUA22
ETPUA23
ETPUA24
ETPUA25
ETPUA26
ETPUA27
ETPUA28
ETPUA29
ETPUA30
ETPUA31
Nexus
Jtag
DSPI
FlexCAN
SCI
EMIOS
eTPU
GPIO98
GPIO99
GPIO206
GPIO207
N26
GPIO98
N24
GPIO99
GPIO206 AH10
GPIO207 AG10
PIN TEST
AN.0
AN.1
AN.2
AN.3
AN.4
AN.5
AN.6
AN.7
AN.9
AN.11
AN.12
AN.13
AN.14
AN.15
AN.16
AN.17
AN.18
AN.21
AN.22
AN.23
AN.24
AN.25
AN.27
AN.28
AN.30
AN.31
AN.32
AN.33
AN.34
AN.35
AN.36
AN.37
AN.38
AN.39
C9
B8
G12
E10
C10
B9
G13
E11
C4
B6
H15
G15
E16
C16
B7
E8
H12
E9
C11
B11
H13
E12
B12
A13
C13
B13
B14
E14
G14
A14
C5
B5
B4
C6
eQADC
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN9
AN11
AN12-SDS
AN13-SDO
AN14-SDI
AN15-FCK
AN16
AN17
AN18
AN21
AN22
AN23
AN24
AN25
AN27
AN28
AN30
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AN39
/CS0
/CS2
/CS3
ADDR.12
ADDR.13
ADDR.14
ADDR.15
ADDR.16
ADDR.17
ADDR.18
ADDR.19
ADDR.20
ADDR.21
ADDR.22
ADDR.23
ADDR.24
ADDR.25
ADDR.26
ADDR.27
ADDR.28
ADDR.29
ADDR.30
DATA.0
DATA.1
DATA.2
DATA.3
DATA.4
DATA.5
DATA.6
DATA.7
DATA.8
DATA.9
DATA.10
DATA.11
DATA.12
DATA.13
DATA.14
DATA.15
AB11
AA10
AB10
AA14
R8
AA15
W7
P7
P8
U7
N7
M8
M7
V7
L8
T8
K8
L7
U8
V8
AB13
AB14
W21
Y22
V21
W22
U21
U22
T21
T22
AA17
AB16
AA18
AB17
AA19
AB19
AA20
AB20
SPC563M64
U1
External Bus Interface (EBI)
C_CS0
C_CS2
C_CS3
C_ADD12
C_ADD13
C_ADD14
C_ADD15
C_ADD16
C_ADD17
C_ADD18
C_ADD19
C_ADD20
C_ADD21
C_ADD22
C_ADD23
C_ADD24
C_ADD25
C_ADD26
C_ADD27
C_ADD28
C_ADD29
C_ADD30
C_DAT0
C_DAT1
C_DAT2
C_DAT3
C_DAT4
C_DAT5
C_DAT6
C_DAT7
C_DAT8
C_DAT9
C_DAT10
C_DAT11
C_DAT12
C_DAT13
C_DAT14
C_DAT15
C_RD_WR
C_WE0
C_WE1
C_OE
C_TS
C_MCKO
C_EVTO
W8
Y8
AA7
AD16
AA11
H18
G19
GND
Reset &
Configuration
Clock / Synthesizer
C_RD_WR
C_WE0
C_WE1
C_OE
C_TS
C_MCKO
C_EVTO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RESET
RSTOUT
BOOTCFG1
WKPCFG
PLLREF
PCKCFG0
PCKCFG1
CLKOUT
EXTAL
XTAL
REFBYPC
VRL
VRH
VSSA0
VSSA0
VSSA1
VSSPLL
VSUP
VRCCTL
VDDA1
VDDA0
VDDPLL
VDDREG
VSTBY
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VDDE12
VRC33
VRC33
VRC33
VRC33
VRC33
/RESET
/RSOUT
BOOTCFG1
WKPCFG
PLLREF
PCKCFG0
PCKCFG1
EXTAL
XTAL
AC28
AD28
AA27
W26
AB24
AA24
AB27
AF24
AG25
REFBYPC
R4
10K
VDDEH6A
100n
10n
C33
C32
VDDSYN
CLKOUT
VRL
A10
B10
J2
J16
FB1
GND VSSSYN VSSA
R5
10K
VDDEH7
+3.3V
VDDEH6B
Close x CUT2.0
Open x CUT2.1
VDDA0
AF25
VRH
VDDREG
A9
A15
B15
A6
AC27
AD24
VSTBY
VRCCTL
AC26
A5
E15
AD27
W28
VDD
+3.3V
VRC33
VDDEH6B
VDDEH6A
VDDEH1A
VDDEH1B
B3
Y21
AA22
AA9
AB8
AC24
AD6
AE26
AF27
AF4
AG3
B25
C2
D27
D3
H7
J8
F5
AA13
AA16
AB18
AB21
AE2
AG12
AG4
K7
N8
R11
R12
R13
R17
R18
R21
T11
T12
T15
T18
U11
U15
U16
U2
V15
V16
V17
V22
B26
D2
W5
AE27
AF9
J7
VDDEH1 A
G11
VDDEH1 B
AD20
VDDEH4
N.C.
V26
VDDEH6AB
K24
VDDEH6BA
C10
100n
C9
10n
C23
10n
C22
100n
C21
10n
C17
100n
10n
C25
VSSSYN
FB2
100n
VSSA
10n
C29
10n
VDDA0
10n
C27
FB3
100n
C24
C19
10n
C18
100n
C30
100n
C26
100n
C20
10n
100n
C14
100n
C13
C7
2.2uF
C6
100n
VDDSYN
GND
GND
+5V
GND
10n
C16
+3.3V
GND
C12
100n
C11
C15
C28
C5
2.2uF
10n
+3.3V
GND
C4
100n
C3
2.2uF
C2
100n
C1
2.2uF
VDD
GND
CON4
1
2
3
4
J4
TEST POINTS
+5V
+3.3V
VDD
C8
100n
Appendix C
A1
A2
A27
A28
AA21
AA8
AB22
AB7
AD5
AF26
AF3
AG1
AG2
AG27
AG28
AH1
AH2
AH27
AH28
B1
B2
B27
B28
C26
C3
E24
E5
G22
G7
H21
H8
L11
L12
L13
L14
M12
M13
M14
M15
M16
M17
N14
N15
N16
N17
P14
P15
P16
P17
R14
R15
R16
T13
T16
T17
U12
U17
U18
V11
V18
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
VDDEH7
D26
F24
H22
J21
L15
L16
L17
L18
M18
N18
P18
C27
VDDEH7
RM0345
Schematic
Schematic
Figure 17. SPC563M64xx in CSP package schematic
GAPGRI00355
33/38
Schematic
RM0345
Figure 18. Polypod-TQ144 connector schematic
Polypod-TQ144
ETPUA0
ETPUA1
ETPUA2
ETPUA3
ETPUA4
ETPUA5
ETPUA6
ETPUA7
ETPUA8
ETPUA9
ETPUA10
ETPUA11
ETPUA12
ETPUA13
ETPUA14
ETPUA15
ETPUA16
ETPUA17
ETPUA18
ETPUA19
ETPUA20
ETPUA21
ETPUA22
ETPUA23
ETPUA24
ETPUA25
ETPUA26
ETPUA27
ETPUA28
ETPUA29
ETPUA30
ETPUA31
RSTOUT
RESET
WKPCFG
BOOTCFG1
PLLREF
EMIOS0
EMIOS2
EMIOS4
EMIOS8
EMIOS9
EMIOS10
EMIOS11
EMIOS12
EMIOS14
EMIOS23
VRL
VRH
REFBYPC
54
55
56
57
58
60
62
63
64
65
EMIOS.0
EMIOS.2
EMIOS.4
EMIOS.8
EMIOS.9
EMIOS.10
EMIOS.11
EMIOS.12
EMIOS.14
EMIOS.23
133 VRL
134 VRH
135 REFBYPC
EXTAL
XTAL
75
76
EXTAL
XTAL
CNTXA
CNRXA
CNTXC
CNRXC
66
67
84
81
CNTX_A
CNRX_A
CNTX_C
CNRX_C
TXDA
RXDA
TXDB
RXDB
83
82
72
69
TXD_A
RXD_A
TXD_B
RXD_B
JCOMP
TDO
TDI
TCK
TMS
98
100
107
105
108
JCOMP
TDO
TDI
TCK
TMS
MCKO
MSEO1
EVTI
EVTO
MSEO0
MDO0
MDO1
MDO2
MDO3
99
101
103
106
109
110
111
112
114
MCKO
/MSEO1
EVTI
EVTO
/MSEO0
MDO0
MDO1
MDO2
MDO3
PCSB5
PCSB4
PCSB3
PCSB2
PCSB1
PCSB0
SINB
SOUTB
SCKB
87
88
97
90
92
94
95
96
89
PCS_B5
PCS_B4
PCS_B3
PCS_B2
PCS_B1
PCS_B0
SIN_B
SOUT_B
SCK_B
VDDEH1A
VDDEH1B
22
48
36
59
73
91
104
115
/RSOUT 85
80
/RESET
WKPCFG 71
BOOTCFG170
PLLREF 68
U5
VDD
VDD
VDD
VDD
52
ETPUA.0.M5
ETPUA.1 51
ETPUA.2 50
ETPUA.3 49
ETPUA.4 47
ETPUA.5 45
ETPUA.6 44
ETPUA.7 43
ETPUA.8 42
ETPUA.9 41
ETPUA.10 40
ETPUA.11 39
ETPUA.12 38
ETPUA.13 37
ETPUA.14 35
ETPUA.15 33
ETPUA.16 32
ETPUA.17 31
ETPUA.18 30
ETPUA.19 29
ETPUA.20 28
ETPUA.21 27
ETPUA.22 25
ETPUA.23 23
ETPUA.24 21
ETPUA.25 20
ETPUA.26 19
ETPUA.27 18
ETPUA.28 17
ETPUA.29 16
ETPUA.30 15
ETPUA.31 14
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN9
AN11
AN12-SDS
AN13-SDO
AN14-SDO
AN15-FCK
AN16
AN17
AN18
AN21
AN22
AN23
AN24
AN25
AN27
AN28
AN30
AN31
AN32
AN33
AN34
AN35
AN38
AN39
VDDEH1B
VDDEH6A
VDDEH6A
VDDEH6B
VDDEH7
VDDEH7
VDDPLL
VDDREG
VRC33
VRCCTL
VSSPLL
VSSA0
VSTBY
VDDA0
VSUP
24
VDDEH1A
34
VDDEH1B
46
61
VDDEH6A
78
93
VDDEH6B
102
VDDEH7
113
74
VDDSYN
10 VDDREG
13
11 VRCCTL
77
7
12 VSTBY
6
VDDA0
79
+5V
J14
Default = CLOSE
J15
Default = CLOSE
C46
1uF
VSSA VSSSYN
GND
GND
26
53
86
120
143
142
141
140
139
138
137
136
5
4
119
118
117
116
3
2
1
144
132
131
130
129
128
127
126
125
124
123
122
121
9
8
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
AN.0
AN.1
AN.2
AN.3
AN.4
AN.5
AN.6
AN.7
AN.9
AN.11
AN.12
AN.13
AN.14
AN.15
AN.16
AN.17
AN.18
AN.21
AN.22
AN.23
AN.24
AN.25
AN.27
AN.28
AN.30
AN.31
AN.32
AN.33
AN.34
AN.35
AN.38
AN.39
VDD
GND
GAPGRI00356
34/38
Doc ID 024080 Rev 3
VRC33
VSTBY
GND
GPIO207_3.3V
J5
47
46
44
43
41
40
38
37
DATA.8
DATA.9
DATA.10
DATA.11
DATA.12
DATA.13
DATA.14
36
35
33
32
30
29
27
26
/CE_RAM 24
25
C_TS
DATA.0
DATA.1
DATA.2
DATA.3
DATA.4
DATA.5
DATA.6
DATA.7
/CE_RAM 1
C_TS
48
DEFAULT=CLOSE
GPIO206_3.3V
VDDEH1A
R11 10K
/RESET
TDO
ADDR.26
TCK
TMS
TDI
JCOMP
ADDR.27
DEFAULT=CLOSE
ADDR.25
J10
Vmem
D1
D2
D3
D4
D5
D6
D7
D8
OE
LE
GND
VCC
Vmem
GND
D1
D2
D3
D4
D5
D6
D7
D8
OE
LE
GND
VCC
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
GND
2
3
5
6
8
9
11
12
Latch_Q00
Latch_Q01
Latch_Q02
Latch_Q03
Latch_Q04
Latch_Q05
Latch_Q06
Latch_Q07
GND
RSVD2
RSVD4
CLKOUT
VEN_IO3
EVTI
VTREF
RDY
MDO07
MDO06
MDO05
MDO04
MDO03
MDO02
MDO01
MDO00
EVTO
MCKO
MSEO1
MSEO0
Latch_Q08
Latch_Q09
Latch_Q10
Latch_Q11
Latch_Q12
Latch_Q13
Latch_Q14
SN74LVC16373DGGR
13
14
16
17
19
20
22
23
SN74LVC16373DGGR
U4B
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
U4A
RSVD1
RSVD3
VEN_IO0
VEN_IO2
RSTIN
TDO
VEN_IO4
TCK
TMS
TDI
JCOMP
VEN_IO1
RSTOUT
TOOL_IO2
TOOL_IO1
UBATT
UBATT
TOOL_IO0
VALTREF
GND
0
BOOTCFG1
C41
100n
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
GND
Vmem
ADDR.23
ADDR.22
ADDR.21
ADDR.20
ADDR.19
ADDR.18
ADDR.17
ADDR.16
C_EVTO
C_MCKO
ADDR.29
ADDR.28
C42
2.2uF
+3.3V
C38
2.2uF
C39
100n
GND
Latch_Q14
Latch_Q13
Latch_Q12
Latch_Q11
Latch_Q10
Latch_Q09
Latch_Q08
Latch_Q07
Latch_Q06
Latch_Q05
Latch_Q04
Latch_Q03
Latch_Q02
Latch_Q01
Latch_Q00
ADDR.15
ADDR.14
ADDR.13
ADDR.12
/CS3
A6
H6
E3
A3
A4
A5
B3
B4
C3
C4
D4
H2
H3
H4
H5
G3
G4
F3
F4
E4
D3
H1
G2
NC
NC
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
U3
C40
2.2uF
1
2
5
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
/OE1
1A
2A
+3.3V
GND
U9
7
3
6
2
4
6
8
10
12
14
16
18
20
22
24
26
CE
WE
LB
UB
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
GND
22
22
/CE_RAM
C_RD_WR
C_WE0
C_WE1
C_OE
DATA.0
DATA.1
DATA.2
DATA.3
DATA.4
DATA.5
DATA.6
DATA.7
DATA.8
DATA.9
DATA.10
DATA.11
DATA.12
DATA.13
DATA.14
DATA.15
R9
R8
RSVDx
MDO0
1
1
PIN TEST
PIN TEST
CNTX_A
C44
J19
100n
J12
JUMPER
330
R1
GND
2 CNTX
CNRX
CNTX
DEFAULT=CLOSE
D1
LED
+5V
CNTX_C
2.2uF
C43
J18
+3.3V
GPIO207_3.3V
GPIO206_3.3V
1
TP3
1
TP2
VDDEH1A
JCOMP
CAL Wakeup
ADDR.30
TDO
TMS
TCK
TDI
Vmem
IS64WV102416BLL
B5
G5
A1
B2
A2
B6
C5
C6
D5
E5
F5
F6
G6
B1
C1
C2
D2
E2
F2
F1
G1
74CB3T3306
/OE2
1B
2B
ERNI_154819
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
J9
Vmem
1
3
5
/RSOUT
7
GND
9
GND
11
GND
13
GND
15
GND
17
GND
19
/RESET
GPIO207_3.3V 21
GPIO206_3.3V 23
25
ECU_Vstby
R7
22K
Vmem
R6
22K
VDDEH7
GPIO207
GPIO206
GND
+3.3V
DEFAULT=CLOSE
J3
CLKOUT
ADDR.24
ADDR.30
8
GND Vcc
4
NEXUS
DEFAULT=OPEN
1
2
3
4
+5V
ASC
C_H
C_L
RX1
CNRX_A
J13
JUMPER
CNRX_C
L9616
TX0
GND
Vs
RX0
U6
Vmem
IN
U2
GND
Vmem
2
GND
8
7
6
5
4
2 CNRX
3
C36
2.2uF
J7
GND
R10
60
Q1
GND
STT5PF20V
R2
60
100n
C37
+3.3V
GND
100n
C45
DEFAULT=CLOSE
D2
20CJQ060
/CE_RAM
74V1G32CTR
U8
J17
J6
4
74V1G00CTR
U7
GND
OUT
LF33CDT-TRY
DEFAULT=OPEN
J11
1
2
1
2
DEFAULT=OPEN
+3.3V
VSTBY
+3.3V
ECU_Vstby
/CS0
/RESET
/RSOUT
C35
100n
C34
1
4.7uF
+5V
5
3
5
3
GND
2
JP1
7
18
4
10
15
21
D6
E1
VDD
VDD
GND
GND
D1
E6
31
42
28
34
39
45
1
3
1
3
1
Doc ID 024080 Rev 3
3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
CAN_HIGH
CAN_LOW
GND
1uF
C31
D3
NUP2105
CON2
1
2
J8
Vmem
RM0345
Schematic
Figure 19. Memory, CAN and connectors schematic
GAPGRI00357
35/38
Options placement
Appendix D
RM0345
Options placement
Figure 20. Options placement
TOP view
Bottom view
GAPGRI00358
36/38
Doc ID 024080 Rev 3
RM0345
Revision history
Revision history
Table 16.
Document revision history
Date
Revision
Changes
18-Jan-2013
1
Initial release.
13-Feb-2013
2
Modified Figure 14.
17-Sep-2013
3
Updated Disclaimer.
Doc ID 024080 Rev 3
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RM0345
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