MEMORANDUM
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BSAC Faculty Directors
W. Flounders, Microlab Technology Manager
Matthew Wasilik, BSAC, Senior Development Engineer
2009 Year-End Report
29 January 2010
K. Voros, Microlab Operations Manager
Professor M. Wu, Microlab Faculty Director
I have served as a development engineer for the Berkeley Sensor & Actuator Center for 9 ½
years now. The following summarizes my work accomplishments for the year 2009.
I. ENGINEERING, DESIGN, & DEVELOPMENT OF NEW EQUIPMENT & PROCESSES
IN MICROLAB

ALUMINUM NITRIDE DEPOSITION
The piezoelectric grade aluminum nitride sputter equipment was successfully upgraded to
6inch substrate compatible processing this past year. At the same time process
improvements based on recommendations from Tegal process engineers were implemented.
Tegal also provided elucidation of formerly cryptic recipe parameters and equipment
configurations. Excellent results were achieved as a result of this development effort. A nonuniformity of 1.7% across a 6 inch wafer was routinely achieved, along with a rocking curve
of 1.53 degrees for a 1 micron nominal thick AlN film. A routine process monitor was
instated for this equipment following the upgrade. The online operations manual for this
equipment was augmented with relevant equipment and process information.

POCKET WAFERS FOR ALN
I designed a silicon pocket wafer process flow for fabrication of a special wafer carrier to
provide continuation of 4 inch substrate and smaller die processing at ALN (aluminum
nitride). The pocket wafer design allows the wafer to rest on a silicon pocket eliminating the
need for adhesives. The process flow for the silicon wafer consists of a dual mask exposure
with front-back side alignment contact lithography. These wafers served to help researchers
meet their deadlines, but they could not be used long term due to the brittle nature of
silicon. Aluminum pocket carriers were also macro-machined for same purpose. They
however became plastically deformed due to the thermal flux from the chamber plasma.
Subsequent analysis was performed to determine elastic and/or plastic deformation for
different materials. Titanium was eventually chosen as the best material for all future pocket
wafers at ALN. It is strong enough to withstand mechanical deformation from a plasma flux
on one side, and easy to clean in standard resist developer solution. More info on pocket
wafer materials can be seen in Table 1.
Silicon Aluminum
Titanium
Linear in situ
deformation estimate
0.008 in
0.067 in
0.024 in
post process (plastic) deformation?
NO
YES
NO
manufacturing cost, per wafer estimate
$127.89
NA
~$116.00
phosphoric acid bath
NA
TMAH‐based developer
mechanical robustness
brittle
temperature issues
strong
process effect
none
detrimental
none
AlN strip method
Table 1 - Pocket Wafer Materials for Aluminum Nitride Deposition

ALUMINUM NITRIDE ANISOTROPIC ETCH CHARACTERIZATION
A new metal etch chamber, the Centura MET came online in Y2009. This chamber is
essentially a DPS decoupled plasma source configuration, similar to the deep silicon Centura
chamber, but plumbed specifically for and dedicated to metal etching. Gases include Cl2,
BCL3, SF6, Ar, N2, and O2. In the interest of supporting BSAC researchers’ process
requirements, the characterization of an anisotropic aluminum nitride etch was embarked
upon using this chamber. The chief target of this development work was to attain perfectly
straight AlN sidewalls up to 2 microns thick. An initial round of AlN etch experiments was
performed to evaluate UV baked g line resist as a masking material in 16 different
preliminary test runs. Resultant resist profiles and selectivities were studied. This
preliminary study served to gain familiarity with idiosyncrasies of the Centura-MET and to
optimize parameter and chemistry combinations pertaining to a resist mask. It was found
that a resist mask alone would not sufficiently serve as a mask for AlN films thicker than 1
micron. Films thicker than 1 micron would require an oxide mask. Furthermore, the oxide
mask profile must also be anisotropic, lest the initial oxide sidewall angle carry through the
AlN due to ionic deflection. See Figure 1 for typical preliminary test result. This necessitated
a separate characterization for anisotropic oxide etch in the MERIE Centura-MXP chamber
described separately in this report. Once the oxide etch had been well characterized, a
resolution V, 16-run fractional factorial design was performed that studied 5 different
factors: plasma power, bias power, SF6, Cl2, and Ar flow rates. This will be referred to as
phase I. Although much was learned from the phase I design of experiment, it was not
entirely successful. Refer to Figure 2. Several of the runs did not etch due to ostensibly
conflicting chemistry effects. Nonetheless information learned from this effort was evaluated
and parlayed into a new design of experiment which studied power, bias, Cl2, BCl3 and Ar
flow rates. This phase II experiment was likewise set up as a resolution V, 16-run fractional
factorial design. The phase II experiment produced acceptable results, as may be seen in
Figure 3. 84 degree sidewalls were deemed a milestone for the researchers involved with
this project. This development effort will be presented at the 2010 spring BSAC IAB
meeting.
-2-
UVB PR
45⁰
AlN
preliminary phase
silicon
Figure 1 - Typical Results From Preliminary Etch Tests for
Uvbaked Photoresist Mask on AlN on Silicon
Figure 2 - Best Result From Phase I Design of Experiment
for Anisotropic AlN Etch on Silicon
-3-
84⁰
oxide
AlN
silicon
phase II
Figure 3 - Best Result From Phase II Design of Experiment
for Anisotropic AlN Etch on Silicon

OXIDE ETCH DEVELOPMENT – CENTURA MXP
Oxide etch development was performed at Centura MXP equipment with the target of
obtaining a straight sidewall recipe. Previously developed recipes typically serve to etch very
thin oxide layers for IC devices, and thus their results will not necessarily exhibit slope
sidewalls, especially for those applications. Thicker oxide etches however required the
development work performed here. Anisotropic etch of aluminum nitride likewise
necessitates a straight sidewall mask, as a sloped sidewall of an oxide mask will carry
through into the aluminum nitride (presumably due to ionic deflection). A resolution V, 16run fractional factorial design provided valuable insight into what parameters have main and
second order effects for selectivity, etch rates, and sidewall straightness. Pre-development
and post-development results shown in Figure 4.

KEYENCE DIGITAL MICROSCOPE
I invited Keyence to BSAC to present their newest 3CCD digital microscope, the VHX-600
during the summer of 2009. The scope has some nice features, among them the capability
to integrate multiple focus planes. This allows crisp, clear, color 3-d images of the device or
specimen under test, which to this point had been otherwise unobtainable with optical
microscopes in the Microlab. The VHX also is also capable of measuring cross sections or
out-of-plane 3-d profiles, as well as recording digital video. A competing system is offered
by Hirox, the KH7700. Both of these systems’ features were compared in tabular form and
presented to the BSAC directors. In late 2009 Keyence offered to temporarily site their VHX600 inside the Marvell Nanolab in January 2010. The system is currently available for
researcher use and evaluation.
-4-
STANDARD OXIDE ETCH RECIPE
POST DEVELOPMENTAL RECIPE
UV baked g line photoresist
UV baked g line photoresist
oxide
oxide
Reci pe ‐>
MXP‐OXSP‐ETCH
Reci pe ‐>
STRAIGHT SIDEWALL Power (W)
Pressure (mT)
Ar flow
CF4 flow
CHF3 flow
Etch Rate (Ang/min)
Profile (degrees)
Selectivity
500
Power (W)
Pressure (mT)
Ar flow
CF4 flow
CHF3 flow
Etch Rate (Ang/min)
Profile (degrees)
Selectivity
900
200
120
10
50
2508
77.7
13 to 1
70
200
15
50
3382
87.2
8 to 1
Figure 4 - Left: Standard Oxide Etch Recipe (best for thin layer applications)
Right: Newly Developed Recipe for Thick Oxides
II.

SUSTAINING OF EXISTING TOOLSET & SUPPLEMENTARY PROCESS
DEVELOPMENT IN MICROLAB
CENTURA DPS
Re-characterization results for the DPS DT deep silicon etch chamber were presented at the
fall BSAC IAB meeting. A resolution V, 16-run factorial design was successful in providing
insight on fine tuning processes for specific applications. A stop on oxide with pulsed bias was
verified to alleviate silicon footing in several cases. The DPS DT recipe set expanded in Y2009.
Note that DPS DT has the added capability of HBr and Cl2 based chemistry, something that
STS currently does not have. It also has 2kW power supply, which enables a 2x faster etch
rate than STS. Ceramic changes and routine mechanical and chemical cleans were performed
as necessary. A routine etch monitor was instated at for DPS and results are posted online. A
DPS equipment-use chart for the past 5 years may be found in Figure 5.
-5-
10000
USE MINUTES
USE MINUTES
9000
36,074
USE MINUTES
21,788
28,092
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process characterization and
development
chamber chemical clean.
chiller / heat exchanger issues
cathode assembly atmospheric
leak
pump issues
chamber manual clean
power supply issues
load lock issues
gas delivery issues
flat finder issues
electrostatic chuck issues
throttling gate valve issues
Figure 5 - Centura Use Chart and Common Problems Encountered (Updated for 2009)

STS
STS continued to be a workhorse for researchers in Y2009. See Figure 6 for a historical
equipment-use graph. The 6 inch upgrade of this equipment was completed in early
February. The upgrade was comprised of replacing the electro static chuck and the load
spatula. Process characterization and verification immediately followed. Save for a slight
difference in etch rate, and an anticipated slightly larger non-uniformity for 6in diameter
substrates, the standard recipe set was established to be largely unaffected. STS routinely
experiences several process regimes over course of a process cycle. Compensation recipes
were regularly made available to researchers as needed and serve to minimize process drift
for respective etch regimes. STS performed exceptionally well as a deep silicon etch tool for
Microlab and its labmembers in 2009. I will continue to support operation and processing
aspects of this important machine.
-6-
18000
10000
USE MINUTES
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software communication issues
chiller issues
electrostatic chuck issues
chamber chemical clean.
chamber lid TC issues
RF match network issues
pump issues
computer/electronics issues
power issues
process development
vacuum leak issues
wafer handling issues
Figure 6 - STS Use Chart and Common Problems Encountered.

STS DEEP SILICON ETCH FOR MINIMAL ARDE LAG
I assisted BSAC researchers with improving the aspect ratio dependent lag in their etch
process, and in doing so helped to preclude the usual necessary processing with an SOI
substrate. A simple tri-stage ARDE model was employed. The model is as such: Polymer
deposition rate, etch rate of the polymer deposited, and silicon etch rate all vary for
different size aspect ratio features. If each of the rates for each respective AR feature are
known, the DRIE recipe cycle times may be tuned to minimize ARDE lag. The improvement
shown in Figure 7 was deemed acceptable by the researchers.

SUSS PMC150 PROBE STATION
The Suss MicroTec PMC150 is a cryogenic probing station that was successfully sited in
professor Clark’s lab in Y2009. The system was designed for manual probing applications in
vacuum and at low temperature down to 4K. I assisted in writing an operations manual for
the system and had it posted on the BSAC website. Unfortunately, due in large part to the
economic downturn, the system was repossessed by Suss shortly thereafter.
-7-
BEFORE
AFTER
4μ hole
Si
Si
4μ hole
100μ+ feature
100μ+ feature
Figure 7 - ARDE Lag Improvement by Adjusting STS Recipe Parameters
FLIPCHIP BONDER
The Suss MicroTec FC-150 flipchip bonder is a high performance bonding tool capable of
performing thermocompression and solder reflow processing. I continued to provide training
and process support to equipment users on this high precision equipment in Y2009. The
special training that I continue to offer for this tool has served researchers well. An
equipment use chart spanning the past five years is found in Figure 8. Common problems
encountered are also shown in this chart. Note there have been no user mishaps with
respect to the flipchip toolset since the special training course was first implemented in
Y2006. No major third party vendor service costs were needed in Y2009.
7000
USE MINUTES
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5600
15,556
USE MINUTES
6694
$ 2765
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
2006
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process characterization
and development
Stage related issues
Computer related issues
UBA related issues
SiC tooling issues
Chuck related issues
2008
SRA related issues
Temp controller issues
Vacuum issues
Crosshair gen issues
Power supply issues
Electronics issues
Plumbing issues
Service & parts costs
Figure 8 - Equipment Use Chart for FLIPCHIP
-8-
I I I . PROJECTS

DUAL LAYER SILICON ON OXIDE ETCH
I assisted BSAC’s visiting researcher Christopher Grinde (Vestfold University, Norway) with
a dual layer oxide SOI etch at Centura DPS and Centura MXP. This etch was performed prior
to the MXP design of experiment outlined above that improved oxide sidewall anisotropy. A
slightly tapered oxide sidewall may be seen in Figure 9. However, silicon footing or
notching is minimal for both silicon device layers. A 30% over-etch was performed on both
device layers. Such demonstrates proper functioning of the HALO (High Accuracy Low
Output) low frequency pulsed bias generator. After evaluating the results, Dr. Grinde
offered a further collaboration with BSAC, including some funds, to follow up on these etch
trials. This work will be completed in 2010.
FIGURE 9 - Dual Layer SOI Etch At Centura DPS DT and Centura MXP

SEM EVALUATION
I worked to evaluate a new generation of tabletop scanning electron microscopes in Y2009.
These systems have a smaller footprint and are less costly than traditional SEMs. Multiple
models were evaluated, included FEI’s Phenom, Hitachi’s TM 1000,, Novelx (now Agilent)
mySEM , JEOL’s Neoscope. A comprehensive specification and comparison table was built
and presented. Recommendations were made. In Figure 10 several different models are
plotted, cost vs. performance (Note costs are subject to change). The LEO 1550 is the
system Marvell Nanolab currently offers and sustains. The Zeiss Supra-25 is shown as
example of newer high end conventional SEM. All other SEMs depicted qualify as benchtop
systems (footprint size of a microwave oven). I continue to hold the opinion that a benchtop
SEM would serve to complement the lab’s current SEM capabilities
-9-
15 nm
NOVELX
mySEM
$115k new
MAX MAGNIFICATION: 900,000x
ACCELERATING VOLTAGE: 200V‐30kV
MAX SPECIMEN SIZE: 6in wafer will fit
MAX MAGNIFICATION: 65,000x
ACCELERATING VOLTAGE: 500V‐2kV
MAX SPECIMEN SIZE: 4in wafer will fit
SEISS
Supra‐25
$300k new
MAX MAGNIFICATION: 500,000x
ACCELERATING VOLTAGE: 500V ‐ 20kV
MAX SPECIMEN SIZE: 6in wafer will fit
30 nm
FIELD EMISSION SOURCES
JEOL
NeoScope
$60k new
60 nm
SPECIFIED FEATURE SIZE RESOLUTION
1 nm
LEO
1550 FE
~$95k used
Hitachi
TM1000
$58k new
THERMIONIC SOURCES
FEI Phenom
$72k new
MAX MAGNIFICATION: 20,000x
ACCELERATING VOLTAGE: 5kV
MAX SPECIMEN SIZE: 25mm diam
MAX MAGNIFICATION: 20,000x
ACCELERATING VOLTAGE: 5kV, 10kV, 15kV
MAX SPECIMEN SIZE: 70mm diam
MAX MAGNIFICATION: 10,000x
ACCELERATING VOLTAGE: 15kV
MAX SPECIMEN SIZE: 70mm diam
M. Wasilik 2009
SYSTEM BASE COST
Figure 10 - SEM Performance Vs. Cost Graph

ELECTROPLATING STATION EVALUATION AND DESIGN
I evaluated a potential donation of a Mesa West electroplating sink from BSAC member JPL.
Several BSAC directors were interested in obtaining this type of sink station. The system
was determined to be in excellent condition from an on site review . However, supporting an
electroplating sink in a research environment is not facile. Large volume plating baths are
not conducive to a versatile, dynamic lab. An equipment modification cost analysis for the
JPL sink was made and presented to the BSAC directors. The sink was ultimately rejected by
Microlab due to the fact it was constructed of non-fire retardant polypropylene. The JPL sink
was eventually accepted by BSAC for UC Davis’ lab. I continued to work with BSAC directors
by designing several versions ( of electroplating stations over the course of several months.
This included on site system evaluations of third party vendors, researching wafer clamps,
pumps, spargers, heaters and casing materials for electroplating. BSAC ultimately
determined that a single bath off- the-shelf model was the most cost effective solution.
- 10 -
IV.

OTHERS
SUSS MICROTEC TOOLSET
I worked to augment Microlab’s Suss equipment toolset for 6 inch processing. The BA6,
MA6, and SB6 systems now have the appropriate chucks and fixtures to accommodate all 4
and 6 inch processes.

PICOSUN ALD
I provided processing oversight for BSAC Industrial members.

GRAPHICAL DISPLAY OF INFORMATION
I attended a seminar on the graphical display of information hosted by Edward Tufte.

MARVELL LAB AUTOCAD LAYOUTS
I evaluated an AutoCAD shareware reader software and provided tutorial to Microlab staff in
order to facilitate modification/assessment of Marvel Lab ACAD layouts. I also provided
AutoCAD expertise in modifying Marvell lab equipment layouts.

MICROLAB TOURS
I provided Microlab tours for current and potential BSAC industrial members.

PROCESS CONSULTATION
I assisted BSAC labmembers with process questions regarding DRIE, various plasma etch,
various wet etch, molecular vapor deposition, HF vapor release, SEM instruction, wafer
bonding, mechanical and optical profiling, IR camera microscope inspection,
thermocompression bonding, contact lithography, flipchip bonding, and liftoff during the
course of the year.

OPERATIONS MANUALS & MODULES
I wrote reversible online bonding modules with easy-to-read graphics and interactive flow
charts. Suss PMC150, Parylene, STS, Centura-DPS, ALN, and AMST manuals were all
revised, updated, and augmented.

POLYTEC MSA-500
I assisted Polytec in the temporary siting of their MSA-500 at BSAC. Ideally this system
would have been installed on the PMC150 probe station but there was a mechanical
incompatibility. I worked to train several users on this system while it was here.

TEGAL ENDEAVOR
I worked to evaluate a Tegal Endeavor platform donated by Analog Devices Inc. The 3chamber system (main film = aluminum nitride) will be brought online in the new lab in
2010.
- 11 -
V.

FUTURE GOALS
MARVELL LAB MOVE
I will continue to assist with the move to the new lab. During the past year I have worked to
successfully instate process monitoring on high profile equipments. Such will serve as a
baseline for process start up for these machines when in the new lab. Any modification to
equipment for move preparation will be performed as necessary. I will be heavily involved in
bringing processes up as their respective equipments come online in the new lab.

III-V COMPOUND ETCH STUDY INITIATIVE
A preliminary etch study for selected III-V compounds has been proposed. The study would
investigate etch rates for a range of standard etchants, both dry and wet. An extended
study would involve more specialized dry etch process development. The initial compound
list is as follows:
III-V semiconductors
a. Aluminum nitride (AlN)
b. Gallium arsenide (GaAs)
c. Gallium nitride (GaN)
d. Indium phosphide (InP)
III-V ternary semiconductor alloys
e. Aluminium gallium arsenide (AlGaAs, AlxGa1-xAs)
f. Indium gallium arsenide (InGaAs, InxGa1-xAs)
g. Indium gallium nitride (InGaN)
III-V quaternary semiconductor alloys
h. Indium gallium arsenide phosphide (InGaAsP)

BORON NITRIDE
I will evaluate Boron nitride for use as an etch mask. BN would ostensibly obviate the need
for metal masks in dry etch processes. Metal masks are typically disallowed in dry etch
processes due to non-volatile byproduct contamination, subsequent process effects, and
costly equipment maintenance. Boron nitride byproducts from plasma processes has been
conversely estimated to be volatile. Its material toughness however may allow it to
effectively serve as an etch mask for SF6, Cl2, HBr and I-based plasma processes. Harsh
SiC etch is a candidate. An Edwards sputtering target for BN deposition has been specified
and ordered. Investigation into patterning the BN will follow. Side note: this material may
also be deposited via atomic layer deposition.

CMOS BASELINE EXTENSION FOR MEMS PROCESSING
I will complete the fabrication and testing/verification of the electrostatic displacement
microactuator that was fabricated in the Microlab’s CMOS baseline process. A working
device will have the capacity to test Young’s modulus of different materials. A known test
material (such as polysilicon) will be processed with the devices to confirm functionality.
- 12 -