LASCAS 2017
In regular digital circuits, if the charge deposited by a particle hit is too small
to change the state of a flip-flop, there will be no indication that such a hit
ever occurred. In contrast to other ICs, the CMOS APS in a digital camera
can record the effect of most particle hits by displaying a pixel output that is
brighter than the incoming illumination. We present an experimental study
of SEUs in digital cameras and compare their rate to that of SEUs in SRAM
memory and to the rate of permanent defects in cameras. This analysis provides important information about the nature and distribution of particle hits
and their occurrence rate, and increases our understanding of SEUs in regular
ICs as well as in camera sensors.
Designing a FINFET based embedded SRAM
Array
Vivek Nautiyal and Jitendra Dasani, ARM
All SOCs have embedded SRAM to store data. As the
processing power of a SOC increases, so is the demand for
embedded SRAM. This makes SRAM a significant contributor to chip power, performance, area, and yield. In the first
part of this tutorial we will start with the basics of SRAM
design, and the basic feature set of an embedded SRAM.
As SRAM is the primary contributor to overall chip yield,
we will talk about different testability and yield enhancement techniques for
SRAM arrays. As the power consumption of an SRAM array is a significant
part of overall chip power, SRAM has different power management features,
which we will also touch on. We will also discuss critical timings associated with
SRAM. In the second part of the tutorial we will discuss variability in SRAM
and its implications. As CMOS technology scales, the density of the embedded
memory in a chip increases. To reduce SOC size, the technological feature for
SRAM is smaller than the logic transistor. The small size increases the susceptibility of variation in SRAM cell transistors. To reduce power consumption
lower voltage is used, and the lower supply voltage along with variation causes
SRAM cell writeability and cell stability issues. In the FINFET process the
width of a transistor can only be based on the number of FINS. This makes
SRAM design even more challenging. Due to the discrete nature of the width of
the transistor, choices for transistor sizes are limited. Limitation on transistor
sizes means SRAM cell issues cannot be addressed by process technology. To
overcome this process challenge, transistors of 6T SRAM cells are dynamically
made stronger and weaker by changing the bias conditions of transistors for
different operations. Circuit used for dynamically changing strength of different transistor in a SRAM cell is called assist circuits. We will be talking about
LASCAS - PRIME - Iberchip
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Bariloche 20-23 February 2017
LASCAS 2017
Live Demos
Live Demos offer the possibility for an interactive and tangible form of
presentation, which is quite different from oral and poster sessions. Attendees
are invited to experience demonstrations directly, to interact with, play with,
and challenge them. Presenters have the opportunity to show direct proof of
their working systems and to create a lasting impression. The Live Demos
accepted for presentation at LASCAS 2017 are:
• Phase-Measurement based Offset-Correction Technique for Dynamic Comparators Andres Amaya, Javier Ardila and Elkim Roa
• The XbarSim Simulator Ioannis Vourkas
• Ionizing Radiation Detection Using CMOS image Sensors. M.
Perez, J. Lipovetzky, M. Sofo Haro, I. Sidelnik, J. J Blostein, F. A. Bessia,
and M. Gomez Berisso.
• LoRa Alfredo Arnaud
• Test platforms for real-life SEU testing of SRAMs and Radiation Ground Testing of digital circuits: results of FACTOMETRICS and HARLMESS STIC-AMSUD projects Raoul Velazco
• UFRGSPlace: Routability Driven FPGA Placement Algorithm
for Heterogeneous FPGAs Julia Casarin Puget
• HW/SW Codesign of Maximum Lyapunov Exponent Estimator
Luciana De Micco, Maximiliano Antonelli, Maria Liz Crespo and Andres
Cicuttin
• A System-on-Chip Platform for the Internet of Things featuring
a 32-bit RISC-V based Microcontroller Ckristian Duran, et al
• An 83% Efficiency Charge Pum for Embedded Nonvolatile Memory (eNVM) in 130nm CMOS Rodrigo Gomez, Andres Amaya, Hector Gomez, Hugo Hernandez, and Elkim Roa
• Stripping and Testing System for COTS Integrated Circuits
Ionizing Radiation Essays Pablo Alejandro Ferreyra y Daniel Sánchez
LASCAS - PRIME - Iberchip
6
Bariloche 20-23 February 2017
LASCAS 2017
Organizing Committee
• LASCAS General Chairs
– Martin Di Federico (INTI, UNS, CONICET, Argentina)
– Jose Lipovetzky (IB, CNEA, CONICET, Argentina)
• LASCAS Program Chairs
– Pedro Julian (UNS, CONICET, Argentina)
– Ralph Etienne Cummings (JHU, USA)
• PRIME-LA and Iberchip General Chair
– Martin Di Federico (UNS, INTI, CONICET, Argentina)
– Benjamin Reyes (UNC, Argentina)
• PRIME-LA and Iberchip Program Chairs
– Alfredo Arnaud (UCU, Uruguay)
– Alfonso Chacon Rodriguez (ITCR, Costa Rica)
• Financial Chairs
– Martin Di Federico (UNS, INTI, CONICET, Argentina)
– Pablo Mandolesi (UNS, CONICET, Argentina)
• Industry Liasons
– Victor Grimblatt (Synopsys, Chile)
– Vojin Oklobdzija (UC Davis, USA)
• Publication Chairs
– Lorena Garcia (Universidad Sergio Arboleda, Peru)
• Special sessions, Demo and Tutorials Chair
– Benjamin Reyes (UNC, Argentina)
• Local Arrangements Team
– Martin Perez (IB, CONICET, Argentina)
– Guillermo Guichal (IB, EMTECH, Argentina)
– Paola Ceminari (UNS, INTI, Argentina)
– Ariel Oroz (UNS, INTI, Argentina)
– Fabricio Alcalde Bessia (IB, CONICET, Argentina)
– Pablo Del Corro (IB, CONICET, Argentina)
– Ivan Sidelnik (IB, CONICET, Argentina)
– Arelovich Ariel (UNS, INTI, Argentina)
– Bellini Jorge (UNS, INTI, Argentina)
– Laura Curuchet(CNEA, Argentina)
– Horacio Mateos(CNEA, Argentina)
– Ariel Pola (UNC, Argentina)
LASCAS - PRIME - Iberchip
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Bariloche 20-23 February 2017
LASCAS 2017
LASCAS Papers
LASCAS Session I-Condor (Tuesday 21st 10:30-12:30)
10:30
10:50
11:10
11:30
11:50
12:10
Modelling
Improving a MOSFET Model for Design by Hand
Ademir De Jesus Costa, Bruno Jambeiro Alves, Shirlene de Santana Soares, Edson Pinto Santana and Ana Isabela Araújo Cunha
Asymmetrical Length Biasing for Energy Efficient Digital Circuits
Francisco Veirano, Fernando Silveira and Lirida Naviner
Adherence of a High-Speed RRP LDMOS Characterization Setup to
JESD 24-10 Standard
Carlos Bernal and Manuel Jimenez
Oscillation-Based Test in a CCII-based Bandpass Filters
Pablo Petrashin, Luis Toledo, Walter Lancioni, Tinus Stander and Piotr Osuch
Statistical Library Characterization Using Arbitrary Polynomial
Chaos
Mehmet Ince, Sule Ozev and Sarma Vrudhula
Low Power Sum of Absolute Differences Architecture Using Novel Hybrid Adder
Rafael Dos Ferreira, Bianca Silveira, Mateus Beck Fonseca, Claudio M. Diniz and
Eduardo A. C. Da Costa
LASCAS Session II-Condor (Wednesday 22nd 10:30-12:30)
10:30
10:50
11:10
11:30
11:50
12:10
Special Session: Resistive Memories
High Density Emerging Resistive Memories: What are the Limits?
A. Levisse, B. Giraud , J.P. Noel , M. Moreau , J.M. Portal
Studies of Dynamics of Memristor-baased Memory Cells
Bartlomiej Garda, Krzysztof Kasiński, Maciej Ogorzalek, and Zbigniew Galias
Analog memristive and memcapacitive properties of Ti / Al2O3 /
Nb2O5 / Ti resistive switches
S. Slesazeck, H. Wylezich, T. Mikolajick
Optimization Opportunities in RRAM-based FPGA Architectures
Xifan Tang, Giovanni De Micheli, and Pierre-Emmanuel Gaillardon
High-Frequency Memristive Synapses
Illiani Carro-Pérez, Hugo Gustavo González-Hernández and Carlos SánchezLópez
Exploring the Voltage Divider Approach for Accurate Memristor State
Tuning
Ioannis Vourkas, Jorge Gomez, Nikolaos Vasileiadis, Angel Abusleme, Georgios
Ch. Sirakoulis and Antonio Rubio
LASCAS Session II-Quintral (Wednesday 22nd 10:30-12:30)
10:30
10:50
Analog Design 1
A 28GHz Self-Contained Power Amplifier for 5G applications in 28nm
FD-SOI CMOS
Boris Moret, Eric Kerherve and Vincent Knopik
A versatile, CMOS compatible, integrated antenna for millimeter-wave
applications
Roberto Stack Murphy Arteaga and Luz Karine Sandoval Granados
LASCAS - PRIME - Iberchip
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Bariloche 20-23 February 2017
LASCAS 2017
11:10
11:30
11:50
12:10
Blind range level shifters from 0 to 18V
Joel Gak, Alfredo Arnaud and Pablo Mandolesi
A 4uA Wireless Platform for Cattle Heat Detection.
Bruno Bellini and Alfredo Arnaud
A 90% Efficiency 60 mW MPPT Switched Capacitor DC - DC Converter for Photovoltaic Energy Harvesting Aiming for IoT Applications
Roger Zamparette, Hamilton Klimach and Sergio Bampi
Biased capacitive divider electrostatic generators for energy harvesting
Antonio Queiroz
LASCAS Session III-Condor (Wednesday 22nd 13:30-15:30)
13:30
13:50
14:10
14:30
14:50
15:10
Digital Desing 1
Hardware Implementation for Permutation Function of MultiplicationHardened Sponge BlaMka
Jonatas F. Rossetti and Wilson V. Ruggiero
A Comparison of Asynchronous QDI Templates Using Static Logic
Ricardo Aquino Guazzelli, Matheus Trevisan Moreira and Ney Laert Vilar
Calazans
Co-design System for Template Matching using Dedicated Coprocessor and Particle Swarm Optimization
Yuri Tavares, Nadia Nedjah and Luiza De Macedo Mourelle
Evaluation of the uModel Factory Software Used For the Modeling of
Embedded Systems with Concurrent States
Mariana Prieto, Lisandro Sugezky, Nahuel Gonzalez, Marcelo Giura, Marcelo
Trujillo and Juan Manuel Cruz
4D reverberator-based digital filters
Minas Kousoulis, Constantine Coutras and George Antoniou
A System-on-Chip Platform for the Internet of Things featuring a 32bit RISC-V based Microcontroller
Ckristian Duran, Luis E. Rueda G., Javier Ardila, Luis Rueda D., Giovanny
Castillo, Anderson Agudelo, Camilo Rojas, Luis Chaparro, Harry Hurtado, Juan
Romero, Wilmer Ramirez, Hector Gomez, Hugo Hernandez, Jose Amaya and
Elkim Roa
LASCAS Session III-Quintral (Wednesday 22nd 13:30-15:30)
13:30
13:50
14:10
14:30
14:50
Power Electronics
Designing an Optimum Non-Dissipative LC Snubber for Step-Up Flyback Converters in DCM
Esteban Oscar Lindstrom, Luciano Andres Garcia Rodriguez, Alejandro Raúl
Oliva and Juan Carlos Balda
Coexistence of Solutions in a Boost-Flyback Converter with current
mode control
Juan Munoz, Guillermo Gallo, Fabiola Angulo and Gustavo Osorio
An small-signal averaged model of a coupled-inductor boost converter
Maria Belen D’Amico and Sergio Gonzalez
Comparative Topology and Power Loss Study for High Power Density
and High Conversion Ratio Integrated Switching Power Converters
Kang Wei and D. Brian Ma
Reconfigurable Multiple-Gain Active-Rectifier for Maximum Efficiency Point Traking in WPT
Pablo Pérez-Nicoli and Fernando Silveira
LASCAS - PRIME - Iberchip
9
Bariloche 20-23 February 2017
LASCAS 2017
15:10
Design of Experiments Implementation towards Optimization of Power
Distribution Networks
Felipe De Jesus Leal-Romo, Jose E. Rayas-Sanchez and Jiangqi He
LASCAS Session VI-Amancay (Wednesday 22nd 15:10-15:30)
15:10
Analog Low Power
A 0.45 V, 93 pW Temperature-Compensated CMOS Voltage Reference
Arthur Oliveira, David Cordova, Hamilton Klimach and Sergio Bampi
LASCAS Session IV-Condor (Wednesday 22nd 16:00-18:00)
16:00
16:20
16:40
17:00
17:20
17:40
Sensors and detection
Silicon Photo-multipliers Characterization System
Laura D. Yelós, Federico Suarez, José L. Correa Lust, Matias Bignert, Agustin
Lucero, Angel Cancio, Alexis Mancilla, Javier Maya and Beatriz Garcı́a
Aspects on the shape dependence with energy of point-like events in
high resistivity CCDs
Guillermo Fernandez Moroni, Miguel Sofo Haro, Javier Tiffenberg, Juan Estrada,
Gustavo Cancelo, Xavier Bertou and Eduardo Paolini
Bearings-only aerial shooter localization using a microphone array
mounted on a drone
Rigel Fernandes, José Apolinário Jr. and António Ramos
RISC-V based ASP sound classifier intended for acoustic surveillance
in protected natural environments
Carlos Salazar-Garcı́a and Alfonso Chacon-Rodriguez
Real-time Teleoperation with the Baxter Robot and the Kinect Sensor
Jose Avalos and Oscar Ramos
A Low-Power, High-Accuracy Capacitance-to-Time Converter for Differential Capacitive Sensors
Satomi Ogawa
LASCAS Session IV-Quintral (Wednesday 22nd 16:00-18:00)
16:00
16:20
16:40
17:00
17:20
17:40
Fault Tolerant Systems and Radiation Effects
Process and Temperature Impact on Single-Event Transients in 28nm
FDSOI CMOS
Walter Enrique Calienes Bartra, Andrei Vladimirescu and Ricardo Reis
Radiation Sensitivity of XOR Topologies in Multigate Technologies
under Voltage Variability
Ygor Aguiar, Cristina Meinhardt and Ricardo Reis
Evaluation of Multiple Bit Upset Tolerant Codes for NoCs Buffering
Felipe Silva, Jarbas Silveira, Otávio A. Lima Jr, João Marcelo Ferreira, Walter
Freitas Jr, Philippe Magalhães and César Marcon
Evaluating the Efficiency of using TMR in the High-Level Synthesis
Design Flow of SRAM-based FPGA
Andre Flores Dos Santos, Lucas Tambara and Fernanda Kastensmidt
Applying Lockstep in Dual-Core ARM Cortex-A9 to Mitigate
Radiation-induced Soft Errors
Ádria B. Oliveira, Lucas A. Tambara and Fernanda L. Kastensmidt
Low Cost Rollback to Improve Fault-Tolerance in VLSI Circuits
Thierry Bonnoit, Nacer-Eddine Zergainoh, Michel Nicoladis, and Raoul Velazco
LASCAS - PRIME - Iberchip
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Bariloche 20-23 February 2017
LASCAS 2017
LASCAS Session V-Condor (Thursday 23rd 10:30-12:30)
10:30
10:50
11:10
11:30
11:50
12:10
RF and Comunications
A high IP3 6.5 mW self-biased 0.3 - 3 GHz small area LNA
Arthur Liraneto Torres Costa, Hamilton Klimach and Sergio Bampi
Object identification using VSWR evaluation based on a narrowband
microstrip antenna and a tuned amplifier
Mauricio Donatti and Leandro Manera
A 4-Wire Interface SoC for Shared Multi-Implant Power Transfer and
Full-duplex Communication
Sara S. Ghoreishizadeh, Dorian Haci, Yan Liu and Timothy G. Constandinou
Double Quadrature Bandpass Sampling for a PLL and Mixer-less LowIF Multistandard Receiver
Guilherme Sionek, Luis Henrique Assumpção Lolis, João Paulo Cunha, Mateus
Lovatel Matias, André Augusto Mariano and Bernardo Leite
Enhancing I2C Robustness to Soft Errors
Vicente Carvalho and Fernanda Lima Kastensmidt
All digital reconfigurable IR-UWB pulse generator using BPSK modulation in 130nm RF-CMOS process
Luiz Carlos Moreira, José Fontebasso Neto, Thiago Ferauche, Guilherme
Apolinário Silva Novaes and Emmanuel Torres Rios
LASCAS Session V-Quintral (Thursday 23rd 10:30-12:30)
10:30
10:50
11:10
11:30
11:50
12:10
Algorithms
A Comparison of Four PDE-Spatial Denoising Systems for Molecular
Images
Salim Lahmiri and Mounir Boukadoum
Exploiting Addition Schemes for the Improvement of Optimized
Radix-2 and Radix-4 FFT Butterflies
Renato Neuenfeld, Mateus Fonseca and Eduardo Da Costa
Filtered-x Error Coded Affine Projection Algorithm with Evolving Order for Active Noise Control
Alejandro Rodriguez, Juan Avalos and Juan Sanchez
Design of Residue Generators with CLA/Compressor Trees and MultiBit EAC
Piotr Patronik and Stanislaw Piestrak
Characterizing Energy Consumption in Software HEVC Encoders:
HM vs x265
Ítalo Machado, Wagner Penny, Luciano Agostini, Marcelo Porto and Bruno Zatt
Energy Evaluation of the HEVC Decoding for Different Encoding Configurations
Douglas Corrêa, Daniel Palomino, Luciano Agostini and Bruno Zatt
LASCAS - PRIME - Iberchip
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Bariloche 20-23 February 2017
LASCAS 2017
LASCAS Session VI-Condor (Thursday 23rd 13:30-15:30)
13:30
13:50
14:10
14:30
15:10
16:00
Analog Design 2
Calibration-Less Nauta OTA Operating at 0.25-V Power Supply in a
130-nm Digital CMOS Process
Rodrigo Aparecido Da Silva Braga, Luı́s Henrique De Carvalho Ferreira, Gustavo
Della Colletta and Odilon De Oliveira Dutra
Settling time-based Design of a Fully Differential OTA for a SC Integrator
Daniel Calderón, Federico Sandoval and Fernando Silveira
A Switched-Capacitor Filter with Dynamic Switching Bias OP Amplifiers
Hiroo Wakaumi
Efficient use of Gain-bandwidth product in active filters: Gm-C and
Active-R alternatives
Adriana C. Sanabria Borbon and Edgar Sanchez Sienencio
A 2.2 uW analog front-end for multichannel neural recording
José Luis Valtierra, Manuel Delgado-Restituto and Ángel Rodrı́guez-Vázquez
A Study of Characterizing Crosstalk Effects in 3-D Vias
Shadi Ms Harb and William Eisenstadt
LASCAS Session VI-Quintral (Thursday 23rd 13:30-15:30)
13:30
13:50
14:10
14:30
14:50
15:10
FPGA and HDL
HW/SW Codesign of Maximum Lyapunov Exponent Estimator
Luciana De Micco, Maximiliano Antonelli, Maria Liz Crespo and Andres Cicuttin
Fixed-point FPGA Implementation and Optimization for Henon Map
Chaotic Generators Design
Lei Zhang
Approximate Frequent Itemsets Mining on Data Streams Using Hashing and Lexicographic Order in Hardware
Lazaro Bustio, Rene Cumplido, Claudia Feregrino, Raudel Hernández León, Jose
Manuel Bande and Martin Letras Luna
A compact FPGA-based microcoded coprocessor for exponentiation in
asymmetric encryption
Luis Rodrı́guez-Flores, Miguel Morales-Sandoval, René Cumplido-Parra, Claudia
Feregrino-Uribe and Ignacio Algredo-Badillo
Nonrecursive Comb-Based Structure for Power of Three Decimation
Factors: Design and FPGA Implementation
Gordana Jovanovic Dolecek and Ricardo Garcia Baez
FPGA Implementation of a Feedforward Neural Network-Based Classifier Using the xQuant Technique
Thiago Marques, Emerson Machado, Carlos Llanos, Renato Coral and Ricardo
Jacobi
LASCAS - PRIME - Iberchip
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Bariloche 20-23 February 2017
LASCAS 2017
LASCAS Session VII-Condor (Thursday 23rd 16:00-17:00)
16:00
16:20
16:40
Biomedical
Gold-Copper-Based Biosensor for Impedance Analysis of Mammalian
Adherent cells
Fabián Giana, Fabián Bonetto and Mariela Bellotti
A Chopped Front-End System with Common-Mode Feedback for real
time ECG applications
Pablo Gardella, Emanuel Villa Fernandez, Juan Cesaretti and Eduardo Baez
Portable Electromagnetic Field Applicator for Magnetic Hyperthermia Experiments
Sergio Gonzalez, Enrique Spinelli, Alejandro Veiga, Diego Coral, Marcela Fernandez Van Raap, Pedro Mendoza Zélis, Gustavo Pasquevich and Francisco Sánchez
LASCAS Session VII-Amancay (Thursday 23rd 16:00-)
16:00
16:20
16:40
Control and modeling
Periphery VDD Collapse mode in SRAMs to allow switching off Periphery Voltage Island instead of doing it per memory
Krashna Nand Mishra, Ruchin Jain, Shailendra Sharad and Ravindra Kumar
Shrivastava
Thought Vectors and Spiking Neuron Circuits
Jonathan Tapson, Guido Zarella and John Harris
Closed Loop Frequency Control for an Hyperthermia Magnetic Field
Applicator
Enrique Spinelli, Sergio Gonzalez and Alejandro Veiga
LASCAS - PRIME - Iberchip
13
Bariloche 20-23 February 2017
LASCAS 2017
IBERCHIP Papers
Iberchip Session I-Quintral (Tuesday 21st 10:30-12:30)
10:30
10:50
11:10
11:30
11:50
12:10
Digital Design
The Design of Low-Power Transition-Signaling Asynchronous
Pipelines
Duarte de Oliveira, Kledermon Garcia, Lester Faria and Leonardo Romano
A Low-Latency Asynchronous Wrapper for GALS Systems Design
Duarte de Oliveira, Tiago Curtinhas, Lester Faria and Leonardo Romano
AMBA-AHB Network Interface for Core Interconnection in a
Network-on-Chip
Fernando Gaya, Cesar Zeferino, Douglas Melo and Eduardo Bezerra
Projeto de Portas Lógicas XOR com Redução de Potência por
Voltage Scaling
Leonardo H. Brendler, Clayton Farias, Alexandra L. Zimpeck, Ygor Aguiar,
Cristina Meinhardt and Ricardo Reis
Identificação de custos computacionais causados por contadores
de desempenho
Pedro Popiolek, Karina Machado and Odorico Mendizabal
Desempenho de Sistemas Multiagentes em Processadores Multicore
Bruno C. Rodrigues, Miguel J.Z. Da Costa Junior, Diana F. Adamatti,
Eder M. Gonçalves and Cristina Meinhardt
Iberchip Session III-Amancay (Wednesday 22nd 13:30-15:10)
13:30
13:50
14:10
14:30
14:50
FPGA and HDL
UFRGSPlace: Routability Driven FPGA Placement Algorithm
for Heterogeneous FPGAs
Julia Puget, André Oliveira, Jorge Tonfat and Ricardo Reis
Análise de Metodologias de Implementação e Desempenho em
FPGA dos Algoritmos Criptográficos Leves Simon, Speck e
Simeck
Claudio Costa, Fernanda Tachibana, Fábio Pereira and Edward Moreno
Synthesis of Auto-Synchronous FSMs from Synchronous Specification using FPGAs
Duarte de Oliveira, Higor Delsoto, Lester Faria and Leonardo Romano
Sistema supervisor de constantes vitales biomédicas utilizando
hardware reconfigurable
Federico Fernandez, Lucas Frutos and Daniel Ocampo
A Module for Remote Reconfiguration of FPGAs in Satellites
Felipe Viel and Cesar Albenes Zeferino
Iberchip Session IV-Amancay (Wednesday 22nd 16:00-18:00)
LASCAS - PRIME - Iberchip
14
Bariloche 20-23 February 2017
LASCAS 2017
16:00
16:20
16:40
17:00
17:20
17:40
Digital Desgin
Comparison between Direct and Indirect Learning for the Identification of Digital Baseband Predistorters
Joel Chavez and Eduardo Lima
Frequency-domain Polynomial Filter for Crest Factor Reduction
in Wireless Transmitters
Leandro Silva, Luis Lolis and Eduardo Lima
OTG: A Target Specification for Design of Synchronous Digital
Systems in the RTL Style
Duarte de Oliveira, Kledermon Garcia, Lester Faria and Leonardo Romano
Evolução de BBDs aplicados a Fault Collapsing
Gabriel Porto, Paulo F. Butzen and Denis Franco
Desarrollo de un Sistema de Control inalámbrico Centralizado,
orientado a la Inmótica
Franco Ezequiel Galeano, Jorge Rafael Osio, José Antonio Rapallini and
Antonio Adrián Quijano
Design and Development of Transcutaneous Electrical Stimulation Prototype for Neuromuscular Rehabilitation in Individuals
with Facial Palsy
Giovanni Francisco Manotas Rodrı́guez
Iberchip Session V-Amancay (Thursday 23rd 10:30-12:30)
10:30
10:50
11:10
11:30
11:50
12:10
Analog Design
An 130nm CMOS Sample-and-Hold dedicated to Double Quadrature BPS Receiver Architecture.
João Paulo Cunha, Guilherme Sionek, Mateus L. Matias, André Mariano,
Luis Henrique Lolis and Bernardo Leite
A CMOS 0.18µm Calibrated Gain Amplifier with DC Offset Cancellation Technique for very low starting band frequency
Ricardo Peres, Roberto Silva, Armando Lagana and Pedro Toledo
Voltage-to-Frequency Converter Design for System-on-Chip
Testing in 0.35m CMOS Technology
Luis Chaparro, Juan Carrillo, Elkim Roa, Hugo Hernandez and Wilhelmus
Van Noije
A Combined Memory and Envelope-Memory Polynomial Model
for RF Power Amplifiers
Carolina Machado and Eduardo Lima
A Functional Verification Method for an All-Digital Automatic
Gain Control Block
Marcio Oliveira, Wang Chau and Vinı́cius Martins
Evaluation of de-embedding techniques for impedance characterization of magnetic nanoparticles
Rafael C. de Medeiros, Leandro T. Manera, Marcos V. Puydinger Dos
Santos and Murilo F. Velo
LASCAS - PRIME - Iberchip
15
Bariloche 20-23 February 2017
LASCAS 2017
Iberchip Session VI-Amancay (Thursday 23rd 13:30-15:30)
13:30
13:50
14:10
14:30
14:50
15:10
Device variations - Resistitve Memories
Impacto da Variabilidade PVT em Somadores na tecnologia FinFET
Pablo M. Da Silva, Alexandra Lackmann Zimpeck, Ygor Quadros De
Aguiar and Ricardo Reis
PVT-Robust Ultra Low Voltage RC Filter Bulk-Driven Calibration Analysis
Roberto Silva, Lucas Severo and Wilhelmus Van Noije
Análise das margens de ruı́do de diferentes topologias de células
de memória SRAM de 1 bit
Roberto Almeida, Paulo F. Butzen and Cristina Meinhardt
Avaliação da Robustez de Votadores Majoritários à Variabilidade
PVT
Ingrid Oliveira and Paulo F. Butzen
Um Modelo Probabilı́stico para Criação de PTMs de Portas
Lógicas Combinacionais
Rafael Schivittz, Denis Franco, Lirida Naviner, Cristina Meinhardt and
Paulo F. Butzen
A Symbolic Expression for the Area of the Memristor Characteristics and Power Considerations
Arturo Sarmiento, Jesús Jiménez-Leon and Luis Hernández-Martı́nez
LASCAS - PRIME - Iberchip
16
Bariloche 20-23 February 2017
LASCAS 2017
PRIME-LA Papers
PRIME-LA Session I-Amancay (Tuesday 21st 10:30-12:30)
10:30
10:50
11:10
11:30
11:50
12:10
Analog and Digital Design
A 280uW Sub-threshold Balun LNA for Medical Radio using
Current Re-use Technique
Vasudeva Reddy K, Sravani K and Prashantha Kumar H
Grid-Voltage Sensorless Control of an LCL filter with Low Resonace Frequency
Roberto Fantino, Claudio Busada and Jorge Solsona
Design of a Delayless Feedback Path Free 2nd-order Two-Path
Time-Interleaved Discrete-Time Delta-Sigma Modulator- a New
Approach
Jafar Talebzadeh and Izzet Kale
HDL and Design Techniques Analysis for FPGA and ASIC Synthesis
Paola Ceminari, Ariel Oroz De Gaetano, Jorge Bellini and Martin Di Federico
Improved Lagrangian Relaxation-based Gate Size and VT Assignment for Very Large Circuits
Anitha Yella and Carl Sechen
Robustness Evaluation of FinFET Transistors under PVT Variability
Alexandra Lackmann Zimpeck, Cristina Meinhardt and Ricardo Reis
PRIME-LA Session II-Amancay (Wednesday 22nd 10:30-12:30)
10:30
10:50
11:10
11:30
11:50
12:10
Devices and Digital Design
Experimental Study of Progressive Breakdown in Different Conductance States of Resistive Switching Structures
Fernando Leonel Aguirre, Sebastián Matı́as Pazos and Felix Palumbo
Analyisis and Comparison of the CV-Dispersion of High-k, Bilayered MOS InGaAs/InP stacks
Sebastián Matı́as Pazos, Felix Palumbo and Fernando Leonel Aguirre
Synthesis and Design of a 4th Order Low-Pass DT Sigma-Delta
Modulator in a 130nm CMOS process
Daniel Calderón, Federico Sandoval and Fernando Silveira
Proposal of a fuzzy logic controller for the improvement of irrigation scheduling decision-making in greenhouse horticulture.
Arys Carrasquilla-Batista and Alfonso Chacón-Rodrı́guez
Programmable Assertion Checkers for Hardware Trojan Detection
Uthman Alsaiari, Fayez Gebali and Mostafa Abd-El-Barr
AES block cipher implementations with AMBA-AHB interface
Paola Ceminari, Ariel Arelovich and Martı́n Di Federico
LASCAS - PRIME - Iberchip
17
Bariloche 20-23 February 2017
LASCAS 2017
LASCAS is the international
symposium and flagship event of the
IEEE Circuits and Systems Society
in Latin America.
LASCAS is
internationaly recognized symposium and a such it will continue to deepen
the interaction between different research groups from the country, the
region and the world, giving place to the integration of existing lines of
scientific and technologic research. These lines include Integrated Circuits,
Power Electronics, Communication’s Systems, MEMS, Microfluhidic Systems,
Ceramic Packaging and Fabrication Technologies, among others. In this way,
it will be possible to further the resolution of problems which require the
interaction of múltiple fields of expertise, such as IoT Systems, Systems On
Chip (SoC), Systems on Package (SoP), Sensor Network, among others. The
event promotes active participation between technology based companies in
order to bring together the research with the reality of today’s industry. .
PhD Research in Microelectronics and
Electronics Conference (PRIME): It is a
new conference where PhD students and
post-docs with less than one year post-PhD
experience can present their research results
and network with experts from industry, academia and research. The 1st
Conference on PhD Research in Microelectronics and Electronics in Latin
America (PRIME-LA 2017) will be held from the 20th to the 23th of February
2017 in Bariloche Argentina. PRIME-LA 2017 conference program will reflect
the wide spectrum of research topics in Microelectronics and Electronics,
building bridges between various research fields.
The IBERCHIP workshop provides an
annual forum to academic and industrial
researchers from Iberoamerican countries
in which to exchange experiences, share
knowledge and establish relations to foster
the development of activities related to the
field of Microelectronics. Special emphasis
is put in the improvement of education
and training, and in the promotion of joint
cooperative projects.
LASCAS - PRIME - Iberchip
23
Bariloche 20-23 February 2017