a
ERRATA
These changes have been made in REV B issued on May 25, 2000
PageNo.
ADMC401
Description
4
ADMC401-PB
Add “ADMC401-ADVEVALKIT
ADMC401-ADVEVALKIT” and “ADMC401-PB
ADMC401-PB” to the Ordering Guide Table
ADMC401-ADVEVALKIT
19
Delete (POR) in the paragraph heading:
33
In the PWM Shutdown section, the following sentence is required to clarify the condition of the
three low side PWM signals when the PWMTRIP pin is in the SR Mode
*Note, however, when the PWMTRIP pin is in the SR mode, the three low side PWM signals
from the three-phase timing unit will remain in the ON state
36
Figure 30:
37
Text in right column, 3rd line from top:
38
Text in right column, section “EET
Register”, 2 nd paragraph, 1st sentence:
EET Status Register
Change from “....the encoder event timer is set to zero and ...” to “...the encoder event timer is
set to one and...”
Reset and Power On Reset Circuit
The uppermost “3t
3tCK
CK” label should be replaced: “ttCK ”
EISLATCH
word “EISZLATCH
EISZLATCH” should be spelled “EISLATCH
EISLATCH”
EISZLATCH
The following sentence should be deleted
deleted: “In the case of a direction reversal, the contents of
the EETDELTAT register is valid, representing the time from the direction reversal to the instant
at which the EIUCNT register is read”
in the Unit Column, the word “Bits
Bits” should be “MHz
MHz”
Bits
MHz
39
Table VI:
43
Figure 34:
“SCLK1”
46
Table VIII (continued from previous page): “EEE
Register” should be swapped
EEE Timer Period Register
EET Delta Timer Register
with “EET
Register”
48
0 ” should
Figure 36: The PWMGATE (R/W) register and the PWMGATE (R/W) register: Bit “0
0” not blank (undefined)
be shown with a “0
49
Figure 37: The EIUSCALE register should be blank (undefined) and not have zeros in the
white rectangles; bits 0 through 7. These bits are undefined at reset
There are 2 pin pairs labeled “TFS1
TFS1”.
TFS1
The lower “TFS1
TFS1 pins should be labeled
If you have any questions regarding this Errata please send an email to "[email protected]".
REV.A Errata
5/23/00
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