Chapter 2
Interconnect Aspects in Design Methodology
and EDA Tools
2.1
Interconnect Planning
The physical layout of a VLSI system is usually represented at a high level of
abstraction as a chip-plan, also called a “floor plan”. As described in [Cong 01], the
first step in planning is to generate a physical hierarchy, which defines the global,
semi-global, and local wires. This step is necessary because systems are often
defined initially as a logical hierarchy, where blocks are clustered together
according to functional behavior, while physical distances and geometrical relationships are ignored. A logical hierarchy only represents the nesting of functional
blocks in the high-level architectural description (see Fig. 2.1). A physical hierarchy is better in mapping onto a two-dimensional layout surface than is a simple
logical hierarchy because it considers wires and physical sizes. In the physical
hierarchy, connections between the different blocks obtained from top-level
partitioning are the global interconnects, and the connections between different
modules within the same block are semi-global or local.
The second step is the actual floor planning, wherein the physical hierarchy is
mapped onto the x–y plane. In the floor plan, the area and the location are assigned
to each block, routing regions are added, and all the global signals are assigned to
specific metal layers (see Fig. 2.2). Typically, floor planning is done manually with
the aid of placement and global routing tools. The interconnect synthesis techniques
described below are then applied to the global and semi-global interconnections to
determine the best topology, layer assignment, wire width, and spacing, in order to
satisfy the performance constraints.
The design steps described above assume that a specific interconnect architecture is given. Interconnect architecture planning involves making decisions about
the required number of routing layers in the chip, the wire thickness, and the
nominal width and spacing in each layer. It includes the allocation of metal
resources for the power supply distribution and clock network, as well as the
characterization in terms of the target clock rate. A number of low-level routing
© Springer Science+Business Media New York 2015
K. Moiseev et al., Multi-Net Optimization of VLSI Interconnect,
DOI 10.1007/978-1-4614-0821-5_2
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2 Interconnect Aspects in Design Methodology and EDA Tools
Fig. 2.1 Illustration of a logical hierarchy: (a) schematic representation, (b) hierarchy graph
representation
4200λ
10 I/O PADS
control: 1500 λ x 400 λ
10 I/O PADS
Wiring channel: 30 tracks = 240 λ
alucontrol:
200λ x 100 λ
10 I/O PADS
zipper: 2700 l x 250 l
bitslice
bitslice
bitslice
bitslice
bitslice
bitslice
bitslice
bitslice: 2700 l x 100 l
datapath
10 I/O PADS
Fig. 2.2 Illustration of physical hierarchy and a floor plan, corresponding to the logical hierarchy
shown on Fig. 2.1
2.2 Interconnect Synthesis
13
layers are allocated for local interconnects, while other layers are allocated for
semi-global and global signals. Each metal layer is assigned a preferred routing
direction. For leading new products in a new technology, all of these decisions are
actually made in conjunction with the floor planning.
The interconnect planning process described above addresses large blocks and
global signals. Traditionally, it has been used only in custom design of high-end
products such as microprocessors, while physical layout of simpler products is
generated automatically from the logical hierarchy, practically skipping the interconnect planning stage. In [Dally 00], the use of custom techniques was proposed
for wire planning within functional blocks in order to improve the performance,
power, and area of ASIC (application-specific integrated circuit) designs without
affecting the development cycle. With an increasing impact of wiring delay and
design complexity, these custom techniques assume more importance as fully
automatic design flows fail to meet aggressive design constraints. In custom design,
it is possible to control the physical structure of the layout, while in automated
design the layout is generated automatically with little or no control of the structure
of the physical implementation. Automatic tools first place the logic modules and
then route the signals; thus, the intrinsic structure of the design is lost. Contrarily, in
custom design, first the critical signals are routed and then the modules are placed.
The fundamental idea of applying custom design techniques to an ASIC is based on
structuring the most critical wires and leaving the rest to automatic tools. Critical
wires that can be structured are global signals – such as clock signals, buses, datapath bits, and word lines. Structured wiring within functional blocks is important
for high-performance ASICs; furthermore, it is consistent with interconnect-centric
design.
Performance estimation is a critical task in interconnect planning, wherein
several floor plan options are explored. Unfortunately, detailed information on the
granularity of wire segmentation, buffer locations and sizes is not available at this
level of abstraction. Interconnect planning that simply uses delay models based on
wire length does not correlate well with the optimization techniques which are
applied later in detailed interconnect synthesis. Consequently, the performance
estimation models that are used in interconnect planning should include predictions. These predictions are based on technology parameters such as wire sheet
resistance, capacitance per unit area and fringing capacitance coefficients, load
capacitance, and driver resistances, which are described in Chap. 3.
2.2
Interconnect Synthesis
The next major task in interconnect-centric design is interconnect synthesis, which
determines the optimal interconnect structure for each net, or the set of metal
conductors that transmit an electrical signal. The net is represented by a hyperedge
in the hypergraph which describes the logic hierarchy. Typically, the electrical
signal is a voltage generated by a logic gate (the signal source, known as a driver)
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2 Interconnect Aspects in Design Methodology and EDA Tools
Fig. 2.3 Modeling of a net
as a binary tree (right) and
as an embedded Steiner tree
in the x–y plane (left). The
net connects a source
terminal (output of the
driver gate) to several sink
terminals (inputs of
receiving gates)
and the wires of the net transmit the signal to the terminals of several receivers. A
net is often modeled conceptually as a routing tree, typically a binary tree (see
Fig. 2.3).
The design of each net involves the mapping of the tree into a topology of wires
embedded as a Steiner tree [Cong 96, Sherwani 95] in the x–y plane, where the
coordinates of each terminal are given. In addition, the insertion of buffers, including their locations and sizes, is involved as is the determination of wire width and
interwire spacing, so that the performance and signal integrity requirements could
be fulfilled under constraints of area and routability.
In order to simplify the synthesis task, the problem is typically decomposed into
global routing, cell placement, and detailed routing. At the global routing stage, the
terminals of each global and semi-global net are identified in the floor plan. The net
is assigned to go through certain routing regions in the floor plan, without paying
attention to details such as exact layer, wire ordering, width, spacing, contacts, vias,
etc. The detailed routing stage is performed after cell placement, when the terminals
of each cell have been determined. At the detailed routing stage, each routing area is
handled separately. All the geometrical details listed above are taken care of during
detailed routing, while layout design rules are enforced by the router tool.
Practical routers work net by net, performing metal layer allocation and placing
wire segments. Since each routed net becomes an obstacle for the following nets,
the order of handling nets is of extreme importance. In the complete physical
layout, each net is typically represented by a routing tree (Fig. 2.3), in which the
root of the tree represents the driving point, or signal source, and the leaves of the
tree represent all signal receivers, or signal sinks. The optimal routing problem is
computationally intractable (NP hard) and it becomes much harder as the system
complexity grows. Often, routers try a different order of handling nets, and human
intervention is sometimes required in the process of routing. Modern routers need to
become more and more sophisticated, since their task should involve optimizations
and tradeoffs among several objectives: delay, power, area, etc.
The router also has to handle congestion minimization. One of the methods
usually employed for this task is called “rip-up and reroute.” It is used to find
alternative routes for blocked nets, and iteratively converges to a low-congestion
solution: the routing engine searches the layout region around the congested area,
and finds an alternative connection for the net. Another common method is iterative
deletion, which begins with multiple routes for each net, and iteratively removes
2.4 Future Requirements for Interconnect Synthesis
15
redundant routing paths with the highest congestion, until each net has only one
route. The two strategies can be combined: rip-up and reroute can be initially used
to obtain multiple routing solutions for some or all nets; while iterative deletion can
be used to determine the best routing solution for each net. Wiring congestion is a
critical design factor that strongly impacts routability and timing, which should be
considered in logic synthesis as was demonstrated in [Pandini 02], where structurally less congested circuits can be routed within a smaller die size and with fewer
metal layers.
2.3
Final Generation of Interconnect Layout
Aggressive interconnect optimization may result in complex interconnect structures
with many buffers, variable wire widths, and different spacing rules between
adjacent wires to minimize capacitive coupling. These requirements must be
taken into account during or after detailed routing. Ideally, the routing algorithm
would support multilayer, variable-width, and variable-spacing interconnections.
To overcome the ordering problem associated with a net-by-net routing, and to
support efficient rip-up and reroute: first, the available routing resources are estimated; second, a multi-iteration approach evenly distributes the nets in the routing
regions, in order to minimize wiring congestion. It is important to point out that
during this phase, the resynthesis capabilities of layout tools are limited, and cannot
significantly modify the wiring structures previously obtained. Consequently, the
most effective interconnect optimization techniques must be applied at higher level
of abstraction, particularly at the floor-planning stage.
2.4
Future Requirements for Interconnect Synthesis
State-of-the art layout automation tools have evolved over the years, driven primarily by the need to contain the complexity of the physical design problem and by
the need to save silicon area as a key to reducing manufacturing cost. In recent
years, considerations of circuit speed and power dissipation have been included too.
However, current layout tools do not exploit many of the possible optimizations.
Specifically, net-by-net operation of the algorithms and tools leads to wire structures which are very dense in some areas while there are large spaces in other areas.
Since wire widths and interwire spaces have been shrinking in every technology
generation, and due to nonuniform scaling, interwire capacitances have become
dominant. These capacitances strongly affect power and delays. A main goal of this
book is to treat wire width and interwire spacing as important resources which
should be allocated wisely. This book is focused on simultaneous optimization of
widths and spaces of multiple-nets, rather than optimizing each net independently
(see Fig. 2.4). Using the methods of simultaneous multi-net optimization, we
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Fig. 2.4 An interconnect layout clip of metal 4 from a commercial microprocessor manufactured
in 32-nm technology: general layout. There are opportunities to space wires further apart so that
cross-capacitances are reduced as well as interconnect power and delay
demonstrate significant improvement of power and speed just by post-processing of
layouts generated by current commercial tools (without changing layout topology).
The new techniques in this book can be even more effective if integrated into future
routers and applied earlier in the layout design flow.
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