Hardware Description Languages
Using VHDL to Design
Digital Circuits – Part 1
 HDLs
allow designers to work at a higher level of
abstraction than logic gates
 As with programming languages, HDL descriptions are
compiled into a lower level representation
» low level form can be simulated for logical correctness
» and, can be converted to a circuit specification using a
library of primitive components and a set of constraints
that affect circuit cost and performance
 assignments
 processes
and if-then-else
unintended storage
 separation principle
 avoiding
 But
don’t confuse hardware design with software
» software is translated into sequential instruction sequence
» HDL descriptions must translate to physical circuits
» circuits are inherently parallel with many things going on
at once
‹#›
Vector Assignments
Binary Coded Decimal to Excess-3 Code
-----
Binary Coded Decimal to Excess 3 converter
ABCD is 4 bit input value
start comment
WXYZ is 4 bit output value
with “--”
WXYZ = ABCD + 3
entity bcd2xs3 is
port (
A,B,C,D : in std_logic;
W,X,Y,Z : out std_logic
);
end bcd2xs3;
entity declaration
defines module
interface
BCD xs3
decimal
ABCD WXYZ
0
0000 0011
1
0001 0100
2
0010 0101
3
0011 0110
4
0100 0111
5
0101 1000
6
0110 1001
7
0111 1010
8
1000 1011
9
1001 1100
W=A+BC+BD
X=B’C+B’D+BC’D’
Y=CD+C’D’
Z=D’
architecture a1 of bcd2xs3 is
begin
W <= A or (B and (C or D));
X <= ((not B) and (C or D)) or
(B and (not C) and (not D));
Y <= C xnor D;
Z <= not D;
signal assignments
end a1
equivalent to logic
meaning of VHDL
is specified circuit
not sequential execution!
equations
The conditional signal assignment can make logic equations
easier to understand (and write)
x
1
 Example:
c
General form
x <=
v1 when condition1 else
v2 when condition2 else
v3 when condition3 else
... else
vN
exclusive-or
gate
b
v1
vn–1
vn
using binary
addition operator
‹#›
c(3 downto 0) <=
"0100" when a /= b else
"1011" when a = '1' else
"1001";
is equivalent to
0
a

architecture a1 of bcd2xs3 is
begin
xs3(3) <= bcd(3) or (bcd(2) and (bcd(1) or bcd(0)));
xs3(2) <= ((not bcd(2)) and (bcd(1) or bcd(0))) or
(bcd(2) and (not bcd(1)) and (not bcd(0)));
xs3(1 downto 0) <= (bcd(1) xnor bcd(0)) & not bcd(0);
-- alternate specification
& concatenates
-- xs3 <= bcd + b"0011";
signals
specify more simply
end a1
0
1
logic vector
declarations
Conditional Assignments with Vectors

y
z
entity bcd2xs3 is
port (
bcd:in std_logic_vector(3 downto 0);
xs3:out std_logic_vector(3 downto 0)
);
end bcd2xs3;
‹#›
Conditional Signal Assignment
c <= x when a /= b else
y when a = '1' else
z;
-- Binary Coded Decimal to Excess 3 converter
-- xs3 <= bcd + 3
1
v2
1
1
0
0
x
condition1
condition2
conditionn–1
0
‹#›
c(3) <= "0" when
"1" when
"1";
c(2) <= "1" when
"0" when
"0";
c(1) <= "0" when
"1" when
"0";
c(0) <= "0" when
"1" when
"1";
a /= b else
a = '1' else
a /= b else
a = '1' else
a /= b else
a = '1' else
a /= b else
a = '1' else
‹#›
1
Practice Questions
1.
Practice Questions
Draw a circuit that implements each of the following VHDL code
segments, assuming a-d are all single bit signals in both cases
x <= a and b;
y <= x or (c and d);
z(0 to 1) <= (a and c) & (x or c);
2.
1.
Draw a circuit that implements each of the following VHDL code
segments, assuming a-d are all single bit signals in both cases
x <= a and b;
y <= x or (c and d);
z(0 to 1) <= (a and c) & (x or c);
x <= a and b;
y <= x or c;
z <= “100” when x = ‘1’ else
“010” when y = ‘0’ else
“001” when a < b else
“111”;
Write a VHDL code segment that implements the circuit shown
below
A
B
4
1
0
4
C
D
4
X
Y
‹#›
Practice Questions
1.
‹#›
Practice Questions
Draw a circuit that implements each of the following VHDL code
segments, assuming a-d are all single bit signals in both cases
2.
Write a VHDL code segment that is implemented by the circuit
shown below
4
A
B
x <= a and b;
y <= x or c;
z <= “100” when x = ‘1’ else
“010” when y = ‘0’ else
“001” when a < b else
“111”;
1
0
4
C
D
4
X
Y
‹#›
‹#›
Selected Signal Assignment
Comments in VHDL
Selected signal assignment can be viewed as special case of
conditional signal assignment
 Example:
 Add

with x select
c <= '0' when "00",
'1' when "01" | "10",
b when others;
» good idea to include your name and date, as well
 Every
VHDL module (entity-architecture pair)
should be preceded by a comment
can be implemented using a single multiplexor stage
'0'
'1'
b
0
1
2
3
» explain what the module does
» explain the role of the input and output ports
c
 Comment
2
 Comment
x

Resulting circuit is more compact and faster than circuit
produced by conditional signal assignment
a comment to a line of VHDL, using two
dashes; e.g. -- this is a comment
 Every source code file should start with a short
comment explaining its role
signal, function, procedure declarations
major sections of architecture
» help reader understand purpose of different code sections
» don’t just re-state the obvious
‹#›
‹#›
2
“Conflicting” Assignments
Processes and if-then-else

Example:
process block enables use of
complex statement types
 The
entity foo is port(
a, b: in std_logic;
c, d: out std_logic_vector(3 downto 0));
end foo;
sensitivity list for
architecture bar of foo is begin
combinational circuits
process (a, b) begin
must include all
if a /= b then
c <= "0010"; d <= "1100"; signals whose values
are used in process
elsif a = '1' then
c <= "1101"; d <= a & b & "01";
else
c <= "0100"; d <= "10" & b & a;
end if;
note that c,d defined under
end process;
all possible input conditions
end bar;
- REQUIRED
code segment
architecture bar of foo is begin
a <= '1'; b <= a; a <= '0';
end bar;
is incorrect, because the two assignments to a conflict
 However,
the following is allowed
architecture bar of foo is begin
process(a) begin
a <= '1'; b <= a; a <= '0';
end process;
end bar;
in such situations, the first assignment is ignored
 Within
process, assignments that come later in text,
logically replace earlier assignments to same signal
» such replacement may be conditional on where assignments
appear (e.g. in statement list of an if-then-else)
‹#›

Within a process, if value of a signal is not specified for
some input condition, it means that signal is unchanged
 Example

Storage elements are required to implement circuit with
the specified behavior
• if one accidentally omits a condition for a signal, unintended
storage elements are synthesized
‹#›
Separation Principle
VHDL code segment defining several signals can
be re-written to separate the different signals
-- code segment defining x
x <= x"0000";
if a = b then x <= y; end if;
-- code segment defining y
y <= x"abcd";
if a /= b and a > c then
y <= b;
end if;
-- code segment defining z
if a = b then z <= b;
elsif a > c then z <= a;
else z <= x + y;
end if;
» statement order matters within each segment,
but order of segments does not matter
‹#›
2. Rewrite the VHDL module shown below
using a process block and an if-then-else
statement. (SLV is used below as an
abbreviation for std_logic_vector.)
entity foo is port(
1. Rewrite the following VHDL module
a: in std_logic_vector(2 to 0);
using only ordinary signal assignments
b,c,d: in SLV(3 downto 0);
(no conditional assignments).
x,y: out SLV(3 downto 0));
entity foo is port(
end foo;
a,b,c,d: in std_logic;
architecture arch of foo
x: out std_logic;
signal z: SLV(3 downto 0);
y: out std_logic_vector
begin
(1 downto 0);
z <= b xor c;
end foo;
with a select
architecture arch of foo
x <= z when “000”,
begin
c when “001”|“100”,
x <= b and c when a=‘0’ else
d when “110”|“111”|“101”,
not c
when a>b else
b+c when “011”,
a or d;
c+d when others;
y <= (a & d) when a=‘1’ else
y <= c+d when a = “010” else
(b & (not c)) when
d when a >= “101” and
(b=‘0’ and c=‘1’) else
a <= “111” else
‘1’ & c;
z
when a = “000” else
end arch;
b+c when a = “011” else
c
when others;
end arch;
Exercises
A
x <= x"0000";
y <= x"abcd";
if a = b then
x <= y; z <= b;
elsif a > c then
y <= b; z <= a;
else
z <= x + y;
end if;
Example:
entity foo is port(
a, b: in std_logic;
c, d: out std_logic_vector(3 downto 0));
end foo;
initial assignments
architecture bar of foo is begin
define “default”
process (a, b) begin
values for c and d
c <= "0100"; d <= "10" & b & a;
if a /= b then
c <= "0010"; d <= "1100";
elsif a = '1' then
c <= "1101"; d <= a & b & "01";
end if;
end process;
What values are assigned to
end bar;
c, d if we rearrange so
if-then-else comes first?
x
process(a,b) begin
D
a
if a = '1' then
C D-latch
b
not a flip flop
x <= '0';
elsif b = '1' then
x <= '1';
end if; -- x retains its value when a=b=0
end process;
Easy way to avoid unintended storage is to start process
with assignment of default values to all signals assigned a
value inside the process
‹#›
Default Values
Avoiding Unintended Storage

-- note: b = '0'
‹#›
‹#›
3
Solutions
1. The revised architecture is.
architecture arch of foo
begin
x <= ((not a) and b and c) or
(a and (not b) and
(not c)) or (a and b);
y(1) <= a or b or (not c);
y(0) <= (a and d) or
((not a) and b and c);
end arch;
2. The body of the revised architecture
appears below
begin
z <= b xor c;
process (a,b,c,d,z) begin
if a = “000” then
x <= z; y <= z;
elsif a = “001” or a = “100”
then
x <= c; y <= c;
elsif a>=“101” and a<=“111”
then
x <= d; y <= d;
elsif a = “011” then
x <= b+c; y <= b+c;
else
x <= c+d; y <= c+d;
end if;
end process;
end arch;
‹#›
4