USOO5844535A
Ulllted States Patent [19]
[11] Patent Number:
Itoh et al.
[45]
[54]
LIQUID CRYSTAL DISPLAY IN WHICH
EACH PIXEL IS SELECTED BY THE
COMBINATION OF FIRST AND SECOND
0 495 428
0 552 952
0 586 155
ADDRESS LINES
43 44 808
7/1994
3-271795
12/1991
Japan .
7-64051
3/1995
Japan .
[75]
Inventors: Goh Itoh, Tokyo; Haruhiko Okumura,
5,844,535
Date of Patent:
7/1992
7/1993
3/1994
Dec. 1, 1998
European Pat. Off. .
European Pat. Off. .
European Pat. Off. .
Germany .
FujisaWa; Hisao Fujiwara, Yokohama,
all of Japan
Primary Examiner—Chanh Nguyen
Attorney)
Or Firm_Ob10n, spivak, Mcclelland,
ASSIgIlGCZ Kabushiki Kaisha Toshiba, Kawasaki,
Japan
Maier & Neustadt, PC.
[21] Appl. No.: 666,262
[57]
ABSTRACT
[22] Filed:
Jun. 20, 1996
[30]
Foreign Application Priority Data
A liquid crystal display includes a liquid crystal display
panel having a pixel matrix consisting of a plurality of
pixels, a signal line driver, a roW address line driving circuit,
Jun. 23, 1995
[JP]
Japan .................................. .. 7-157910
a row pixel Counter Circuit, a row address Signal generating
[51]
Int. Cl? ..................................................... .. G09G 3/36
Circuit, a Column address line driving Circuit, a Column pixel
[52]
us CL ________________ __
__ 345/92; 345/103
counter circuit, and a column address signal generating
[58]
Field of Search ................................ .. 345/87, 88, 92,
Circuit Each Pixel includes a liquid Crystal uhih a Storage
345/93, 99, 103, 98; 349/36, 33, 42, 41,
capacitor, and a switching unit consisting of sWitching
48
devices. The sWitching unit is turned on and off by a
cooperation of a roW address line and a column address line.
[56]
References Cited
While the switching unit is ON, an image signal is supplied
us PATENT DOCUMENTS
from a signal line to a pixel electrode. This reduces Write
operations to pixels and thereby reduces the poWer
Z/
gitazima etlal' """""""""""" "
consumption, and also improves the Writing characteristic
5:691:783 11/1997 N352: :1.' I: ...................... .: 345/92
and the holding Characteristic Which differ from one Pixel to
another.
FOREIGN PATENT DOCUMENTS
0 112 700
7/1984
European Pat. Off. .
20 Claims, 27 Drawing Sheets
SIGNAL LINE DRIVER
212
I
if 220
—]I
2520
Y
T
:3
O
g
SWLIJ
cLc~— v
_y[
(
m
P“
1
g
5%
1.
I
T
J. .L
J. l
T
.L l
T
.L l
22,
I
221
g
11
T
.L l
X3
11
X3
>
1.
X3
f
X3 221
f
1.
P‘
(
l .1.
1
1
J_ .1
.L .1
>—-—
I
T
1.
1.].
11
l .1.
I22‘
>--—
I
.54 T‘
N
T
.L .I.
>—'
o
J; 220
P
com
l .l.
5 —v
?,
J; 220
V
com
T1
a d‘
l
s
(/2
C
CPL
.L l
g
,,
E20
T1
i 1:1:
~222
l1
*
l1
--
~1:?
~ 222
PIXEL BLOCK ADDRESS LINE DRIVING CIRCUIT
3.26
U.S. Patent
Dec. 1, 1998
5,844,535
Sheet 2 0f 27
{J1
F1
25
AD.
4
KF
37.
2KS
HA
M
K@E5i|2Ov8m3:
/<
l20
{J2$K5i.Ivm
5
_
%
K.
A
F
u-L
A
wzjmo
FIG.
2B
56:W3t
i
A
J.._
H_
m
3E2,.
A
A
. .3
E21
U.S. Patent
Dec. 1,1998
K
Sheet 3 0f 27
Fi
8* IX
J
K
F2
if X
VA‘
<
5,844,535
I
31 X
1/
rr
I!
I!
VA3
n
H
HA2
J,
”
HA3
,1
H
F
F I G.
7f
3A
l Pm P1,2 Pu Pm
X P2.1 P2,2 P2,.3 P2,4
F l 6,
P3,! P3,2 P3.3 P3,4
3B P4,1 P4,2 P43 P4,4
F1
a‘,
F2
ON
ON OFF ?t
0N OFF
ON
\
0N
OFF
OFF ON
ON OFF
OFF OFF OFF
OFF ON ON
I
FIG. 30
'
FIG.
3D
U.S. Patent
Dec. 1,1998
Sheet 5 0f 27
5,844,535
SIGNAL LINE DRIVER
_
L
I
g
1;’
—-I—
45
“
21
l
/
.,_I—I
mu
(0E
-
swz l
go
CI
80
<2
S
I
l
I
I
SW1
CLC
:: (:3
32
Q0‘;
Q0
22\
L,“
2o\
-\
Vcom
‘a
T
F |
COLUMN
ADDRESS LINE
DRIVING CIRCUIT
5
SIGNAL LINE DRIVER
S
T
I
2‘
--——II
4
g
.1.
:g
n
a;
sw2
g”
l
' SWI
ow
L
<_z_
§Z
8%
4
CLC
22N
w
.L
2- C3
2o\
*5
Vcom
T
F I 6.
5B
gawm's AEPFIESFT
I
U.S. Patent
Dec. 1,1998
Sheet 6 0f 27
5,844,535
INPUT IMAGE SIGNAL
0
8‘
~ SIGNAL LINE DRIVER
VA E
62\
64
I
LI
I’
IéJP
35
~60
mg
$5
PANEL
go
0
ROW PIXEL 33
4E
CIRCUIT
on:
COUNTER
\GI
33
(ID
1»
R
'53
RM
COLUMN ADDRESS LINE ~63
DRIVING GIRGuIT
66
I
FREQUENCY
» DIVIDING
CIRCUIT
60-HZ
DRIVE SIGNAL
20-HZ
I
|
A2
A
DRIVING
DR "E S G“ L
I2-IIz
DRIVE sIGNAL
s4
DIsPLAY COLOR T0
DRIVING FREQUENCY
REFERRING SECTION
FIG.
COLUMN
EAEFILfER
SELECTOR
CIRCU‘T
~57
6
65
I
FREQUENCY
55
SI
68
I
86
U.S. Patent
Dec. 1,1998
Sheet 7 0f 27
5,844,535
i 35
SELECT ION SIGNAL
GENERATOR
T7
FIG.
FIG.
7A
7B
69
1
U.S. Patent
Dec. 1,1998
Sheet 8 0f 27
5,844,535
INPUT INIAGE SIGNAL
0 I
Si
SIGNAL LINE DRIvER
III F
S2~
~8I
LI
r
LLI
'\
5:
(I)
884
8
Q5
ow PIXEL s3
OUNTER
CIRCUIT
so
PANEL
go
<1’
32
3g
1,
LI HA
coLuNIN ADDRESS LINE x83
DRIvING CIRCUIT
86
‘
FREQUENCY
DIvIDING
CIRCUIT
A2 87
IIIIIUIIIIITE
885
‘
DRIVING
LOW-RATE
DRIVING
s4
FREQUENCY
SELECTOR
DYNAMIC IMAGE / STILL
IMAGE SELECTION SIGNAL
S5
FIG.
S6
8
%‘.’,IEI_‘"
COUNTER
CIRCUIT
U.S. Patent
Dec. 1,1998
Sheet 9 0f 27
INPUT IMAGE sIGNAL
O
94 s‘
92
i
9,
sIGNAL LINE DRIVER ,1
32
i vA Fl
Row PIXEL 33
LI
F
COUNTER
CIRCUIT
90
I;
3,:
3
mg
CK
9? 0
KBE’RESS
Row ADDREss
SIGNAL
AI
J
‘Q6
0o
2;
SIGNAL
GENERATING
5,844,535
PANEL
32
3g
cIRcuIT
L
I
ggl-uggls
COLUMN ADDRESS
983M
3'6"“
GENERATING
HAIJ
LI
COLUMN ADDRESS LINE
A2
DRIVING cIRcuIT
CIIfRCUIT
97
S4
F l G_
93
[95
COLUMN PIXEL
9A
COUNTER cIRcuIT
/
AII
FI
{A1
F2
l 83
M
vAI
G
:)—
>P UN
FIG. 98G
25/
CK
RSEHGIFTER
T
VAE
I’
U.S. Patent
Dec. 1,1998
Sheet 10 0f 27
5,844,535
"(NORMALI
Sl
QX_4
AQX >GX+§<QX+2>\_‘
<
l/n-FOLD-RATE
552%?“
NON_SELECT|ON
(THIS EMBODIMENT)
m
FIG.
10A
VAX-4 VAX-3 VAX-2 VAX-1 VAX VAx+1 VAX+2
((NORMAL) CK ‘"1 U U U U U U
A!
r
#1‘
I/l'l-FOLD-RATE
U PROCESSING
DUR l NG
NON- SELECTION
PER IOD
(THIS
—-4
EMBODIMENTIM In
FIG.
{OB
U.S. Patent
Dec. 1,1998
INPUT IIIIIAGE SIGNAL
Sheet 12 0f 27
III
g
SIGNAL LINE DRIVER
SI
Q
II4
II2
I
I
Row PIXEL
32
couNTER
VA F
LISZ
f
%
CIRCUIT
IIo
3:
1')
“>32
J
Q5
Q
H9\
oNE-FRANIE
MEMORY
IIG
2%
\
0CD
PANEL
IGIIIIII
T»
SIGNAL
HA
GENERATING
cIRcuIT
H87
s3
5,844,535
H3
A
L‘ ‘
COLUMN ADDRESS LINE
DRIVING cIRcuIT
S4
H8\
36
S7 IH5
DISPLAY
TO GATE COLOR
voLTAGE
S5 @QEAGE
GENERATING
COUNTER
REFERRING SECTION
CIRCUH
CIRCUIT
F I G.
I2A
I 85
GATE voLTAGE
SELEcToR
(G6)
vGI
I
SWXK”
S
—c
HAD
0
SWXY
'
vG2
a
g -*
HAn-I
$Wx,Y-I o
V63
0O
HAn-z
TTT
F l G.
12 B
U.S. Patent
Dec. 1,1998
Sheet 14 0f 27
5,844,535
Isa
INPUT IMAGE SIGNAL
G
so
I
AI
INIAGE SIGNAL
A2
DIvIDER
SI
I34
3 VA {1 I30I
Row PIXEL s3
I36
3
ROW
ADDRESS
SIGNAL
L;
Row ADDRESS
$3
825
GENERATING
3:
PANEL
c:
SIGNAL
2%
AI
CIRCUIT
sz‘q
f
COUNTER
CIRCUIT
I
SIGNAL LINE DRIVER
I32
I
I31
3>
0;
0:0
L
ggbglégs
SIGNAL
GENERATING
cIRcuIT
goéglml ADDRESS
HA J
'
‘L.
COLUMN ADDRESS LINE
A2
I33NDRIVING CIRCUIT
3
s4
*3?
COLUMN PIXEL
‘35* COUNTER CIRCUIT
FIG.
14
U.S. Patent
Dec. 1,1998
Sheet 15 0f 27
mcRuT IMAGE SIGNAL
nzm INTERLACE
PROCESSING CIRCUIT
n COUNTER
GB
33
4T’
38
\
SCAN LINE
SELECTION
31
SIGNAL
GENERATING
CIRCUIT
g
i
3
E
I
“Jo
'
50
I
J2
32
/
PANEL
|
:5
1
3%
I
|
F | 6.
_\_)
15A
GE
PRIOR ART
46s
~44
~44
l
1
SW
CLC
S
46
/
SIGNAL LINE DRIVER /
32
S
34
36
40“ CIRCUIT
42\
5,844,535
C
s
l
F I G.
PRIOR ART
l
{5 B
U.S. Patent
Dec. 1, 1998
Sheet 17 0f 27
1A
I8
(I ICJUDEIEIEIDEIEI
2
3
4
< 5
6
T
a
9
5,844,535
0N EIEIIIIEIEIEIEIDCIEI
EIIEIEIEICIEIEIUEI
ON EIEJEIDEJEIEJEIEIU
DEIIEIEIIDEIEIEI IMAGE 0N DEIDEICIEICIEIDEI
EIEIUIEIIEIDEIEI SIGNAL 0N CIEJEIEICIEIEIDEIEI NORMAL
EIEJEIEIIIEJCIEIE]
ON DUEJCIIEIEIEIEJU (6OHZI
DEIIIIIIEIEIUCI
ON DEIIIIEIUICIEIEIE] DRIVING
EIEIDEIEIDEIEIEICI
0N DEIEJIIIDEIIEJEII
EIEIEIEIEIIIIDCIEIEI
ON EIEJEIEIEIEIEIIDI
EIEJUEJEIEIEIEIDEI
ON DUEJEIUEJUEIII
U0 DEIEIIIIEIEIEIEIEICI
F I G.
ON EICIEIEIEIEIIIII
ITA
/
OFF
0N
OFF
OFF
F | G
ICIEIEIEIIEIEIDEIEI
EIIIIEIEIIIIEIIIIEJDEI
EIEIIEIEIIEIEIEIEI
EIEIEIIEIIDEIEIEI
{7 B< 0N EIIIIIIIEIIDEIEIUEI
‘
OFF IIIIIIIIIIIIIIIIIIIEI
PRIOR ART
OFF EIIIIEIEJEIEIEJIIIEIEI
ON DEICIEIUEIEIIEJI
oFF EIEIIUEIEIEIIIICIIIIEI
\ OFF EIIIIEIEIEJEIUEIEIEI
/
IA
18
IEIEIIIIEIEJCICIEIE]
DIEIEIEICJEIEIDEI
EIEIICICIICIEIEIEI
DEJIIIEJEIEIEIIIIUEI
DEIEIEIEIEIEIEIEJEI
EIDEIEIDEIEIEICIEI
IIIEIDIEIIEIEIDEI
EIEIEIEIIIEIEJCIE]
EIEIEIEIEIEIEIDEIEJ
IIJIIIEICIIEIEIIIIEIIII
< EII'JIIIIEIEIEIEI @
mamas-[113cm
EIEIIIIIIIEICIEIEIUCI
EIEJDEIEIDIEICII
UCIIIIIZIEIEIEICIEJEI
DEIEJCIEICIEIEICIEI
EIEIEICIEIUUEIIIIEI
EIIIIEIIIIEJEIEIIEII
EIEIEIEIEIEIEIEIII
DEIEJEIIIIEIIIII
\
F I 6.
I7 C
3=I
INTERLACE
DRIVING
U.S. Patent
Dec. 1, 1998
5,844,535
Sheet 18 0f 27
211
S
INPUT IMAGE SIGNAL
Q
S‘
2I4
2I2
S
( VA {-1
Row mm
216
33
COUNTER
CIRCUIT
W
SIGNAL
GENERATING
CIRCUIT
2&0
52Ll
I
m
z
3|:
‘
ADDRESS
SIGNAL LINE DRIvER
I
ma
0:
Row ADDRESS
SIGNAL
AI
Q6
00
22
PANEL
;
3;
ED
—I_>
PIXEL BLOCK
QPGDNFES
GENERATING
PIxEL BLOCK
ADDRESS SIGNAL
A2
cIRcuIT
BA
*1
PIXEL BLOCK ADDRESS
[LINE DRIVING CIRCUIT
2B
227
84
PIXEL BLOCK
COUNTER
CIRCUIT
S
2I5
F l G.
{9A