Analytical model for TDDB-based performance
degradation in combinational logic
Mihir Choudhury† Vikas Chandra‡ Kartik Mohanram† Robert Aitken‡
†
Department of Electrical and Computer Engineering, Rice University, Houston
‡
ARM R&D, San Jose
†
Email: {mihir,kmram}@rice.edu ‡ {vikas.chandra,rob.aitken}@arm.com
Abstract
With aggressive gate oxide scaling, latent defects in the gate oxide
manifest as traps that, in time, lead to gate oxide breakdown. Progressive gate oxide breakdown, also referred to as time-dependent
dielectric breakdown (TDDB), is emerging as one of the most important sources of performance degradation in nanoscale CMOS
devices. This paper describes an accurate analytical model to predict the delay of combinational logic gates subject to TDDB. The
analytical model can be seamlessly integrated into a static timing
analysis tool to analyze TDDB effects in large combinational logic
circuits across a range of supply voltages and severity of oxide
breakdown. Simulation results for an early version of an industrial 32 nm library show that the model is accurate to within 3% of
SPICE with orders of magnitude improvement in runtime.
1. Introduction
Progressive time-dependent dielectric breakdown (TDDB), commonly termed gate oxide breakdown, is emerging as one of the
most important sources of temporal degradation in CMOS devices
with technology scaling [1]. The gate oxide thickness of CMOS
devices has decreased steadily with technology scaling, and oxide
thicknesses of less than 2 nm are common in state-of-the-art technologies. In addition to thin gate oxides, the saturating trend in
supply voltage scaling results in a large electric field in the gate oxide, which eventually forms traps in the oxide leading to tunneling
currents. In time, the tunneling currents further degrade the oxide, leading to the formation of more traps. Once enough traps are
formed, they start affecting the electrical properties of the device in
the condition known as soft oxide breakdown.
Studies have revealed that the rate of trap formation increases as
the permittivity of the dielectric increases [2]. With the introduction of high-κ gate dielectrics in the 45 nm technology node [3], the
probability of having a soft oxide breakdown during the device lifetime has increased substantially. Although soft oxide breakdown
does not cause a drastic functional failure, it changes the electrical
properties such as energy, delay, and noise margin of a gate [4–7].
Most of the research in literature has focused on studying the characteristics of SRAM cells in the presence of a soft breakdown. This
is because SRAM cells have minimum width transistors that are
more susceptible to delay and noise margin variations. The effect
of a soft breakdown on SRAM static noise margin and functionality
has been discussed in [6]. In [7], the authors describe the impact of
soft oxide breakdown on the energy/delay drift in SRAMs. The impact of a soft breakdown on circuit functionality for simple circuits
has been investigated in [8].
This research was supported in part by NSF grant CCF-0917226.
.
As technology scales, the impact of soft breakdown on combinational logic cells will become important as well, especially with
the use of high-κ gate dielectrics. With clock frequencies in the
multi-GHz range, it is imperative to be able to predict the delay
of combinational logic paths in the presence of soft breakdown to
avoid over-design and pessimistic margins. Unlike memory elements, SPICE-based simulation of soft breakdown effects in large
combinational circuits is computationally demanding. The complexity arises due to the fact that the impact on delay is a function
of the level of soft breakdown as well as the supply voltage. Hence,
it is necessary to develop analytical models that can accurately predict the delay of combinational logic gates in the presence of soft
breakdown.
This paper proposes an accurate analytical model to predict the
delay of a combinational logic gate across a range of supply voltage and soft breakdown levels. Although the analytical model is
derived for a soft breakdown in an nMOS transistor, the model can
accurately predict the delay of a gate due to a soft breakdown in the
pMOS transistor as well. A soft breakdown affects the propagation
delay of the defective gate as well as the propagation delay of gates
in the fanout cone of the defective gate. This makes timing analysis
of combinational circuits with soft breakdown defects challenging.
The proposed analytical model addresses these issues by dividing the impact of a soft breakdown into two components: (i) degradation in the propagation delay of the defective gate and (ii) degradation in the transition time at the output of the defective gate.
The degradation in the propagation delay and transition time at the
output of the defective gate are a consequence of reduced voltage
swing at the input of the defective gate due to the soft breakdown.
We develop an accurate model for predicting the reduced voltage
swing and build on this model to predict the propagation delay and
transition time of the defective gate. The degradation in the transition time at the output of the defective gate captures the effect of
the soft breakdown on the gates in the fanout cone of the defective
gate. Thus, our analytical model can be seamlessly integrated into
a static timing analysis tool. Results indicate that the maximum
error in the delay predicted by the analytical model compared with
SPICE is less than 3% over a large range of oxide breakdown defect
and supply voltage values. For random oxide breakdown defects at
gates in a combinational logic path, the analytical model predicts
the delay with a maximum error of 0.8% as compared to the results
obtained using SPICE simulations.
This paper is organized as follows. Section 2 describes oxide
breakdown and its modeling. Section 3 presents the derivation of
the proposed analytical model. Section 4 presents the performance
degradation model. Section 5 presents results for static timing analysis of combinational circuits with TDDB defects based on the proposed analytical model. Section 6 is a conclusion.
2. Background
For older technology nodes, the hard oxide breakdown scenario
has been analyzed in detail for failure analysis. The gate oxide
breakdown at the end of device lifetime was abrupt and hence understanding the impact of hard breakdown was important. However, current generation devices are prone to time-dependent dielectric breakdown (TDDB), also known as soft oxide breakdown,
during their lifetime. A soft oxide breakdown begins when the
traps begin to form in the gate oxide. At first, the traps are nonoverlapping and thus do not conduct. As more traps are formed,
they start to overlap and this may result in a resistive conduction
path from gate to channel. Once the conduction channel is formed,
more traps appear due to thermal damage. These new traps cause
the conduction channel to become wider and hence more current
flows leading to even higher temperature. This thermal runaway
condition leads to a catastrophic failure known as hard oxide breakdown (HBD).
Fig. 1 shows the three phases of gate oxide wearout [7]. The
traps start to form at the end of the first phase, known as the time to
soft breakdown. During the second phase (SBD phase), the traps
move around and the leakage current fluctuates randomly. In this
phase, the device is still functional but drifts in energy and delay.
Once the conduction path is formed in the oxide, the device enters the third phase (HBD phase). In the HBD phase, the leakage
current is exponentially higher and the fault is termed catastrophic.
The transition from the beginning of soft oxide breakdown to hard
breakdown is not abrupt, and the gate leakage current starts to progressively increase long before hard breakdown occurs.
leakagepath
path
current
Leakage
current
Hard BD
Hard
BD
I
d
d
II
time to
creation
=
time to
TimeBD
to
soft
wear out
time
=
digital breakdown
phase
Wearout
soft BD
time
s
s
Ig = K V
p
RBD (V)
Figure 2: Power-law gate oxide breakdown model for an nMOS
transistor [9, 10]
2.1
TDDB model
A linear Ohmic oxide breakdown resistance is not sufficient to
model the experimental data, since the Ohmic model only provides
good results for hard breakdown. In this paper, we have used the
voltage-dependent power-law gate oxide degradation model [9,10],
as shown in Fig. 2. In this model, once the gate oxide degrades,
the increase in gate leakage is modeled as a voltage-dependent
current source between the gate and the source or drain depending on the location of the breakdown. It has been shown that the
power-law leakage current model predicts progressive oxide breakdown behavior more accurately leading up to the final hard breakdown [4, 5]. As shown in Fig. 2, the power-law leakage current
model can be converted to a voltage-dependent resistance model
(Eqn. 1). The exponent p refers to the level of oxide degradation
and K reflects the “size” of the breakdown spot.
RBD (V ) =
=
III
Catastrophic
catastrophic
failure
failure
0
Time
time
g
g
Soft
BD
Soft
SoftBD
BD
Figure 1:Wearout and breakdown model for thin gate oxides [7]
For technology scaling in sub-45nm region, higher electric field
in gate oxides due to lack of supply voltage scaling increases the
likelihood of soft oxide breakdown during the lifetime of a chip.
Further, studies indicate that high-κ gate dielectrics, introduced in
the 45 nm technology node, are more susceptible to trap formation,
and hence to soft oxide breakdown [2]. Hence, it is crucial to model
the impact of a soft breakdown on circuit characteristics such energy and delay to avoid pessimistic margins during design.
For combinational logic circuits, a soft breakdown in a transistor of a gate can impact the delay of combinational paths containing the gate. The complexity in characterizing the impact of soft
breakdown arises because soft breakdown at various devices can
occur at different times during the lifetime and progressively become worse until a hard breakdown occurs. Hence, models for soft
oxide breakdown play a vital role in bridging the gap between the
impact of a soft breakdown on a device and its impact on the circuit.
Section 2.1 describes the various soft oxide breakdown models proposed in literature.
V
K ·Vp
1
· V (1−p)
K
(1)
The exact values of K and p are difficult to predict a priori
for a new technology node since device post-breakdown behavior
is extremely complicated. Device characteristics after gate oxide
breakdown rely on many parameters including breakdown location, transistor type, voltage polarity, device operation mode, oxide
area, and even the type of poly-gate doping. In this work, we do
not explicitly change K and p in our model but consider a range
of breakdown resistances to account for the level of oxide degradation. Based on our simulations and published data, the resistance range we consider is from GΩ (fresh oxide) to a few KΩ
(hard breakdown) [4, 11]. With time, the oxide degradation level
increases, which can be captured by increasing K and p. In our
time-dependent resistance model, the increase in K and p is modeled as a reduction in the resistance based on Eqn. 1.
A gate-to-diffusion (source or drain) breakdown represents the
worst-case scenario for a SBD [12]. Breakdown to the channel can
be modeled as a superposition of gate-to-drain and gate-to-source
breakdowns. Since the probability of having more than one breakdown in an nMOS transistor is low [13], we consider only gate-tosource breakdown in this paper. The time-dependent gate-to-source
resistance model has also been experimentally verified [11]. It has
been shown in [5, 8] that the time to oxide breakdown in pMOS
is an order of magnitude higher than in nMOS. Hence, the performance degradation models presented in this work consider a soft
breakdown in nMOS even though the models also hold for a soft
breakdown in pMOS.
The impact of a soft breakdown at a gate in a combinational path
mainly impacts the propagation delay of the defective gate. However, there is also a modest impact on the propagation delay of gates
in the fanout cone of the defective gate that cannot be neglected.
Sec. 3 describes how our analytical model is able to capture these
effects for easy integration into a static timing analysis tool.
9
2
SBD gate
Propagation delay
Transition time
6
Driver
Propagation delay
Transition time
3
4
10
10
1.8
1.6
Driver
Propagation delay
Transition time
1.2
1
10
Breakdown resistance (RBD) (in ȍ)
4
5
10
Breakdown resistance (RBD) (in ȍ)
VDD = 1.2 V
1.4
SBD gate
Propagation delay
Transition time
1.4
5
(b)
Normalized value
VDD = 1.0 V
(a)
Normalized value
Normalized value
VDD = 0.8 V
1.3
(c)
SBD gate
Propagation delay
Transition time
Driver
Propagation delay
Transition time
1.2
1.1
1
4
10
10
5
Breakdown resistance (RBD) (in ȍ)
Figure 4: Impact of a soft breakdown on the propagation delay and transition time of the driver and SBD gate.
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Figure 3: (a) Impact of soft breakdown on the delay of a combinational path and (b) Normalized VBD vs. RBD for VDD = 0.8,
1.0 and 1.2 V.
3. Proposed analytical model
Consider an inverter chain g1 , g2 , ..., gn shown in Fig. 3(a) in
which one of the inverters, say gk , has a soft breakdown. In our
naming convention, gk refers to the kth inverter in the chain and
node gk refers to the output of inverter gk . Inverter gk will also
be referred to as the soft breakdown (SBD) gate and inverter gk−1
as the driver. A soft breakdown in gk is modeled using a timedependent resistor between the gate and source terminals of the
nMOS transistor of gk . We will refer to this resistance as the breakdown resistance (RBD ). The impact of a soft breakdown on the
delay of a combinational logic gate is derived analytically based
on the time-dependent resistor model and validated against SPICE
simulations for an early version of an industrial 32 nm library.
Consider a rising transition at node gk−1 . As node gk−1 charges
through the pMOS transistor of gate gk−1 , the breakdown resistor
on the nMOS transistor of gk draws current and reduces the effective strength of the pMOS transistor of the driver. The reduced
effective drive strength of the pMOS transistor of the driver affects
the delay of all combinational paths containing the driver. Thus,
the impact of a soft breakdown on the delay of a combinational
logic path depends on the driver as well as the SBD gate. Static
timing analysis in the presence of TDDB defects could potentially
become intractable since all combinations of driver and SBD gate
in the technology library have to be characterized for a range of
breakdown resistance and supply voltage values.
Our analytical model addresses this issue by decoupling the effect of a soft breakdown on the driver and the SBD gate. First, the
breakdown resistor affects the DC voltage, referred to as the breakdown voltage, VBD , of the driver. In the steady state, the breakdown
resistor has a voltage divider effect that restricts node gk−1 from
reaching the supply voltage VDD . Fig. 3(b) shows the normalized
VBD as a function of the breakdown resistance RBD for VDD = 0.8,
1.0, and 1.2 V. Second, the reduced voltage swing impacts the propagation delay and transition time of the SBD gate. The increase in
transition time of the SBD gate captures the affect of the soft break-
down defect on the propagation delay of gates in the fanout cone of
the SBD gate. Thus, the delay impact of a soft breakdown is decoupled as (i) reduced DC voltage swing of node gk−1 that depends on
the driver gate and (ii) increase in propagation delay and transition
time of the SBD gate resulting from the reduced gate-source voltage at its input. The solid curves in Fig. 4(a), (b), and (c) show the
increase in transition time and propagation delay of the SBD gate
for VDD = 0.8, 1, and 1.2 V. The soft breakdown defect also has a
loading effect that increases the propagation delay and transition
time of the driver. The dotted curves in Fig. 4(a), (b), and (c) show
the increase in transition time and propagation delay of the driver
VDD = 0.8, 1, and 1.2 V. Although a soft breakdown has a loading
effect on the driver, there is no experimental work in literature that
verifies that the effect of this loading is accurately captured by the
same resistor model. Hence, we only consider the increase in the
propagation delay and transition time of the SBD gate in this paper.
3.1
Voltage-divider VBD model
For a rising transition at the output of gk−1 , the breakdown resistor has a voltage divider effect that reduces the breakdown voltage,
VBD , of gk−1 . In the steady state, the pMOS transistor of gk−1 is
in the linear region, and it is possible to compute the VBD of gk−1
using a simple voltage divider expression as follows:
VBD = VDD RBD /(Rgate + RBD )
(2)
where Rgate is the resistance of the pMOS transistor of the driver.
Fig. 5(a) compares VBD predicted by the simple voltage dividerbased expression with SPICE for different values of the breakdown
resistor and supply voltage VDD . The value of resistance Rgate at
each supply voltage point was obtained using a mean-squared error
fit over a range of breakdown resistance values.
For large values of the breakdown resistor (≥ 100KΩ), VBD of
gk−1 is close to VDD (greater than 0.95VDD ) and in the steady-state,
the VDS for the pMOS transistor of inverter gk−1 is close to zero.
Hence, in the steady state, the pMOS transistor of inverter gk−1 is
in the deep linear region (VDS VGS − VT ). For this case, the
driving pMOS transistor of gk−1 can be modeled by a simple resistor and the voltage divider-based expression for VBD is accurate.
However, as the breakdown resistance decreases, the difference between the VBD of gk−1 and VDD increases, and hence, the VDS of the
pMOS transistor of inverter gk−1 increases. With increasing VDS ,
the non-linearity in the drain current of the pMOS transistor increases, and the pMOS transistor of inverter gk−1 cannot be treated
as a resistor. This effect is more prominent with decreasing VDD , as
illustrated in Fig. 7. Thus, modeling the pMOS transistor of gk−1
with a resistor the non-linearity in the drain current can also be seen
in Fig. 5(a) as the error of the voltage divider expression increases
as VDD decreases.
0.95
VDD = 1.2 V
0.9
0.85
VDD = 1 V
0.8
Traditional
voltage-divider
model
0.75
VDD = 0.8 V
0.7
o oo
(a)
0.65
10
SPICE
Model
4
10
1
VDD = 1.2 V
0.95
0.9
0.85
Proposed
model
VDD = 1 V
0.8
0.75
VDD = 0.8 V
0.7
o oo
(b)
0.65
5
Normalized VBD (VBD/VDD)
Normalized VBD (VBD/VDD)
Normalized VBD (VBD/VDD)
1
10
Breakdown resistance (RBD) (in ȍ)
SPICE
Model
4
10
1
VDD = 1.2 V
0.95
0.9
0.8
0.75
VDD = 0.8 V
0.7
o oo
(c)
0.65
5
Proposed
compact model
VDD = 1 V
0.85
SPICE
Model
4
5
10
10
Breakdown resistance (RBD) (in ȍ)
Breakdown resistance (RBD) (in ȍ)
3.2 Proposed VBD model
In order to address the inaccuracies in the voltage-divider VBD
model, we derive a model for VBD based on the n-power law model
for the drain current IDS in the linear region given by [14]:
»
–
W (VGS − VT )n (1 + λVDS )VDS
VDS
IDS = B
2−
(3)
Leff VD,sat
VD,sat
where VD,sat = K(VGS − VT )m , W is the channel width, Leff is
the effective channel length, λ is the channel length modulation
parameter, VGS is the gate-source voltage, VDS is the drain-source
voltage, VT is the threshold voltage, K and m control the linear
region characteristics, and B and n control the saturation region
characteristics. Alternatively, by separating the VGS and VDS terms,
the drain current can be expressed as:
IDS = B
W (VGS − VT )n
(1 + λVDS )×
Leff K 2 (VGS − VT )2m
m
(2K(VGS − VT )
= KG (1 + λVDS )(Vgate VDS −
− VDS )VDS
2
VDS
)
(4)
where KG = (BW (VGS − VT ) )/(Leff K (VGS − VT ) ) and
Vgate = 2K(VGS − VT )m depends on the gate voltage. The expression for IDS shown in Eqn. 4 is a cubic expression in the drainsource voltage VDS . We simplify the expression to a quadratic expression in VDS by neglecting λVDS for small values of VDS as this
would allow us to obtain a closed-form expression for the breakdown voltage VBD . Hence, the drain current IDS is given by:
n
2
2m
2
)
IDS = KG (Vgate VDS − VDS
VDD − VDS
2
= KG (Vgate VDS − VDS
)
RBD
that can be rearranged as
+ 1/RBD )VDS + VDD /RBD = 0
1
o oo
0.8
SPICE
Model
VDD = 0.8 V
VDD = 1.2 V
0.6
VDD = 1 V
0.4
0.2
0
0
0.05
0.1
0.15
0.2
0.25
0.3
|VDS| (in V)
Figure 7: Model validation for drain current of a pMOS transistor in the linear region (Eqn. 5).
where VDS is the source-drain voltage across the pMOS transistor of
gk−1 . Note that VDD − VDS is equal to the breakdown voltage VBD .
Since Eqn. 6 is a quadratic equation in VDS , the two solutions of
this quadratic equation are:
1 h
(KG Vgate + 1/RBD )±
VDS =
2KG
`
´1/2 i
(KG Vgate + 1/RBD )2 − 4KG VDD /RBD
1 h
=
(KG Vgate + 1/RBD )±
2KG
` 2 2
´1/2 i
2
KG Vgate + 1/RBD
+ (2KG Vgate − 4KG VDD )/RBD
(5)
Fig. 7 validates Eqn. 5 against SPICE for a pMOS transistor in
the linear region. The gate voltage to the pMOS transistor is fixed
at 0 V and the source terminal is fixed at VDD . The x-axis plots
VDS from 0–0.3 V, since this is the range of VDS of interest for a
soft breakdown for VDD from 0.8–1.2 V. The value of Vgate varies
between 0.5 V and 1 V as VDD goes from 0.8 V to 1.2 V.
Using the model for the drain current in the linear region from
Eqn. 5, an expression for VBD can be derived when the nMOS transistor of inverter gk is subject to soft breakdown with a breakdown
resistance RBD . In the steady state, by Kirchhoff’s current law, the
drain current through the pMOS transistor of gk−1 must equal the
current through the breakdown resistance:
2
−(KG Vgate
KG VDS
Normalized pMOS drain current
Figure 5: Comparison of VBD (a) voltage-divider model (Eqn. 2), (b) proposed model (Eqn. 8), and (c) proposed compact model
(Eqn. 9) against SPICE.
(6)
By completing squares by adding and subtracting 4KG Vgate /RBD
under the square-root, we obtain
`
1 h
2
2
(KG Vgate + 1/RBD ) ± KG2 Vgate
VDS =
+ 1/RBD
2KG
i
−2KG Vgate /RBD − 4KG (VDD − Vgate )/RBD )1/2
1 h
=
(KG Vgate + 1/RBD )±
2KG
`
´1/2 i
(KG Vgate − 1/RBD )2 − 4KG (VDD − Vgate )/RBD
1 h
(KG Vgate + 1/RBD )±
=
2KG
s
4KG (VDD − Vgate )/RBD i
(KG Vgate − 1/RBD ) 1 −
(7)
(KG Vgate − 1/RBD )2
When RBD → ∞, the term under the square-root tends to 1. As
RBD → ∞, there is no soft breakdown defect, and thus, we require
VBD → VDD and VDS = VDD −VBD → 0. Thus, to make VDS → 0 as
4
3.5
SPICE
Model
VDD = 0.8 V
3
VDD = 1 V
2.5
VDD = 1.2 V
2
1.5
1
10
4
5
5
9
(b)
4.5
o oo
4
3.5
SPICE
Model
VDD = 0.8 V
3
VDD = 1 V
2.5
VDD = 1.2 V
2
1.5
1
4
5
10
10
10
(c)
8
7
SPICE
Model
6
VDD = 0.8 V
5
VDD = 1 V
4
VDD = 1.2 V
3
2
1
10
10
Breakdown resistance (RBD) (in ȍ)
Breakdown resistance (RBD) (in ȍ)
o oo
Normalized transition time
o oo
Normalized transition time
(a)
Normalized propagation delay
Normalized propagation delay
5
4.5
4
(d)
8
6
o oo
SPICE
Model
VDD = 0.8 V
VDD = 1 V
4
VDD = 1.2 V
2
4
5
10
10
Breakdown resistance (RBD) (in ȍ)
5
10
Breakdown resistance (RBD) (in ȍ)
Figure 6: Model validation for propagation delay of (a) an inverter, (b) a two-input NOR gate and transition time of (c) an inverter
and (d) a two-input NOR gate.
RBD → ∞, we must choose the negative solution of the quadratic
equation. Hence, VDS and VBD are given by:
VDS
VBD
1 h
(KG Vgate + 1/RBD ) − (KG Vgate − 1/RBD )
=
2KG
s
4KG (VDD − Vgate )/RBD i
1−
(KG Vgate − 1/RBD )2
h
1
(KG Vgate + 1/RBD )−
= VDD −
2KG
s
4KG (VDD − Vgate )/RBD i
(KG Vgate − 1/RBD ) 1 −
(KG Vgate − 1/RBD )2
VBD given by the following expression:
(KG Vgate + 1/RBD ) − (KG Vgate − 1/RBD )
2KG
= VDD − 1/KG RBD = VDD (1 − RG /RBD )
(9)
VBD = VDD −
where RG = 1/(KG VDD ). Fig. 5(c) compares VBD obtained using
the compact model with the results from SPICE. The maximum
error in the compact model over the range of breakdown resistance,
for VDD ranging from 0.8 V to 1.2 V, is 1.5%.
(8)
Eqn. 8 is the analytical expression for VBD of inverter gk−1 . Fig. 5(b)
compares VBD obtained using Eqn. 8 with SPICE. The maximum
error in the model over the entire range of breakdown resistance
(until hard breakdown), for VDD ranging from 0.8–1.2 V, is 0.3%.
4.
Performance degradation model
The reduced voltage swing at the input of the SBD gate results
in an increase in the propagation delay and transition time at the
SBD gate. The model for the propagation delay and transition time
subject to soft breakdown can be obtained using the α-power law
model [15] for the delay of a combinational logic gate:
Δ∝
VDD
(VGS − VT )α
1
0.8
where VGS is the gate-source voltage, VT is the threshold voltage,
and α is the carrier velocity saturation index. By substituting the
gate-source voltage of the SBD gate by the breakdown voltage VBD
(Eqn. 8), analytical models for the propagation delay (Δprop, SBD )
and transition time (Δtran, SBD ) of combinational logic gates subject
to soft breakdown can be obtained as follows:
VDD = 1.2 V
VDD = 1.0 V
VDD = 0.8 V
Ș
0.6
0.4
0.2
0
Δprop, SBD ∝
4
10
10
Figure 8: η as a function of breakdown resistance at various
supply voltage points.
Compact model: Eqn. 8 can be simplified into a compact model
without significantly compromising
accuracy. Denote the term unq
−V
(10)
5
Breakdown resistance (RBD) (in ȍ)
4K (V
VDD
1
, Δtran, SBD ∝
(VBD − VT )α1
(VBD − VT )α2
)/R
gate
BD
in Eqn. 8 by η.
der the square-root term, 1 − (KG VDD
2
G gate −1/RBD )
Fig. 8 plots the value of η as a function of the breakdown resistance
for VDD = 0.8, 1, and 1.2 V. For VDD = 1 V, η has a constant value
of 1. For values of VDD away from 1 V, η is equal to 1 when RBD
is high. As RBD decreases, η reduces to 0.9 and 0.6 for VDD = 1.2
V and 0.8 V, respectively. However, as RBD decreases, 1/RBD →
KG Vgate . Hence, (KG Vgate − 1/RBD )η (KG Vgate + 1/RBD ).
The maximum error introduced in the model by approximating η
by a constant 1 is 5% as VDD increases from 1 V to 1.2 V and 8%
as VDD decreases from 1 V to 0.8 V. Since, KG is also a function of
VDD , the error introduced in the model by this approximation can
be absorbed into the expression for KG as a function of VDD . By
approximating η by a constant 1, we obtain a compact model for
where the velocity saturation indices, α1 and α2 , tend to 1 as velocity saturation increases. We found that α1 and α2 decrease linearly
with supply voltage VDD since velocity saturation becomes more
severe as voltage increases. The model for the propagation delay
and transition time in the presence of soft breakdown can be applied to complex combinational logic gates such as 2-input nand
and nor gates. Consider a gate g subject to a soft breakdown in an
nMOS transistor. Denote p as the input corresponding to the nMOS
transistor with the soft breakdown defect. Denote the output of g
as y. The soft breakdown will increase the propagation delay for a
rising transition at p. For all input combinations of g that sensitize
a rising transition at p, the propagation delay and transition time
are computed using Eqn. 10. Figs. 6(a) and (b) compare the propagation delay obtained using Eqn. 10 against SPICE simulations for
a soft breakdown defect in an inverter and a two-input nor gate,
respectively. Similarly, Figs. 6(c) and (d) compare the transition
time at the output obtained using Eqn. 10 against SPICE simulations for an inverter and a two-input nor gate, respectively. The
maximum error for the propagation delay over a range of breakdown resistance and supply voltage values is 3% in comparison to
SPICE simulations.
o oo
1.3
SPICE
Model
1.2
1.1
1
0
20
40
60
80
100
(b)
1.1
o oo
VDD = 1 V
Normalized propagation delay
VDD = 0.8 V
(a)
Normalized propagation delay
Normalized propagation delay
1.4
SPICE
Model
1.08
1.06
1.04
1.02
1
0
20
Random TDDB defect insertion run
40
60
80
100
Random TDDB defect insertion run
1.07
1.06
(c)
VDD = 1.2 V.
1.05
o oo
SPICE
Model
1.04
1.03
1.02
1.01
1
0
20
40
60
80
100
Random TDDB defect insertion run
Figure 9: STA flow validation for the propagation delay of an inverter chain of length 20 with 100 runs of random soft breakdown
defects at 4 inverters in the chain.
5. STA with TDDB defects
Normalized propagation delay
The analytical model for performance degradation of combinational logic gates subject to TDDB can be integrated into static timing analysis (STA) as follows. Each gate in a technology library is
characterized as a driver and as an SBD gate. The drive strength
of the pMOS transistors in the pull-up network of the driver gate
determine the breakdown voltage VBD for different inputs to the
driver gate. Hence, characterization of the driver gate is done using
either Eqn. 8 or Eqn. 9 on its inputs. The decrease in VBD results
in an increase in the propagation delay and transition time of the
SBD gate. Hence, the SBD gate is characterized using Eqn. 10 as a
function of the breakdown voltage, VBD . With the characterization
of each gate as a driver and as an SBD gate, the propagation delay
of a combinational path with TDDB defects can be computed in
a single topological pass during STA. At each node with a TDDB
defect, the breakdown voltage is computed for the driver gate and
this voltage is used to compute the propagation delay and transition
time for the SBD gate.
2.5
o oo
VDD = 0.8 V
SPICE
Model
2
1.5
VDD = 1.2 V
1
0
5
10
VDD = 1 V
15
20
Percentage of SBD gates
Figure 10: Propagation delay of an inverter chain as a function
of percentage of gates on the chain subject to soft breakdown.
The STA flow for TDDB is validated for an inverter chain with
soft breakdown at multiple inverters. Fig. 10 shows the normalized propagation delay of the inverter chain as function of the percentage of inverters in the chain with a soft breakdown defect at
VDD = 0.8, 1.0, and 1.2 V. The breakdown resistance for each soft
breakdown defect is 4 KΩ. As expected, the propagation delay increases linearly with the defect percentage. The maximum error in
the propagation delay of the inverter chain is 3% as compared to
SPICE simulations for VDD = 0.8, 1.0, and 1.2 V.
In practice, different gates in a combinational logic path will experience different severity in soft breakdown. Fig. 9 shows a scenario where 4 inverters in a 20 inverter chain are subject to random
soft breakdown defects with breakdown resistance ranging from 4–
50 KΩ. The maximum error in the propagation delay of the inverter
chain estimated using our analytical model is less than 1% as compared to SPICE simulations for VDD = 0.8, 1.0, and 1.2 V.
6.
Conclusions
This paper presented an accurate analytical model for the propagation delay and transition time of combinational logic gates subject to time-dependent dielectric breakdown (TDDB). The model
for propagation delay and transition time were validated against
SPICE simulations for an early version of an industrial 32 nm technology library. The accuracy was also validated by integrating the
analytical model into a static timing analysis tool to predict the
propagation delay of combinational logic paths subject to multiple
random TDDB defects.
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