Module Introduction
Purpose
• The intent of this module is to provide you with an overview of i.MX31
system connectivity.
Objectives
• Describe the role of the USB module, the eDMA, and AUDMUX in
i.MX31 connectivity.
• Describe the role of the display port and sensor port for enabling
i.MX31 connectivity.
• Describe the roles of the ATA interface and the SIM.
Content
• 19 pages
• 3 questions
Learning Time
• 40 minutes
The intent of this module is to provide you with an overview of i.MX31 system
connectivity. You will learn the roles of various components used in connecting the
i.MX31 to various devices. It should be noted that, unless specifically mentioned, all
information in this module applies to both the i.MX31 and the i.MX31L.
1
i.MX31 Registers
i.MX21
i.MX31
$Base_Addr1
$Base_Addr2
$ADDR0
REGISTER A
$ADDR1
REGISTER B
$ADDR2
REGISTER C
$ADDR3
REGISTER D
$ADDR4
REGISTER C
REGISTER B
REGISTER D
$ADDR5
REGISTER A
Let’s begin by looking at the i.MX21 and i.MX31 registers. On modules
carried over from the i.MX21 to the i.MX31, the registers typically do not
have the same address on both devices. In fact, the i.MX21 has a different
register base from the i.MX31.
Register addresses are in different locations in memory in the i.MX31. Any
applications written on i.MX21 will have to be ported to the i.MX31 memory
map. These addresses are not covered in this module, but are detailed in the
i.MX31 Reference Manual.
2
BGA Package
Attribute
i.MX21
i.MX31
Ball Count
289
457
Pitch
0.65 mm
0.5 mm
Package Height
1.41 mm
1.2 mm
Printed circuit board area
is the same: 14 x 14 mm
Now, let’s look at the Ball Grid Array (BGA) package. There are three major
differences in the BGA package used in the i.MX31.
First, the number of connections has increased to 457.
Second, the ball pitch is reduced to 0.5 mm.
Third, the physical size of the i.MX31 is 14x14 mm. However, the package
height has decreased from 1.41 mm for the i.MX21 to 1.2 mm for the
i.MX31.
3
High Speed USB 2.0
USB Block Diagram
Also included in the i.MX31 is a USB module. The USB module provides high performance USB On-TheGo (OTG) functionality. This is compliant with the USB 2.0 specification and is capable of connecting to a
USB host or client device. The USB module consists of three independent USB cores, each controlling
one USB port. One high speed, or 480 Mbits per second, USB OTG interface allows devices to be
connected and can automatically toggle between Host/Device modes. The other two USB cores include
one high speed host port and one full speed, or 12 Mbits per second, host port.
The high speed OTG core includes a high speed ULPI 1.0 compliant interface, configurable software for
a ULPI or serial transceiver interface, high speed operation with a ULPI transceiver, and full speed and
low speed operations in Host mode. Also included is high speed operation with a ULPI transceiver and
full speed operation in Peripheral mode. The OTG core contains hardware support for OTG signaling,
Session Request Protocol, and Host Negotiation Protocol. There are also up to eight bidirectional endpoints.
The Full Speed/Low Speed (FS/LS) Host Only core includes Transceiver-less Link Logic (TLL) for on board
connection to a FS/LS USB peripheral. It also has a Bypass mode to route host port 1 signals to the OTG
I/O port. Bypass mode is useful when i.MX31 cooperates with a second host, typically a cellular BB IC.
The 2nd host is then able to gain control over the USB transceiver that is normally controlled by the i.MX31.
The High Speed/Full Speed/Low Speed Host Only core includes a high speed ULPI 1.0 compliant
interface, a FS/LS interface for Serial transceiver, and a TLL function for direct connection to USB
peripheral in FS/LS (serial) operation.
TMAX includes an embedded DMA controller and AHB master connectivity to the crossbar switch.
Both are essential for internal support of the high speed data rate.
4
eDMA
The Enhanced Direct Memory Access (eDMA) controller represents a RISC
core that maximizes the system’s performance. This is done by relieving the
ARM core of the bulk transfer of data from memory to memory or between
memory and on-chip peripherals. The advantage of the eDMA controller is
its dynamic routing capability and its ability to perform numerous tasks
simultaneously based on the DMA channel’s descriptors.
Some features of the eDMA controller include a multi-channel DMA that
supports up to 32 time-division multiplexed DMA channels; memory
accesses including linear, FIFO, and 2D addressing; and very fast contextswitching with 2-level priority based preemptive multi-tasking. The eDMA
also has a 16-bit instruction-set micro RISC engine, one or two controlling
masters (the MCU and possibly the DSP), two DMA units to access the
MCU domain, and an optional DMA unit to access the DSP domain. Other
features include support of byte-swapping and CRC calculations, an
available library of scripts and API, Little-endian and Big-endian modes, and
much more. For more information, please refer to the i.MX31 reference
manual.
5
AUDMUX
AUDMUX
Port 1
(Internal)
SSI2
Port 2
(Internal)
SAP
Port 3
(External)
Port 4
(External)
Voice
Codec
Port 5
(External)
Stereo
DAC
Port 6
(External)
IOMUX
SSI1
Port 7
(External)
Bluetooth
(Optional)
CE Bus
Device
i.MX31
Now, let’s look at the digital audio multiplexer (AUDMUX). The AUDMUX is a digital
multiplexer that supports bi-directional data transfers without the need for host processor
intervention. It offers programmable interconnects for multiple, simultaneous voice, audio,
data routing between two on-chip SSI modules, and external SSI and Serial Audio Port
(SAP) devices. Uses can be found in audio and video CODECs and modems. With the
AUDMUX, resources do not need to be hard-wired and can be effectively shared in different
configurations.
Features of the AUDMUX include two internal ports, five external ports, and independent
Tx/Rx Frame sync and clock direction selection for host or peripheral. AUDMUX also
includes full 6-wire SSI interfaces for asynchronous receive and transmit, configurable 4wire (synchronous) or 6-wire (asynchronous) peripheral interfaces, transmit and receive data
switching to support external network mode, and CE Bus network mode to provide
synchronous switching on RxD.
Seven ports are provided on the AUDMUX. Two of the host ports are internal.
One port is an external host port which can interface to SAP devices for inter-processor
audio transfer.
The remaining four ports are peripheral ports with the flexibility to interface SSI, I2S, or AC97
external devices. Port 7 can be physically connected to any of these peripherals as well as
the CE Bus. The limitation of connecting CE Bus only at port 7 is due to the data selection in
CE bus network mode at ports 1 to 7. Ports 1 to 6 communicate with CE Bus devices by
being configured to connect to Port 7.
6
Question
Is the following statement true or false? Select the correct response,
then click Done.
“The BGA package for the i.MX31 has increased its connections to 457,
reduced the ball pitch to 0.5 mm, and decreased the package height to
1.2 mm.”
True
False
Consider this question concerning the i.MX31 BGA package.
Correct.
There are 3 major differences in the i.MX31 BGA package. The number of
connections is increased to 457 , the ball pitch is reduced to 0.5 mm, and
the package height has decreased from 1.41 mm for the i.MX21 to 1.2 mm
for the i.MX31.
7
i.MX31 Display Port
Supports connection to:
•
•
•
Memory-less LCD displays
Smart LCD displays
TV encoders
Three interface types:
1. Synchronous parallel (18-bit)
•
•
•
Memory-less LCD’s, TV encoders, dual-port smart LCD’s
HYSYNC, VSYNC, pixel clock
1024x1024, 262K colors
2. Asynchronous parallel (18-bit)
•
•
•
•
Smart LCD’s
DMA read/write between system memory and smart LCD
Direct read/write access by ARM11 core to smart LCD
1024x1024, 262K colors
3. Asynchronous serial (SPI)
•
Smart LCD’s
The display port is part of the Image Processing Unit (IPU) on the i.MX31. It allows for connecting to
a variety of display devices, such as memory-less (also known as “dumb”) LCD displays, smart LCD
displays, and TV encoders.
The i.MX31 display port supports three types of interfaces; synchronous parallel, asynchronous
parallel, and asynchronous serial.
The synchronous parallel interface is an 18-bit interface that is used primarily for memory-less
displays, TV encoders and dual-port smart displays. It generates the timing signals, HSYNC,
VSYNC, and pixel clock, and sends the pixel data to the display. The synchronous parallel interface
can support memory-less displays up to 1024x1024 resolution with 262,000 colors, with a maximum
interface speed of 30 MHz.
The second interface type supported by the i.MX31 display port is the asynchronous parallel
interface, an 18-bit interface that is used primarily for smart LCD displays. The interface supports
DMA read and write transfers from system memory to the smart LCD display as well as ARM11 core
direct read/write accesses to the smart LCD display. The asynchronous parallel interface can support
a smart display that is 1024x1024 resolution with 262 thousand colors, with a maximum interface
speed of 100 MHz.
The third interface supported by the i.MX31 display port is an asynchronous serial interface. This
interface is a 3, 4, or 5 wire interface that is primarily used for smaller resolution smart LCD displays
with lower performance requirements.
8
Display Port: Connectivity
Data
Async. Control
TV Encoder
Sync. Control
Data
Screen
Async. Control
Primary Display
Smart, Dual Port
Display Port
Sync. Control
Display Port
TV Encoder
Primary Display
Smart, Dual Port
Serial I/F
Secondary Display
Smart, Parallel I/F
•Data bus: 18 bits
•Sync. I/F controls: VSYNC, HSYNC, DotClk,
Valid
Secondary Display
Smart, Serial I/F
•
•
Async. I/F controls: CS, data/command, read,
write
Serial I/F: CS, RS, Clk. D0
Here is an example of the different connectivity scenarios that are possible
with the i.MX31 display port. The i.MX31 display port allows up to three
simultaneous connections – two displays and a TV encoder. This is a new
feature on the i.MX31 that was not available on previous generations of i.MX
products. This feature is enabled via time-sharing of the bus and interfaces
on the display port.
In both diagrams, you can see the display port is connected to a TV encoder
and two smart displays. The primary display is a dual-port smart display,
meaning that it has both an asynchronous and synchronous parallel
interface. The secondary display is a single-port smart display. The
difference between the two diagrams is the interface that is used for the
secondary display. In the diagram on the left, the secondary display uses the
asynchronous 18-bit parallel interface. In the diagram on the right, the
secondary display uses the asynchronous serial interface.
To see a diagram of the i.MX31 connection to a TV encoder, click “i.MX31
Connection”.
9
Connection To TV-Encoders
i.MX31
TV Encoder
Control interface
I 2C
Serial Control Interface
Port
Data Bus
XTAL
OSC
IPU
V-Sync (Field)
Display Port
H-Sync
Clock
Control
Module
Data Clocks (27MHz)
Ref.Clocks
Data
YUV
Processing,
Sync Insertion,
DACs
Clock Control Module
PLL
•Data bus: 8- or 10-bit YUV 4:2:2 (both interlaced and non-interlaced)
•Synch control: Data Clock – 27 MHz for BT.656 compatible mode; Vsync, Hsync
Reference material for previous page
10
Display Port: New Features
Feature
Number of Displays
Supported
Maximum Screen Size
TFT Support
STN/CSTN Support
TFT Data I/F
Color Support
Alpha Blending
i.MX21
i.MX31
2
Smart LCD + Memory-less LCD or TV
Encoder
3
Smart LCD + Memory-less LCD + TV
Encoder
Dumb – 800 x 600
Smart – 320 x480
1024x1024 (All)
18-bit, RGB666
18-bit, RGB666
Yes
No
18-bit
18-bit
262k colors
262k colors, but internally supports 16M
colors
Supports global alpha
Supports per-pixel alpha
Now, let’s examine the enhancements to the capabilities of the i.MX31
display interface compared to the i.MX21. In the chart shown here, green
indicates an improvement in the i.MX31, yellow indicates the feature is the
same, and red indicates that the feature has been eliminated on the i.MX31.
The main enhancement in the i.MX31 display interface is that it can support
up to three displays that are simultaneously connected to the display port – a
smart display, memory-less display, and a TV encoder. The i.MX31 can now
also support displays up to 1024x1024 resolution. Previous generations of
i.MX could only support up to 800x600 resolution displays. Another new
feature in the i.MX31 display port is the capability to do a per-pixel alpha
blend instead of a global alpha blend. This allows greater control when
blending foreground and background images. In terms of feature elimination,
the i.MX31 is targeting high-tier consumer products and therefore does not
support STN or CSTN displays.
11
Question
Which of the following statements about the i.MX31 display port are
true? Select all that apply and then click Done.
The i.MX31 supports 3 types of display interfaces: synchronous parallel,
asynchronous parallel, and asynchronous serial.
The maximum display resolution supported by the i.MX31 is 800x600
pixels.
The i.MX31 supports per-pixel alpha values for blending images.
The i.MX31 can support dual-port smart displays.
Done
Here is a question to test your understanding of the i.MX31 display ports.
Correct.
The i.MX31 supports synchronous parallel, asynchronous parallel, and
asynchronous serial interfaces. The i.MX31 also supports per-pixel alpha
values and dual-port smart displays. The previous generation i.MX21
supported only 800x600 resolution, but the i.MX31 can display up to
1024x1024 resolution.
12
Sensor Port
i.MX31
Data
Sync. Control
Mode Control
Sensor
Port
Primary Sensor
2
I2C Control I C Port
• Includes image capture of
up to 30 Mpixels per second
• Handles CMOS logic and
control interfaces with data
packing and synchronization
• Supports Flash strobe
generation
Secondary Sensor
Lets move on to the i.MX31 sensor port. The sensor port provides a
connection to either one or two image sensors. Only one sensor can be
active at any given time. The sensor port provides connection to either
CMOS or CDD image sensors using a parallel interface. The interface can
be 12, 10, 8, or 4 bits wide and the data bus rates can be up to 60 MHz.
The Camera Sensor Interface (CSI) consists of the Interface Logic, the Data
Packing Unit and the Sensor Interface Control. The CSI is controlled via the
peripheral bus registers. All programming parameters for the CSI are double
buffered with synchronous change at the frame start.
Some of the features of the CSI include image capture of up to 30 Mpixels
per second with real-time VGA resolution video at 30 fps, 5 Mpixel images at
6 fps, and the capability of handling up to a 16 Mpixel still camera sensor.
The CSI can also handle CMOS logic and control interfaces with data
packing and synchronization, and it supports flash strobe generation.
13
Connection To TV-Decoders
TV Decoder
Serial Control Interface
TV-Receiver
Data
BT.656
Clock Control Module
XTAL
OSC
i.MX31
Control Interface
Data Bus
I2C Port
IPU
Sensor Port
Data Clocks
(27 MHz)
PLL
•Data bus: 18 or 16 bit RGB, 8 or 10 bit YUV 4:2:2 (both interlaced and non-interlaced)
•Synch control: Data Clock – up to 30 MHz, 27 MHz for BT.656 compatible mode; Vsync, Hsync
•Reference clock equal to the Data Clock
In addition to CMOS and CCD image sensors, TV-IN is supported by an
external TV decoder chip and is another target application for the i.MX31.
For TV-IN/OUT, the VSYNC and HSYNC discrete signals are two methods
of digital video frame and line synchronization. For BT.656 protocol, line and
frame borders are marked in code and embedded into the pixel stream, so
there is no need for additional VSYNC and HSYNC support.
14
Sony Memory Stick PRO Interface
• Maximum transfer rate of 19.7 Mbytes per second
• 10 connector pins for each port
• 4-bit bus, 40 MHz clock
i.MX31
Memory
Stick
PRO
The i.MX31 has two ports for connecting with the Sony Memory Stick PRO,
based on the Memory Stick/Memory Stick PRO Host Controller IP
Specifications, V.1.3. When the card is inserted, an i.MX31 GPIO signal
detects the presence of the memory stick.
Data transfer can be performed by CPU or eDMA with a maximum transfer
rate of 19.7 Mbytes per second.
Each port has ten connector pins. Memory Stick is serial with a 20 MHz
clock. Memory Stick Pro is a 4-bit bus with a 40 MHz clock, which complies
with the mentioned 19.7 Mbytes per second after some overhead reduction.
15
ATA-6
ATA Interface Block Diagram
The Advanced Technology Attachment (ATA) block is an AT attachment
host interface. Its main use is to interface with IDE hard disc drives and
ATAPI optical disc drives. It interfaces with the ATA device over a number of
ATA signals.
The ATA interface communicates with the ATA peripherals connected to the
ATA bus by means of PIO mode read/write operation to the ATA bus, and
DMA transfers with the ATA bus.
The ATA interface has 2 busses connected. One is the DMA bus for
communication with the host DMA unit. The other is the CPU bus for
communication with the host processor. All internal registers are visible from
both busses, allowing eDMA access to program the interface.
The ATA interface is compliant with the ATA-6 standard and supports
several protocols. They are PIO mode 0, 1, 2, 3 and 4; multiword DMA mode
0, 1 and 2; Ultra DMA modes 0-4 with bus clock of 50 MHz or higher; and
Ultra DMA mode 5 with bus clock of 80 MHz or higher.
16
SIM
Secure
Network Access
Cards
SIM CARD
i.MX31
SIM
SIM CARD
Banking
Eurochip
Pre-paid
Calling cards
Satellite TV
Government
Identification
The Subscriber Identification Module (SIM) is designed to facilitate
communication to SIM cards. It interfaces to an external subscriber
identification card and serves as an asynchronous serial interface adapted
for smart card communication.
The SIM module has two ports that can be used to interface with the various
cards.
Some target applications of the SIM include secure network access cards,
banking, Eurochip pre-paid calling cards, satellite TV, and government
identification.
Some of the features of the SIM include a 16/32 bytes deep Tx/Rx FIFO,
automatic NACK generation/detection on parity and overrun errors, and
hardware data format support (inverse or direct convention). The SIM also
includes retransmission of data upon a SIM card, NACK request with a
programmable maximum threshold of retransmissions, decoding of initial
character mode for setting data format, 11 ETU character support, and a
character wait time counter.
17
i.MX21 and i.MX31 Comparison
Fast IR
Timers
GPIO
SSI/ I2S
Real-Time
Clock
Watchdog
Timer
1-Wire
Keypad
PWM
PCMCIA/CF
3 x I2C
3 x Configurable SPI
5 x UARTs
Now let’s compare the i.MX31 and the i.MX21 processors.
There are no differences between the following blocks on the i.MX21 and the
i.MX31: Fast IR, the timers, GPIO, SSI/ I2S, real-time clock, watchdog timer,
1-wire, keypad, PWM, and PCMCIA/CF.
On the i.MX31, the I2C has increased to 3 blocks, the configurable SPI has
increased to 3 blocks, and a fifth UART has been added.
18
Question
Here are some statements about i.MX31 processor connectivity. Identify
whether each statement is “True” or “False” by dragging the letters on
the left to the statements on the right. Click Done when you are finished.
A
B
A
The ATA interface connects to the DMA bus and the
CPU bus.
B
The SIM module has one port that can be used to
interface with various cards.
B
The sensor port can interface with up to two
image sensors at the same time.
A
The i.MX31 has two ports to connect with the
Sony Memory Stick PRO.
True
False
Done
Reset
Show
Solution
Let’s review some general information about the connectivity of the i.MX31
processor.
Correct.
The ATA interface connects to two busses. One is the DMA bus for
communication with the host DMA unit and the other is the CPU bus for
communication with the host processor. The SIM module, in fact, has two
ports that can be used to interface with the various cards. The sensor port
provides a connection to either one or two image sensors, but can only one
sensor can be active at any given time. The Sony Memory Stick PRO
connects to the i.MX31 via two ports.
19
Module Summary
•
USB
•
eDMA
•
AUDMUX
•
Display port
•
Sensor port
•
ATA interface
•
SIM
In this module, you learned that the USB module provides high performance
USB On-the-Go functionality, and the eDMA maximizes the system’s
performance. You learned that the AUDMUX is a digital multiplexer that
supports bi-directional data transfers without the need for host processor
intervention. You learned that the i.MX31 display port supports three types of
interfaces; synchronous parallel, asynchronous parallel, and asynchronous
serial. The sensor allows connection to either one or two image sensors.
Finally, you learned that the ATA block is an AT attachment host interface and
the SIM is designed to facilitate communication to SIM cards.
20