Real Digital Problem Set #7
1. (10 points) Modify the state diagram branching conditions in the diagrams below as needed to
ensure the sum and exclusion rules are obeyed in each case. You can add a holding conditions or
change branch codes as desired.
RESET
A
X = '1' and
Y = ‘1’
X = '0' and
Y = ‘1’
Y=’0' and W='0'
S1
X='1'
X='0'
W=’1'
C
B
X=’0' and Y=’0'
and Z='1'
D
S2
E
X=’0' and
Y=’1'
S4
S3
X=’0' and Y=’0'
and Z='0'
X='0' and
Y=‘0’
Modify the S4 branch and holding condition only
2. (4 points) What “to S2” branch can be added so that all possible
branch conditions go to at least one state? How can the holding
condition be modified to ensure there is one and only one next
state for all possible branch conditions? Enter the branch
conditions below.
To S2:___________
X=’0'
Holding condition:___________
Y·Z
S0
X·Y + Y·Z
X·Z
S1
S2
S3
Real Digital
Problem Set #7
3. (15 points) A vending machine should SELL an item if 30 cents is input. The machine has a coin
sensor that can detect nickels, dimes, and quarters, and reject everything else. No change is
given (i.e, if two quarters are input, simply assert SELL and keep the fifty cents). Sketch a state
diagram to assert SELL when adequate coinage has been inserted.
Real Digital
Problem Set #7
4. (15 points) Sketch a Moore-model and also a Mealy-model state diagram for a sequential machine
that can detect when a four-digit combination has been typed into a numeric keypad. Use last four
numbers of your telephone number for a combination. A “start” button must be pressed
immediately prior to entering a valid combination, and an “open” button must be pressed
immediately after a valid combination. For this problem, you can assume that two buttons cannot
be asserted simultaneously (i.e., if more than one button is pressed, only the signal from the first
button pressed will be asserted until it is released; the second button will be asserted after the first
button is released if it is still being pressed. If more than two buttons are pressed, and the first
button pressed is released, then the second button pressed will be asserted until it is released,
and so forth). The “Any Button” (AB) output will be asserted as soon as any button is pressed, and
deasserted only when no buttons are pressed.
1
2
3
4
5
6
7
8
9
St
0
Op
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
St
Op
AB
Real Digital
Problem Set #7
5. (25 points) Sketch a circuit for the state machines below.
BPS
RESET
0
1
1
f
1
1
1
APS
00
BPS
APS
X = '1'
10
11
RED <= '1'
Y = '0'
BPS
0
0
1
f
1
1
0
APS
0
ANS
X = '1'
X = '0'
X = '0'
0
0
1
Y = '1'
0
X
1
f
X
Y
RED
BPS
APS
0
1
0
0
1
f
0
1
BNS
GRN <= '1'
Next-state maps
GRN
Output Maps
6. (16 points) In the timing diagram below, show the time courses of the flip-flops (labeled A and B)
and output signals defined by the state diagram.
00
A·B
B
A·B
B
BLU <= B
RST
A
B
10
F1F2
CLK
01
A
00 01 00 01 11 11 11 10 11 10 00
RED
A
11
A·B
A+B
BLU
RED <= A
B
F1
F2
RED
BLU
Real Digital
Problem Set #7
7. (25 points) Sketch a state diagram based on the following Verilog Code
module fsm (
CLK, RST, X, Y, Z, RED, BLUE);
input CLK, RST, X, Y, Z;
output reg RED, BLUE;
localparam
localparam
localparam
localparam
S1
S2
S3
S4
=
=
=
=
2’d0;
2’d1;
2’d2;
2’d3;
reg [1:0] ps, ns;
always @ (ps, x, y, z)
begin
case (ps)
S1: begin
RED = 1’b0;
BLUE = 1’b0;
if (X == 1’b0) ns = S1;
else ns = S2;
end
S2: begin
RED = 1’b0;
BLUE = 1’b1;
if (X == 1’b0 && Y == 1’b0
else if (X == 1’b1 || Y ==
else if (Z == 1’b1 && X ==
end
S3: begin
RED = Y;
BLUE = 1’b0;
if (Y == 1’b1 && X == 1’b0
else if (X == 1’b0 && Y ==
else if (X == 1’b1 || Z ==
end
S4: begin
RED = 1’b1;
BLUE = X;
ns = S1;
end
default: begin
RED = 1’b0;
BLUE = 1’b0;
ns = S1;
end
endcase
end
always @ (CLK, RST)
begin
if (RST == 1’b1) ps <= S1;
else ps <= ns;
end
endmodule
&& Z == 1’b0) ns = S2;
1’b1) ns = S1;
1’b0 && Y == 1’b0) ns = S3;
&& Z == 1’b0) ns = S4;
1’b0 && Z == 1’b0) ns = S3;
1’b1) ns = S1;
Real Digital
Problem Set #7
8. (16 points) Assign state codes to the state diagrams below, using unit-distance coding and/or
matching state codes to outputs
RESET
RESET
ODD <= '1'
X = '0'
X = '1'
Y = '0'
Y = '1'
Y = '1'
Y = '0'
ODD <= '1'
GRN <= '1'
RED <= '1'
RESET
RESET
X = '0' and
Y = ‘0’
X = '0'
X = '0' and
Y = ‘1’
X = '1'
X = '1'
X='1'
BLU <= '1'
RED <= '1'
GRN <= '1'
X = '0' and
Y = ‘1’
X = '1' or
Y = ‘0’
X = '0' and
Y = ‘0’
Y = '0'
Y = '1'
RED <= '1'
X='0'
GRN <= '1'
X='1' and
Y=‘0’
Y = '0'
Y = '1'
Y = '1'
GRN <= '1'
RED <= '1'
GRN <= '1'
BLU <= '1'
Real Digital
Problem Set #7
9. (16 points) A simple state machine must assert three outputs (R, G, B) in sequence for 333ms
each. An input signal called “Start” is created from a push button. Sketch a state machine that can
output the required sequence of signals (R, G, and B) once each time the button is pressed. You
have a 3Hz clock and a 1KHz clock to work with. The push button can bounce for up to 2ms on
any transition. (Hint: You can use two state machines)
Real Digital
Problem Set #7
10. (8 points) A state machine receives an input X that is synchronous with the system clock. If X is a
1, then the machine must output a signal RED for one clock cycle. Then, if X is still asserted, the
machine must output a signal GRN for one clock cycle, but if X is not asserted, the machine must
assert an output called BLU. The state diagram below meets these requirements. Can you sketch
a machine that can meet these same requirements, but that uses just one flip-flop?
X
S0
X
X
S2
GRN
S1
Red
X
S3
BLU