APPLIED PHYSICS LETTERS 89, 042104 s2006d
Evidence of electron and hole inversion in GaAs metal-oxide-semiconductor
capacitors with HfO2 gate dielectrics and a-Si/ SiO2 interlayers
S. J. Koester,a! E. W. Kiewra, Yanning Sun, D. A. Neumayer, J. A. Ott,
M. Copel, and D. K. Sadana
IBM Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598
D. J. Webb, J. Fompeyrine, J.-P. Locquet, C. Marchiori, M. Sousa, and R. Germann
IBM Zurich Research Laboratory, Säumerstrasse 4/Postfach, CH-8803 Rüschlikon, Switzerland
sReceived 26 January 2006; accepted 20 June 2006; published online 25 July 2006d
Evidence of inversion in GaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectrics and
a-Si/ SiO2 interlayers is reported. Capacitors formed on n-GaAs with atomic layer-deposited HfO2
displayed C-V characteristics with minimum Dit of 7 3 1011 cm−2 / eV, while capacitors with
molecular beam epitaxy-deposited HfO2 on p-GaAs had Dit = 3 3 1012 cm−2 / eV. Lateral charge
transport was confirmed using illuminated C-V measurements on capacitors fabricated with thick
Al electrodes. Under these conditions, capacitors on n-GaAs sp-GaAsd showed “low-frequency”
C-V behavior, indicated by a sharp capacitance increase and saturation at negative spositived gate
bias, confirming the presence of mobile charge at the semiconductor/dielectric interface. © 2006
American Institute of Physics. fDOI: 10.1063/1.2235862g
does not suffer from strain-induced band gap shrinkage. In
this letter we study the electrical characteristics of GaAs
MOS capacitors with both molecular beam epitaxy sMBEd
and atomic layer deposited HfO2 gate dielectrics using
a-Si/ SiO2 interlayers. We show that these structures have
low interface state density and are thermally stable to temperatures as high as 900 ° C. We further demonstrate evidence of inversion, for both electrons and holes, using an
illuminated C-V technique which confirms the presence of
mobile surface charge at the semiconductor-dielectric
interface.
The starting samples used in this work were n-type and
p-type GaAs wafers with doping concentrations of
s0.7– 1.0d 3 1018 and s0.2– 0.5d 3 1018 cm−3, respectively.
The wafers were cleaned using UV-generated ozone, followed by treatment in an aqueous sNH4d2S solution before
loading the substrates into a Riber MBE chamber. The
samples were then exposed to a mixture of atomic argon and
hydrogen diffusing out of a remote rf plasma source while
the reflection high-energy electron diffraction sRHEEDd pattern was monitored. Once the RHEED pattern had stabilized,
a-Si was deposited onto the samples. The entire surface
preparation was performed at temperatures ,250 ° C. For
the n-type GaAs, the sample was then removed from the
chamber, and the a-Si was allowed to form a native oxide in
air, and then HfO2 was deposited by atomic layer deposition
sALDd at 300 ° C. For the p-type GaAs sample, after a-Si
deposition, HfO2 was deposited in situ by electron-beam
evaporation of Hf in the presence of atomic O generated by a
different rf remote plasma source. After deposition of the
HfO2, the samples were subjected to anneals at various temperatures in a N2-purged rapid-thermal annealing system.
Figure 1sad shows a cross-sectional transmission electron
micrograph sTEMd of a n-type GaAs sample after annealing
at 800 ° C for 1 min. The HfO2 layer thickness is 8.3 nm,
while the a-Si/ SiO2 interlayer has a combined average
thickness of 1.9 nm. Several angstroms of roughness were
observed for the a-Si/ SiO2 interlayer, as well as for the
GaAs surface itself. Delineation between the a-Si and SiO2
In recent years, a paradigm shift has started to occur in
the complementary metal-oxide-semiconductor sCMOSd industry, where materials innovation, rather than scaling, has
become the primary driver for achieving performance improvement. Perhaps the most dramatic materials innovation
that is being considered for future CMOS technologies is the
incorporation of III-V channel materials.1 Due to their high
mobility, III-V channels could have a tremendous advantage
for digital logic applications, because they could dramatically improve the power/performance trade-off that is so
critical for the wide range of systems that rely upon CMOS
technology. GaAs emerges as a natural choice for III-Vchannel metal-oxide-semiconductor field-effect transistors
sMOSFETsd, due to the fact that it has a high electron mobility sapproximately six times higher than in Sid, and is also
lattice matched to Ge, thus opening the possibility of creating a high-mobility CMOS platform based upon GaAs
NFETs and Ge PFETs.
In order to implement a GaAs MOSFET technology,
however, an effective gate stack solution needs to be developed. This gate stack must overcome the problem of Fermilevel pinning at the GaAs surface,2 as well as allow the incorporation of state-of-the art high-k dielectrics3 that will be
needed to meet future ITRS performance targets. Previously,
several approaches have been taken to address the pinning
problem.4–10 Perhaps the most promising of these is the use
of a Si interlayer between the GaAs and the deposited gate
dielectric.4–7 However, as pointed out by Chen et al.,11
pseudomorphic Si layers are problematic in that the Si can
act like a parasitic surface quantum well due to straininduced band gap shrinkage. More recently, amorphous Si
sa-Sid interlayers with HfO2 gate dielectrics have been studied and shown to produce a high-quality interface with
GaAs.12 Compared to pseudomorphic interlayers, the a-Si
layer approach has the advantage that a-Si can have a relatively wide band gap f,1.5– 2.1 eV sRefs. 13 and 14dg and
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Electronic mail: [email protected]
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Koester et al.
Appl. Phys. Lett. 89, 042104 ~2006!
FIG. 1. sad Cross-sectional TEM of MOS structure on n-GaAs with
a-Si/ SiO2 interlayer and atomic layer deposited HfO2 after annealing at
800 ° C for 1 min in N2. sbd High-resolution TEM image of MOS structure
with a-Si/ SiO2 interlayer and in situ deposited MBE HfO2 after annealing
at 900 ° C for 5 s in N2.
FIG. 2. sColor onlined sad Plot of C-V characteristics at 1, 10, and 100 kHz
for MOS capacitors on sad n-type and sbd p-type GaAs with a-Si/ SiO2
interlayers. Insets: Plot of Dit vs gate voltage for HfO2-gated MOS capacitors on sad n-GaAs and sbd p-GaAs.
portions of the interlayer could not be determined by TEM,
though x-ray photoemission spectroscopy sXPSd analysis on
a similar structure indicated that some unreacted a-Si remained even after annealing at 800 ° C. A high-resolution
TEM of the p-type GaAs sample after annealing at 900 ° C
for 5 s is shown in Fig. 1sbd. Here the MBE-deposited HfO2
layer thickness is 11 nm, and the combined a-Si/ SiO2 interlayer thickness is 4.8 nm. The TEM shows no evidence of
crystallization in the interlayer, despite the aggressive thermal treatment.
For the C-V measurements, circular dot capacitors with
areas of ,10−4 cm2 were formed by thermal evaporation of
Al metal through a shadow mask and deposition of a backside Ohmic contact. The capacitors had metal thicknesses
such that they were opaque to illumination under an optical
microscope during testing. The measurements were performed using an HP4284A LCR meter, after open-circuit
calibration, and the capacitance was measured as a function
of voltage, where the voltage was swept from depletion
to accumulation and back again. The rms oscillator
amplitude was 50 mV, and frequencies ranging from
100 Hz to 100 kHz were utilized. The C-V results of n-MOS
capacitors after annealing at 700 ° C for 1 min are shown in
Fig. 2sad. The C-V curves have very little frequency dispersion; the accumulation capacitance was reduced by only
1.5% per decade of frequency change, and the apparent flatband voltage shifted by only 20 mV/decade. About 400 mV
of hysteresis was observed between the forward and reverse
voltage sweeps. The C-V results for the p-MOS capacitors
after annealing under the same conditions are shown in Fig.
2sbd. These devices displayed increased frequency dispersion
compared to the n-GaAs samples and had hysteresis of
,100 mV. Single-frequency conductance measurements
were utilized to determine the interface state density Dit.15
The results for the n-GaAs samples are shown in the inset of
Fig. 2sad, where Dit is plotted versus gate voltage. The minimum Dit value obtained was 7 3 1011 cm−2 / eV, which is
roughly an order of magnitude lower than for capacitors
with HfO2 directly on GaAs. A minimum Dit value of
3 3 1012 cm−2 / eV was obtained on the HfO2-gated p-GaAs
samples, as shown in the inset of Fig. 2sbd.
A key question in assessing the suitability of
a-Si/ SiO2 / HfO2 gate stacks for practical applications is
whether or not inversion can be achieved. In much of the
previous literature,4–8 quasistatic C-V measurements have
been utilized to detect carrier inversion. However, quasistatic
C-V is not ideal for this purpose, since it is not only sensitive
to free carriers, but also trap-induced fixed charge buildup at
the semiconductor/dielectric interface. Therefore, in order to
investigate the possible presence of inversion in our structures, we have utilized a methodology based upon illuminated C-V measurements that confirms the presence of
mobile surface charge in our structures. For these measurements, the dot capacitors were tested under an optical microscope and illuminated using the output of a 150 W tungstenhalogen lamp that was focused onto the sample though a
503 objective lens. The illuminated spot was approximately
500 mm in diameter, several times larger than the dot diameter of ,100 mm. Since the dot was opaque, only the exposed GaAs regions at the periphery of the dot were exposed
to the illumination. The purpose of the illumination can be
understood by considering a capacitor on p-type GaAs. First
of all, the peripheral illumination provides a source of charge
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042104-3
Koester et al.
Appl. Phys. Lett. 89, 042104 ~2006!
the above argument, these results confirm the presence of
mobile surface charge in our MOS capacitor structures.
An outstanding question for these samples is the precise
location of the surface charge, since a true inversion condition requires that at least a portion of the mobile surface
charge resides in the GaAs layer itself. The effective oxide
thicknesses sEOTd extracted from the illuminated capacitance values in Fig. 3 are EOT= 3.4 and 3.1 nm for the nand p-GaAs samples, respectively. Based upon the HfO2 and
interlayer thickness measured by TEM, the EOT value for
the n-GaAs sample suggests that the mobile charge layer is
at the GaAs surface, while the p-GaAs value indicates that
the carriers are located in the a-Si layer. However, without
precise knowledge of a-Si and SiO2 individual layer thicknesses, accurate determination of the mobile charge layer
location is difficult.
In conclusion, mobile charge transport at the
semiconductor/dielectric interface of HfO2-gated GaAs MOS
capacitors with a-Si/ SiO2 interlayers has been demonstrated, providing strong evidence that carrier inversion can
be achieved in these structures. These results are an important step toward the ultimate goal of realizing true surfacechannel, inversion-mode GaAs MOSFETs.
The authors would like to acknowledge useful discussions with E. Cartier and P. M. Solomon, and also thank G.
G. Shahidi for management support.
FIG. 3. sColor onlined C-V characteristics at 100 Hz in the dark and using
peripheral illumination for MOS capacitors on sad n-type and sbd p-type
GaAs with a-Si/ SiO2 interlayers.
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such that a quasiequilibrium surface electron layer can be
maintained as the gate bias is swept to positive voltages, thus
preventing the device from going into deep depletion. Secondly, the illumination reduces the potential barrier from the
surface electron layer to the bulk material at the edges of the
dot, so that the electrons can respond to the ac excitation
signal faster than when the sample is tested in the dark. The
presence of surface electrons is therefore confirmed if conditions can be found where “high-frequency” C-V behavior
is observed in the dark, but “low-frequency” behavior is observed under illumination, since this situation can only occur
by means of lateral transport of free electrons between the
interior and edges of the dot. A similar situation applies to
identifying surface hole transport in MOS capacitors on
n-type GaAs.
Figure 3sad shows the C-V characteristics of a MOS capacitor with a-Si/ SiO2 interlayer and HfO2 dielectric on n
-GaAs, at a frequency of 100 Hz, both in the dark and using
the illumination scheme described above. In the dark, the
capacitors show typical high-frequency characteristics. However, when the sample is illuminated, low-frequency behavior is observed, as evidenced by a sharp capacitance increase
starting at Vgs , −0.5 V followed by capacitance saturation at
Vgs , −1.5 V. In Fig. 3sbd, similar characteristics are observed when the p-type sample is illuminated. Based upon
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