Divideby3FSM
• Outputshouldbe“1”every3clockcycles
S2
S0
S1
Thedoublecircleindicatestheresetstate
SlidederivedfromslidesbyHarris&Harrisfromtheirbook
1
FiniteStateMachines(FSMs)
• AsimpleMooremachinelookslikethe
following
inputs
M
next
state
logic
CLK
next
k state
k
SlidederivedfromslidesbyHarris&Harrisfromtheirbook
state
output
logic
N
outputs
2
FSMExampleinSystemVerilog
module divideby3FSM (input logic clk, reset_n,
output logic q);
enum logic [1:0] {S0=2’b00, S1=2’b01, S2=2’b10} state; // declare states as enum
// next state logic and state register
always_ff @(posedge clk, negedge reset_n)
begin
if (!reset_n)
state <= S0;
else begin
case (state)
S0: state <= S1;
state transition graph is the same
S1: state <= S2;
thing as a state transition table, which
S2: state <= S0;
can be specify as a case statement
endcase
end
end
// output logic
assign q = (state == S0);
endmodule
output is “1” every clock cycles when we are in state S0
3
FSMExampleinSystemVerilog
module divideby3FSM (input logic clk, reset_n,
output logic q);
enum logic [1:0] {S0=2’b00, S1=2’b01, S2=2’b10} state; // declare states as enum
// next state logic and state register
always_ff @(posedge clk, negedge reset_n)
begin
if (!reset_n)
state <= S0;
else begin
case (state)
S0: state <= S1;
S1: state <= S2;
S2: state <= S0;
endcase
end
end
compilerrecognizesthis“template”shoulduse
positiveedge-triggeredflip-flopsw/negativeedge
asynchronousresetshouldbeused.
compilerknowsthis“if”
partdefinesthereset
valuesforflip-flops.
state
next
state
logic
FF
output
logic
q
// output logic
assign q = (state == S0);
endmodule
4
Whatasynchronousresetmeans
• “Negative-edgeasynchronousreset”means
thefollowing:
reset_n
flip-flopsgetresetonthisnegedgetransition
clk
5
ContinuingwiththeFSMExample
• Whatifwewanttodesignthe“Divideby3FSM”
examplewithjustone“always_ff”statement(no
separate“assign”statement)?
• Let’sassumewestillwant“q”tobe“1”whenweare
instate“S0”.
• Canweputthelogicfor“q”insteadthe“always_ff”
statement?
• Yes,butaflip-flopwillbecreatedfor“q”!
6
FSMExampleinSystemVerilog
module fsm2 (input logic clk, reset_n, output logic q);
enum logic [1:0] {S0=2'b00, S1=2'b01, S2=2'b10} state; // declare states as enum
always_ff @(posedge clk, negedge reset_n)
begin
if (!reset_n) begin
state <= S0;
synthesiswillgenerateD-FFs
q <= 1;
forboth“state”and“q”
end else begin
case (state)
S0: begin
state <= S1;
q <= 0;
end
S1: begin
state <= S2;
q <= 0;
end
S2: begin
inordertohavetheoutput“q”=1when“state”
state <= S0;
isinS0,havetosettheD-FFfor“q”inS2sothat
q <= 1;
theoutput“q”=1when“state”getstoS0.
end
endcase
end
end
endmodule
7
FSMExampleinSystemVerilog
module fsm2 (input logic clk, reset_n, output logic q);
enum logic [1:0] {S0=2'b00, S1=2'b01, S2=2'b10} state; // declare states as enum
always_ff @(posedge clk, negedge reset_n)
begin
if (!reset_n) begin
state <= S0;
q <= 1;
end else begin
case (state)
S0: begin
state <= S1;
q <= 0;
end
S1: begin
state <= S2;
q <= 0;
end
S2: begin
state <= S0;
q <= 1;
end
endcase
end
end
endmodule
compilerknowsthis“if”
partdefinesthereset
valuesforflip-flops.
state
next
state
logic
FF
logicfor
“q”
FF
q
8
FibonacciCalculator
• F(0)=0,F(1)=1
• F(n)=F(n– 1)+F(n– 2),whenn>1
• Examples:
9
FibonacciCalculator
•
•
•
•
DesignaFSMwiththeinterfacebelow.
input_s is“n”,andfibo_out is“F(n)”.
WaitinIDLEstateuntilbegin_fibo.
Whentestbenchseesdone==1,itwillcheckiffibo_out==
F(input_s).
module fibonacci_calculator (input
input
input
output
output
...
always_ff @(posedge clk, negedge
begin
clk
...
end
reset_n
endmodule
input_s
begiin_fibo
logic
logic
logic
logic
logic
clk, reset_n,
[4:0] input_s,
begin_fibo,
[15:0] fibo_out,
done);
reset_n)
fibonacci_
calculator
fibo_out
done
10
FibonacciCalculator
• Basicideaistointroduce3registers:
logic [4:0] counter;
logic [15:0] R0, R1;
• Setloopcounterto“n”
counter <= input_s;
• Repeataslongascounterisgreaterthan1sincewe
alreadyknowwhatF(0)andF(1)are:
counter <= counter – 1;
R0 <= R0 + R1;
R1 <= R0;
• Finally,setoutputto“F(n)”
done <= 1;
fibo_out <= R0;
11
FibonacciCalculator
module fibonacci_calculator (input logic clk, reset_n,
input logic [4:0] input_s,
input logic begin_fibo,
output logic [15:0] fibo_out,
output logic done);
enum logic [1:0] {IDLE=2'b00, COMPUTE=2'b01, DONE=2'b10} state;
logic [4:0] count;
logic [15:0] R0, R1;
always_ff @(posedge clk, negedge reset_n)
begin
if (!reset_n) begin
state <= IDLE;
done <= 0;
end else
case (state)
IDLE:
inclockedalwaysstmts,
if (begin_fibo) begin
D-FFskeeptrackof
count <= input_s;
previousvalue,sothe
R0 <= 1;
missing“else”partwill
R1 <= 0;
justkeep“state”at
state <= COMPUTE;
end
IDLE.
COMPUTE:
if (count > 1) begin
count <= count - 1;
R0 <= R0 + R1;
R1 <= R0;
end else begin
state <= DONE;
done <= 1;
fibo_out <= R0;
end
DONE:
state <= IDLE;
endcase
end
endmodule
12
FibonacciCalculator
• Athreestatesolutionisprovided.
• Designitusingonly2states (orfewer)w/ocreating
flip-flopsforfibo_out ordone,andshouldwork
forn≥1. Hint:use“assign”statementsfor
fibo_out anddone.
• Useprovided“tb_fibonacci_calculator.sv”toverify
yourdesignusingModelSim.
• Synthesizeyour2-state“fibonacci_calculator.sv”
designusingQuartus.
13
FSMDtoVHDL:One’scounter
• FSMDcanbedirectlymappedtoVerilog
withoutanyfurthermicroarchitecture
exploration
• Logicsynthesistoolwillinferboththe
datapath andtheFSMthatcorrespondstothe
FSMDmodel
– Multiplexersandcontrolsignalsarenowhidden
bythedesignerandappearonlyafterlogic
synthesis
• FSMDcanbemappedtooneprocess
always @(posedge clk or negedge rst)
begin
if (!rst)
state <= S0;
else begin
case (state)
S0 : if (start) state <= S1;
else state <= S0; // redundant
S1 : done<=‘0’;
data<=input;
state <= S2;
S2 : Ocount <= 0;
state <= S3;
S3 : mask <= 1;
state <= S4;
S4 : temp <= data & mask;
state <= S5;
S5 : Ocount <= Ocount + temp;
state <= S6;
S6 : data[14:0] <= data[15:1];
data[15] <= 0;
...
endcase
end
end
Allvariablesassignedunder
risingedgeofclock=>registers
inferred
Assignmentandchecking
• Ifcodedthiswayconditionchecking(data=0)
willseetheoldvalueofdata(datainthe
previouscycle)
• Toworkcorrectlytheassignmentofdata
shouldbemadeblocking(notpreferred)orto
addanextrastatebetweenS6andcondition
checking
always @ (posedge clk)
...
case (state)
...
S6: data[14:0] <= data[15:1];
data[15] <= 1’b0;
if (data)
state <= S7;
else
state <= s4;
Blockingassignmentwillchaintogetherbothshiftingandconditioncheckingasa
combinationalcircuit
Inthiscasenotaproblembutnotscalableinthegenericcase
FSMDwithdummycheckstate
case (state)
...
S6: data[14:0] <= data[15:1]
data[15] <= 0;
state <= check
check: if (data == 0)
state <= S7;
else
state <= s4;
s7: done <= 1;
output <= Ocount;
state <= s0;
ConvertingfromCtoHigh-LevelStateMachine
• ConverteachCconstructto
equivalentstatesand
transitions
• Assignment statement
– Becomesonestatewith
assignment
target :=
expression
target = expression;
a
• If-then statement
– Becomesstatewith
conditioncheck,
transitioningto“then”
statementsifconditiontrue,
otherwisetoendingstate
• “then”statementswouldalsobe
convertedtostates
18
cond’
if (cond) {
// then stmts
}
cond
(then stmts)
(end)
a
ConvertingfromCtoHigh-LevelStateMachine
• If-then-else
– Becomesstatewithcondition
check,transitioningto“then”
statementsifconditiontrue,or
to“else”statementsif
conditionfalse
cond’
if (cond) {
// then stmts
}
else {
// else stmts
}
cond
(then stmts) (else stmts)
a
(end)
• Whileloopstatement
– Becomesstatewithcondition
check,transitioningtowhile
loop’sstatementsiftrue,then
transitioningbacktocondition
check
cond’
while (cond) {
// while stmts
}
cond
(while stmts)
(end)
19
a
SimpleExampleofConvertingfromCtoHigh-LevelStateMachine
Inputs: uint X, Y
Outputs: uint Max
(X>Y)’
(X>Y)’
X>Y
X>Y
if (X > Y) {
Max = X;
(then stmts)
(else stmts)
Max:=X
Max:=Y
}
else {
Max = Y;
}
(end)
(end)
a
a
(a)
(b)
(c)
• Simpleexample:Computingthemaximumoftwonumbers
– Convertif-then-elsestatementtostates(b)
– Thenconvertassignmentstatementstostates(c)
20
Example:SADCcode
toHLSM
Converteachconstructto
states
•
Inputs: byte A[256],B[256]
bit go;
Output: int sad
main()
{
uint sum; short uint i;
while (1) {
RTLdesignprocessto
converttocircuit
CanthusconvertCto
circuitusing
straightforwardprocess
•
– Actually,subsetofC
(notallCconstructs
easilyconvertible)
– Canuselanguageother
thanC
go'
go'
}
go'
go
sum:=0
i:=0
i=0
sum = 0;
i = 0;
}
go
sum:=0
while (!go);
– Simplify,e.g.,merge
states
•
(go')'
(c)
(b)
while (i < 256) {
sum = sum + abs(A[i] – B[i]);
i = i + 1;
}
sad = sum;
go'
(d)
go
go'
go
(a)
sum:=0
i:=0
go'
sum:=0
i:=0
go
(i<256)'
sum:=0
i:=0
i<256
(i<256)'
sum:=sum
+ abs...
i := i + 1
i<256
while stmts
(i<256)'
i<256
sum:=sum
+ abs...
i := i + 1
sadreg :=
sum
(g)
21
(e)
sadreg :=
sum
(f)
a
Example1
S7
Dfreq=dcnt
S0
Busy=0
S1
Busy=1,i =sAddr
S2
now=A[i],dcnt=0
X
i<1024
S4
XX
Last-now>=5
Last=now=,now=A[i]
Last-now<5
S5
S6
dcnt=dcnt+1
i=i+1
Example2
Forloopscanbe
treated
equivalentlyas
whileloop
i=0
While (i < cond) {
…
i++
}
Sorting
• Sortingunitkeepsinsideasmallregisterfile
• Theuserwritesorreadsthevaluestothisregisterfilewhen
s=0
• Whenstart=1sortingbeginsandendswhenDone=1
– Ifstart=0systemreturnstoIDLEphasewaitingforre-initializationor
readingoutthesortednumbers
ΣυστήματαVLSI
24
Sortingalgorithm- bubblesort
ΣυστήματαVLSI
25
Staterequired
• Registerfileforstoring
datatobesorted
M[address]
– Numberofread/write
portsdeterminethe
efficiencyofsorting
• A,Bregistersforstoring
thepairofvaluesunder
comparison
• i,j loopcounters
ΣυστήματαVLSI
26
Expressingloopswithregisters
ΣυστήματαVLSI
27
Datapath forsorting
ΣυστήματαVLSI
Onlyoneport(oneaddressportconnection)usedforreadingor
writing.Oneactionpercycleisallowed
28
Datatransfers
• AandBarewrittenandreadthroughmemory
• Whatadditionisrequiredtothedatapath totransferBtoA?
Amux is
requiredat
theinputofA
ΣυστήματαVLSI
29
Scheduleofoperationsforsorting
Cycles
Module
0
Mem
2
3
Read@i Read@j
RegisterA
4
5
6
7
Write@i Write@j Read@i
A<-M[i]
RegisterB
Count I
1
A<-M[i]
B<-M[j]
i++
Count j
j++
AgtB
A>B
1st iterationforj
1st iterationfori
•
•
•
ControlimplementedasaMooreFSM
Thenumberofcycleslimitthethroughputofsorting
Therealproblemisnottheavailablecomputationbutthelackofmorememoryports
–
ΣυστήματαVLSI
Moreoperationsinterleavingcanbepossiblewithadiffe
30
GCD
31
GCDinterface
32
Datapath modules:Arith+Registers
33
Datapath modules:Arith+Registers
34
35
36
moduleGCD
#(parameterW=8)(
inputlogicclk,
inputlogicrst,
inputlogic[W-1:0]operand_bits_A,
inputlogic[W-1:0]operand_bits_B,
inputlogicoperands_val,
outputlogicoperands_rdy,
outputlogicresult_val,
inputlogicresult_rdy,
outputlogic[W-1:0]result_bits_data);
37
38