PE19601
Document Category: Product Specification
Monolithic Phase & Amplitude Controller, 8–12 GHz
Features
Figure 1 • PE19601 Functional Diagram
• Broadband operation with 50Ω impedance
• 6/10 bit phase shifter
RX_IN
• 6-bit attenuation
• High power handling
TX_IN
• Bare wirebond die
Applications
• Airborne weather radar and airborne radar
SCLK
SDI
SDO
LE
• Ground-based phased array weather radar
VDD
• Ground-based phased array scanning radar
VSS
MODE
TWK_0
Serial Bus Control
• Input IP3 of +40 dBm
CAL
TWK_1
RX_OUT
TX_OUT
Product Description
The PE19601 is a HaRP™ technology-enhanced monolithic phase and amplitude controller (MPAC)–
beamforming device designed for radar and beamforming networks. The PE19601 consists of a digital step
attenuator (DSA), a phase shifter and RX/TX switching. This functionality is intended for the amplitude and
phase control of signals to individual elements in an electronic scanning phased antenna array.
It offers a maximum power handling of +17 dBm up to 12 GHz and covers 31.5 dB attenuation range in 0.5 dB
steps. The phase shifter offers 360° of phase range with a resolution of 5.6°. The device provides a serial
interface to control the attenuation, phase and RX/TX switching. It maintains high attenuation and phase
accuracy over frequency and temperature and exhibits low power consumption.
©2015–2016, Peregrine Semiconductor Corporation. All rights reserved. • Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121
Product Specification
DOC-69095-5 – (09/2016)
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PE19601
MPAC–Beamforming
Figure 2–Figure 9 display the PE19601 switch configurations.
Figure 2 • TX Calibration
Figure 4 • RX Calibration
RX_IN
RX_IN
TX_IN
VDD
VSS
MODE
TWK_0
SCLK
SDI
SDO
LE
CAL
VDD
VSS
MODE
TWK_0
Serial Bus Control
SCLK
SDI
SDO
LE
Serial Bus Control
TX_IN
TWK_1
TWK_1
RX_OUT
RX_OUT
TX_OUT
TX_OUT
Figure 3 • TX Nominal/TX Only
Figure 5 • RX Nominal/RX Only
RX_IN
RX_IN
TX_IN
VSS
MODE
TWK_0
SCLK
SDI
SDO
LE
CAL
VDD
VSS
MODE
TWK_0
Serial Bus Control
VDD
Serial Bus Control
TX_IN
SCLK
SDI
SDO
LE
CAL
CAL
TWK_1
TWK_1
RX_OUT
RX_OUT
TX_OUT
TX_OUT
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PE19601
MPAC–Beamforming
Figure 6 • Cal In
Figure 8 • Cal Out
RX_IN
RX_IN
VDD
VSS
MODE
TWK_0
TX_IN
SCLK
SDI
SDO
LE
CAL
VDD
VSS
MODE
TWK_0
Serial Bus Control
SCLK
SDI
SDO
LE
Serial Bus Control
TX_IN
TWK_1
TWK_1
RX_OUT
RX_OUT
TX_OUT
TX_OUT
Figure 7 • DN Calibration
Figure 9 • Isolation
RX_IN
RX_IN
VSS
MODE
TWK_0
TX_IN
SCLK
SDI
SDO
LE
CAL
VDD
VSS
MODE
TWK_0
TWK_1
Serial Bus Control
VDD
Serial Bus Control
TX_IN
SCLK
SDI
SDO
LE
CAL
CAL
TWK_1
RX_OUT
TX_OUT
RX_OUT
TX_OUT
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PE19601
MPAC–Beamforming
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for PE19601
Parameter/Condition
Min
Max
Unit
Supply voltage, VDD
–0.3
3.5
V
Negative supply voltage, VSS
–3.5
0.3
V
Digital input voltage
–0.3
3.6
V
18
dBm
+150
°C
ESD voltage HBM(1), all pins
1000
V
ESD voltage CDM(2), all pins
500
V
RF input power, 50Ω
Storage temperature range
–55
Notes:
1) Human body model (MIL-STD 883 Method 3015).
2) Charged device model (JEDEC JESD22-C101).
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PE19601
MPAC–Beamforming
Recommended Operating Conditions
Table 2 lists the recommended operating conditions for the PE19601. Devices should not be operated outside
the recommended operating conditions listed below.
Table 2 • Recommended Operating Conditions for PE19601
Parameter
Min
Typ
Max
Unit
Supply voltage, VDD
3.14
3.3
3.46
V
Supply current, IDD
5
Negative supply voltage, VSS
–3.46
Negative supply current, ISS
Digital input high
2.1
–3.3
RF input power, 50Ω
Operating temperature range
–40
DOC-69095-5 – (09/2016)
–3.14
V
1
µA
0.7 × VDD
V
0.3 × VDD
Digital input low
µA
1.1
V
+17
dBm
+105
°C
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PE19601
MPAC–Beamforming
Electrical Specifications
Table 3 provides the PE19601 key electrical specifications at +25 °C, VDD = 3.3V, VSS = –3.3V, 10 GHz, unless
otherwise specified.
Table 3 • PE19601 Electrical Specifications
Parameter
Condition
Operating frequency
Min
Typ
8
Max
Unit
12
GHz
Insertion loss
Attenuation setting = 0, phase setting = 0
10
dB
Return loss
Attenuation setting = 0, phase setting = 0
13
dB
Input P0.1dB compression point(*)
17
Input IP3
dBm
44
dBm
Switching time
50% LE to 90% or 10% final RF value
120
ns
Reconfiguration time
50% LE to 90% or 10% final RF value
120
ns
Phase range
6 bit
10 bit
340
350
deg
deg
5
deg
2
1.5
deg
deg
8
5
deg
deg
Attenuation range
30
dB
Attenuation step
0.5
dB
Relative attenuation error RMS attenuation error with respect to the 64 attenuation states and at
(RMS value)
reference phase state
0.25
dB
Absolute attenuation
error
Measured at the reference phase state
0.8
dB
Isolation between TX_IN
and RX_OUT
TX nominal mode
55
dB
Isolation between TX_IN
and RX_OUT
RX nominal mode
55
dB
Phase step
Relative phase error
(RMS value)
RMS phase error with respect to the 64 phase states and at reference
attenuation state
6 bit
10 bit
Absolute phase error
Measured at the reference attenuation state
6 bit
10 bit
Note: * The input P0.1dB compression point is a linearity figure of merit. Refer to Table 2 for the operating RF input power (50Ω).
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PE19601
MPAC–Beamforming
Control Logic
Table 4–Table 10 provide the control logic truth tables for the PE19601. The MODE control pin is used to select
between 6-bit and 10-bit phase shifter mode of operation. The MODE pin should be set to the desired mode of
operation before setting the phase shifter via the SPI bus.
Serial Interface
The serial interface is a 22-bit serial-in register with a serial data output. The device has two modes of operation,
10-bit phase shifter mode and 6-bit phase shifter mode. The desired phase shifter mode is selected using the
MODE control pin. A logic LOW on the MODE pin sets the device to 6-bit phase shifter mode, while logic HIGH
sets the device to 10-bit mode.
In 10-bit mode the entire 22 bits of the serial register are used. In this configuration, the 22 bits comprise 10 bits
for phase setting, 6 bits for attenuation setting and 6 bits for I/O Path setting. In a 6-bit mode the first 4 bits
(MSBs) clocked in are not used. There are two options in 6-bit mode: the entire 22 bits can be loaded (using 22
clock cycles), with the 4 MSBs arbitrarily set; the 18 least significant bits can be loaded with 18 clock cycles.
The serial interface is controlled using three CMOS (3.3V logic) compatible signals: serial data in (SDI), clock
(CLK) and latch enable (LE). The SDI and CLK inputs allow data to be serially entered into the shift register.
Serial data is clocked in starting with the phase shifter MSB. The shift register must be loaded while LE is held
HIGH to prevent the internal register values from changing as data is entered. The LE input should then be
toggled LOW, latching the new data into the PE19601. The latching occurs on the falling edge of the LE. SDO
feeds the last entered data out as a new data is loaded. This would allow daisy chaining of devices, providing
the sent data string is lengthened to 22 bits times the number of PE19601 in the string. Once the data is present
within all devices a single LE applied would update all settings simultaneously. Phase shift, attenuation setting
and I/O Path truth tables are listed in Table 4, Table 5 and Table 6.
Tweak Input Settings
Tweak inputs TWK_0 and TWK_1 can be used to add phase increments to the phase shifter. When activated
they add a phase offset to the phase shifter extending its range, creating a new zero setting starting point. The
TWK bits create finer phase increments by accessing phase values otherwise not accessible. This offset can be
used either to extend the frequency range of the phase shifter or improve its accuracy by acting as fill-in bits.
The tweak inputs are independently controlled, and not part of the SDI logic inputs. The TWK bits can be hard
coded using a fixed voltage (logic HIGH or LOW). Logic HIGH activates each of the inputs. The inputs can be
used independently or in combination. In combination their phase offsets add together. The use of a phase
mapping look-up table is recommended to fully utilize the tweak inputs.
Mode Control Pin
The Mode Control pin (pad number 9) is active as soon as asserted and is independent of the SPI control word.
Originally envisaged as a strapped option: logic LOW = 6-bit phase mode, logic HIGH = 10-bit phase mode. It
can be changed to the alternate state while there is no traffic on the SPI bus. The format of the SPI control word
has to be altered when the mode control pin is toggled, as shown in Figure 12. The word length changes
between 10-bit mode (22 bits) and 6-bit mode (18 bits).
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PE19601
MPAC–Beamforming
Table 4 • SPI Addressing for 6-bit Phase Shifter
Table 5 • SPI Addressing for 10-bit Phase Shifter
Bit Number
Description
Bit Number
Description
(MSB) B17
Phase shifter B5
(MSB) B21
Phase shifter B9
B16
Phase shifter B4
B20
Phase shifter B8
B15
Phase shifter B3
B19
Phase shifter B7
B14
Phase shifter B2
B18
Phase shifter B6
B13
Phase shifter B1
B17
Phase shifter B5
B12
Phase shifter B0
B16
Phase shifter B4
B11
DSA B5
B15
Phase shifter B3
B10
DSA B4
B14
Phase shifter B2
B9
DSA B3
B13
Phase shifter B1
B8
DSA B2
B12
Phase shifter B0
B7
DSA B1
B11
DSA B5
B6
DSA B0
B10
DSA B4
B5
I/O path B5
B9
DSA B3
B4
I/O path B4
B8
DSA B2
B3
I/O path B3
B7
DSA B1
B2
I/O path B2
B6
DSA B0
B1
I/O path B1
B5
I/O path B5
(LSB) B0
I/O path B0
B4
I/O path B4
B3
I/O path B3
B2
I/O path B2
B1
I/O path B1
(LSB) B0
I/O path B0
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PE19601
MPAC–Beamforming
Table 6 • DSA Truth Table
B5
B4
B3
B2
B1
B0
16 dB
8 dB
4 dB
2 dB
1 dB
0.5 dB
31.5 dB
1
1
1
1
1
1
31 dB
1
1
1
1
1
0
16 dB
1
0
0
0
0
0
8 dB
0
1
0
0
0
0
4 dB
0
0
1
0
0
0
2 dB
0
0
0
1
0
0
1 dB
0
0
0
0
1
0
0.5 dB
0
0
0
0
0
1
0 dB
0
0
0
0
0
0
Operating Mode
B5
B4
B3
B2
B1
B0
TX nominal/TX only
0
1
1
0
0
1
RX nominal/RX only
1
1
0
1
0
0
TX calibration
0
1
0
1
1
1
RX calibration
1
0
1
0
0
0
DN calibration
0
0
0
0
1
1
Isolation
1
1
1
0
1
0
CAL in
1
1
0
1
1
0
CAL out
0
0
1
0
0
1
Attenuation Value
Table 7 • I/O Path Truth Table
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PE19601
MPAC–Beamforming
Table 8 • 6-bit Mode Phase Shifter Truth Table
Target Phase
B5
B4
B3
B2
B1
B0
Degrees
180
90
45
22.5
11.25
5.625
354.375
1
1
1
1
1
1
348.75
1
1
1
1
1
0
180
1
0
0
0
0
0
90
0
1
0
0
0
0
45
0
0
1
0
0
0
22.5
0
0
0
1
0
0
11.25
0
0
0
0
1
0
5.625
0
0
0
0
0
1
0
0
0
0
0
0
0
Table 9 • MODE Pin Truth Table
MODE Pin
Phase Shifter Mode
L
6-bit phase shifter
H
10-bit phase shifter
Table 10 • TWK Truth Table
TWK_1
TWK_2
TWK_0 and TWK_1
Phase State
L
L
TWK bits OFF
L
H
TWK_0 ON
H
L
TWK_1 ON
H
H
TWK_0 and TWK_1 ON
TWK_0 and TWK_1 control bits are active as soon as
asserted. TWK_0 and TWK_1 each introduce a small
phase shift which can be used to extend the
frequency range of the phase shifter.
Page 10
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PE19601
MPAC–Beamforming
The diagram in Figure 10 is a simplified functional block diagram of the phase shifter in 10-bit mode. 10-bit
mode does not produce 10-bit resolution; i.e., it does not produce 360 degrees divided by 1024 resolution. The
mode is intended to provide fill-in bits to deliver finer phase resolution than a 6-bit phase shifter. In 10-bit mode,
a look-up table should be used to map the desired phase to the appropriate phase shifter setting. The phase
steps in Figure 10 are indications only; over the frequency range of 8–12 GHz, the absolute phase values may
deviate by several degrees from the indications. These deviations are consistent and repeatable. Very low RMS
phase error results can be achieved by employing a look-up table to take advantage of the improved resolution.
Figure 10 • 10-bit Phase Shifter Operation
CLK DATA
EN
MODE
5.625°
5.625°
5.625°
22.5°
22.5°
22.5°
90°
54°
180°
8°
Serial Controller
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
PS1
PS2
PS3
PS4
The 10-bit phase shifter is made up of 3x 5.625° phase shifts, 3x 22.5° phase shifts, a 90° phase shift, a 180°
phase shift and two fill-in phase shifts of approximately 52° and 8°. As each of these phase shifts is activated it
adds to the other activated blocks.
For example, if an 11.25° phase shift is required internal logic activates two of the 5.625° phase shifts (B0, B1,
B2). Equally, if a 45° phase shift is required two of the 22.5° phase shift blocks (B3, B4, B5) are activated. B7
and B9 provide intermediate phase offsets to create intermediate phase steps with finer resolution than 5.625°.
They can be considered as fill-in or dithering bits that offset the phase. Note: Figure 10 is a simplified block
diagram and exact 5.625° increments are not expected when bits B0–B9 are added. The 10-bit phase shifter
mode is intended to operate with a phase look-up table. The look-up table orders the phase in ascending phase
value and selects the index for the desired phase value.
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PE19601
MPAC–Beamforming
A typical plot for the 10-bit phase shifter can be seen in Figure 11. Note: Although values of Setting Value from
0 to 511 appear the same as the values from 512 to 1023, they include a small offset and contain different phase
values.
Figure 11 • 10-bit Phase Shifter Phase vs Setting(*)
9.6GHz
400
350
Phase (deg)
300
250
200
150
100
50
0
0
200
400
600
Setting Value
800
1000
1200
Note: * Please contact Peregrine Semiconductor for more detail regarding look-up table implementation.
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PE19601
MPAC–Beamforming
Figure 12 • SPI Streams 6-bit Mode 0 and 10-bit Mode 1
First bit in
(MSB)
Phase Shifter
I/O
DSA
Don’t Care
(LSB)
Mode 1 10b phase shift. 22 bit Clk
SPI data
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b5
b4
b3
b2
b1
b0
b5
b4
b3
b2
b1
b0
b3
b2
b1
b0
b5
b4
b3
b2
b1
b0
b5
b4
b3
b2
b1
b0
b3
b2
b1
b0
b5
b4
b3
b2
b1
b0
b5
b4
b3
b2
b1
b0
SPI Clock
SPI Enable
Mode 0 6b phase shift 18 bit Clk
SPI data
b5
b4
SPI Clock
SPI Enable
Mode 0 6b phase shift 22 bit Clk
SPI data
b5
b4
SPI Clock
SPI Enable
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PE19601
MPAC–Beamforming
Typical Performance Data
Figure 13–Figure 21 show the typical performance data at +25 °C, VDD = 3.3V, VSS = –3.3V, 10 GHz, unless
otherwise specified.
Figure 13 • Calibrated RMS Phase Error vs Frequency
Rx mode
RMS Phase Error (deg)
6
5
4
3
2
1
0
8
8.5
9
9.5
10
10.5
Frequency (GHz)
11
11.5
12
300
350
400
Figure 14 • 10 GHz Calibrated Phase vs Setting Value
Rx mode
400
350
Phase (deg)
300
250
200
150
100
50
0
0
50
100
150
200
250
Phase Setting (deg)
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PE19601
MPAC–Beamforming
Figure 15 • Calibrated RMS Attenuation Error vs Frequency
Rx mode
2
RMS Attenuation Error (dB)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
8
8.5
9
9.5
10
10.5
11
11.5
12
Frequency (GHz)
Figure 16 • 10 GHz Calibrated Attenuation vs Setting Value
Rx mode
35
Attenuation (dB)
30
25
20
15
10
5
0
0
5
10
15
20
Attenuation Setting (dB)
DOC-69095-5 – (09/2016)
25
30
35
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PE19601
MPAC–Beamforming
Figure 17 • RX Mode Output Return Loss
0dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31dB
0
-5
Return Loss (dB)
-10
-15
-20
-25
-30
-35
-40
-45
8
8.5
9
9.5
10
10.5
Frequency (GHz)
11
11.5
12
Figure 18 • RX Mode Input Return Loss
0dB
0.5dB
1dB
2dB
4dB
8dB
16dB
31dB
0
-5
Return Loss (dB)
-10
-15
-20
-25
-30
-35
-40
-45
8
8.5
9
9.5
10
10.5
Frequency (GHz)
Page 16
11
11.5
12
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PE19601
MPAC–Beamforming
Figure 19 • Input IP3 vs Attenuation Setting Value
Rx mode
54
Input IP3 (dBm)
53
52
51
50
49
48
47
0
5
10
15
20
DSA Setting (dB)
25
30
35
Figure 20 • Input IP3 vs Phase Shifter Setting Value (10-bit mode)
Rx mode, 10 bit phase shifter mode
54
Input IP3 (dBm)
53
52
51
50
49
48
47
0
200
400
600
800
Phase shifter setting (decimal value)
DOC-69095-5 – (09/2016)
1000
1200
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PE19601
MPAC–Beamforming
Figure 21 • RMS Phase Error vs Frequency, with Single Frequency Calibration (8.5, 9.5, 10.5 and 11.5 GHz)
10 bit mode, 1GHz LUT
6
RMS Phase Error (deg)
5
4
3
2
1
0
8
9
10
11
12
Frequency (GHz)
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PE19601
MPAC–Beamforming
Evaluation Kit
The PE19601 evaluation kit (EVK) includes hardware required to control and evaluate the functionality of the
MPAC. The MPAC evaluation software can be downloaded at www.psemi.com and required a PC running
Windows® operating system to control the USB interface board. Refer to the PE19601 Evaluation Kit User’s
Manual for more information.
Figure 22 • Evaluation Kit Layout for PE19601
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PE19601
MPAC–Beamforming
Pad Information
This section provides pad information for the PE19601. Figure 23 shows the pad configuration of this device.
Table 11 provides a description for each pad.
41
42
31
40
43
30
45
28
44
46
27
47
48
51
52
53
56
57
58
59
60
61
62
36 37
5
6
7
35
y
2600 µm (drawn)
38
39
49
50
x
55
4
3
54
2
1
Figure 23 • Pad Configuration (Top View)(1)(2)
34
32
29
26
25
23
21
19
17
16
15
14
12
13
11
10
9
33
24
22
20
18
8
origin
4650 µm (drawn)
Notes:
1) Drawings are not drawn to scale.
2) Singulated die size shown, pad side up.
Table 11 • Pad Descriptions for PE19601
Pad
No.
Pad Name
1
GND_RF(1)
Ground for RF section
2
GND_RF(1)
Ground for RF section
3
GND_RF(1)
Ground for RF section
4
GND_RF(1)
Ground for RF section
5
GND_RF(1)
Ground for RF section
6
GND_RF(1)
Ground for RF section
7
GND_RF(1)
Ground for RF section
8
GND_RF(1)
Ground for RF section
Description
Table 11 • Pad Descriptions for PE19601 (Cont.)
Pad
No.
Pad Name
9
RX_IN(2)
10
GND_RF(1)
Ground for RF section
11
GND_RF(1)
Ground for RF section
12
GND_RF(1)
Ground for RF section
13
GND_RF(1)
Ground for RF section
14
GND_RF(1)
Ground for RF section
15
GND_RF(1)
Ground for RF section
16
GND_RF(1)
Ground for RF section
17
VSS
Page 20
Description
Receive input port
Negative supply voltage
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PE19601
MPAC–Beamforming
Table 11 • Pad Descriptions for PE19601 (Cont.)
Pad
No.
Pad Name
18
MODE
19
VDD
Positive supply voltage
20
DATA_OUT
Serial buffered data out
21
EN
22
TWK_0(3)
23
DATA
Table 11 • Pad Descriptions for PE19601 (Cont.)
Pad
No.
Pad Name
45
GND_RF(1)
Ground for RF section
46
GND_RF(1)
Ground for RF section
47
GND_RF(1)
Ground for RF section
Serial interface latch enable
48
GND_RF(1)
Ground for RF section
Phase tweak bit 0. Introduces a
small fixed phase offset
49
NC
Not connected
50
NC
Not connected
51
GND_RF(1)
52
CAL(2)
53
GND_RF(1)
54
NC
Not connected
55
NC
Not connected
56
GND_RF(1)
Ground for RF section
57
GND_RF(1)
Ground for RF section
58
GND_RF(1)
Ground for RF section
59
GND_RF(1)
Ground for RF section
60
GND_RF(1)
Ground for RF section
61
GND_RF(1)
Ground for RF section
62
TX_IN(2)
Description
Select between 6- and 10-bit phase
shifter mode
Serial interface data input
Phase tweak bit 1. Introduces a
small fixed phase offset
24
TWK_1(3)
25
CLK
26
GND_RF(1)
Ground for RF section
27
GND_RF(1)
Ground for RF section
28
GND_RF(1)
Ground for RF section
29
GND_RF(1)
Ground for RF section
30
GND_RF(1)
Ground for RF section
31
GND_RF(1)
Ground for RF section
32
GND_RF(1)
Ground for RF section
33
TX_OUT(2)
Transmit output port
34
GND_RF(1)
Ground for RF section
35
GND_RF(1)
Ground for RF section
36
GND_RF(1)
Ground for RF section
37
GND_RF(1)
Ground for RF section
38
GND_RF(1)
Ground for RF section
39
GND_RF(1)
Ground for RF section
40
GND_RF(1)
Ground for RF section
41
GND_RF(1)
Ground for RF section
42
RX_OUT(2)
Receive output port
43
GND_RF(1)
Ground for RF section
44
GND_RF(1)
Ground for RF section
Serial interface clock input
Description
Ground for RF section
Calibration port, used for calibrating
system
Ground for RF section
Transmit input port
Notes:
1) Grounds for RF section should have short bond wires to maximize
part performance. Long bond wires will result in reduces frequency
range and reduced DSA + phase shifter range.
2) RX_IN, RX_OUT, TX_IN, TX_OUT and CAL are bi-directional.
3) TWK_0 and TWK_1 can be used to apply a small fixed offset to
optimize the phase range for a chosen frequency range. They can
be parallel controlled using a direct write mode of operation or
they can be permanently strapped to a fixed voltage. Both pins
have internal pull-downs so will be default low. The pins operate
under 3.3V logic control.
DOC-69095-5 – (09/2016)
Page 21
www.psemi.com
PE19601
MPAC–Beamforming
Die Mechanical Specifications
This section provides the die mechanical specification and pad coordinates for the PE19601.
Table 12 • Mechanical Specification for PE19601
Parameter
Min
Typ
Die size, singulated (x,y)
Max
Unit
2600 × 4650
Wafer thickness
180
µm
200
220
µm
Note: * Peregrine’s guarantee of our bump quality and reliability is based on the use of underfill.
Table 13 • Pad Coordinates for PE19601(*)
Pad
No.
Pad
Name
Pad Center(*)
(µm)
Table 13 • Pad Coordinates for PE19601(*) (Cont.)
Pad Opening
Size (µm)
X
Y
X
Y
Pad
No.
Pad
Name
Pad Center(*)
(µm)
Pad Opening
Size (µm)
X
Y
X
Y
1
GND_RF
–2183.9
1117.6
180
180
23
DATA
180
–1147.6
120
80
2
GND_RF
–2213.9
907.6
140
120
24
TWK_1
270
–697.6
120
80
3
GND_RF
–2213.9
647.6
280
120
25
CLK
360
–1147.6
120
80
4
GND_RF
–2213.9
337.6
280
120
26
GND_RF
653
–1147.6
120
290
5
GND_RF
–2213.9
97.6
140
120
27
GND_RF
967.9
–1147.6
120
210
6
GND_RF
–2213.9
–97.6
140
120
28
GND_RF
1245
–1147.6
120
210
7
GND_RF
–2213.9
–337.6
280
120
29
GND_RF
1583.9
–1147.6
120
140
8
GND_RF
–2213.9
–647.6
280
120
30
GND_RF
1763.9
–1117.6
180
180
9
RX_IN
–2213.9
–907.6
140
120
31
GND_RF
1973.9
–1117.6
180
140
10
GND_RF
–2183.9
–1117.6
180
180
32
GND_RF
2183.9
–1117.6
180
180
11
GND_RF
–1973.9
–1117.6
180
140
33
TX_OUT
2213.9
–907.6
140
120
12
GND_RF
–1763.9
–1117.6
180
180
34
GND_RF
2213.9
–647.6
280
120
13
GND_RF
–1583.9
–1147.6
120
140
35
GND_RF
2213.9
–337.6
280
120
14
GND_RF
–1303.6
–1147.6
120
280
36
GND_RF
2213.9
–97.6
140
120
15
GND_RF
–967.9
–1147.6
120
210
37
GND_RF
2213.9
97.6
140
120
16
GND_RF
–653
–1147.6
120
290
38
GND_RF
2213.9
337.6
280
120
17
VSS
–360
–1147.6
120
80
39
GND_RF
2213.9
647.6
280
120
18
MODE
–270
–697.6
120
80
40
GND_RF
2213.9
907.6
140
120
19
VDD
–180
–1147.6
120
80
41
GND_RF
2183.9
1117.6
180
180
20
DATA_OUT
–90
-697.6
120
80
42
RX_OUT
1973.9
1117.6
180
140
21
EN
0
–1147.6
120
80
43
GND_RF
1763.9
1117.6
180
180
22
TWK_0
90
–697.6
120
80
44
GND_RF
1535.5
1147.6
120
236.8
Page 22
DOC-69095-5 – (09/2016)
www.psemi.com
PE19601
MPAC–Beamforming
Table 13 • Pad Coordinates for PE19601(*) (Cont.)
Pad
No.
Pad
Name
Pad Center(*)
(µm)
Pad Opening
Size (µm)
X
Y
X
Y
45
GND_RF
1245
1147.6
120
210
46
GND_RF
693
1147.6
120
210
47
GND_RF
967.9
1147.6
120
210
48
GND_RF
417.8
1147.6
120
210
49
NC
240
667.6
120
80
50
NC
270
267.6
120
80
51
GND_RF
195
1147.6
120
150
52
CAL
0
1147.6
120
140
53
GND_RF
–195
1147.6
120
150
54
NC
–240
667.6
120
80
55
NC
–270
267.6
120
80
56
GND_RF
–416
1147.6
120
210
57
GND_RF
–693
1147.6
120
210
58
GND_RF
–888
1147.6
120
140
59
GND_RF
–1186.4
1147.6
120
280
60
GND_RF
–1535.5
1147.6
120
236.8
61
GND_RF
–1763.9
1117.6
180
180
62
TX_IN
–1973.9
1117.6
180
140
Note: * All pad locations originate from the die center and refer to the
center of the pad.
DOC-69095-5 – (09/2016)
Page 23
www.psemi.com
PE19601
MPAC–Beamforming
Ordering Information
Table 14 lists the available ordering codes for the PE19601 as well as available shipping methods.
Table 14 • Order Codes for PE19601
Order Codes
Description
Packaging
Shipping Method
PE19601A–G
PE19601 Die
Waffle Pack
Waffle Pack
EK19601–01
PE19601 Evaluation kit
Evaluation kit
1/box
Document Categories
Advance Information
Product Brief
The product is in a formative or design stage. The datasheet contains
design target specifications for product development. Specifications
and features may change in any manner without notice.
This document contains a shortened version of the datasheet. For the
full datasheet, contact [email protected].
Preliminary Specification
Not Recommended for New Designs (NRND)
This product is in production but is not recommended for new designs.
The datasheet contains preliminary data. Additional data may be added
at a later date. Peregrine reserves the right to change specifications at
any time without notice in order to supply the best possible product.
Product Specification
The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the
intended changes by issuing a CNF (Customer Notification Form).
End of Life (EOL)
This product is currently going through the EOL process. It has a
specific last-time buy date.
Obsolete
This product is discontinued. Orders are no longer accepted for this
product.
Sales Contact
For additional information, contact Sales at [email protected].
Disclaimers
The information in this document is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be
entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to
support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death
might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
Patent Statement
Peregrine products are protected under one or more of the following U.S. patents: patents.psemi.com
Copyright and Trademark
©2015–2016, Peregrine Semiconductor Corporation. All rights reserved. The Peregrine name, logo, UTSi and UltraCMOS are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp.
Product Specification
www.psemi.com
DOC-69095-5 – (09/2016)