ADC Resolution: Myth and Reality
Renesas Electronics America Inc.
© 2012 Renesas Electronics America Inc. All rights reserved.
Renesas Technology & Solution Portfolio
2
© 2012 Renesas Electronics America Inc. All rights reserved.
Microcontroller and Microprocessor Line-up
2010
2012
1200 DMIPS, Superscalar
32-bit
 Automotive & Industrial, 65nm
 600µA/MHz, 1.5µA standby
1200 DMIPS, Performance
 Automotive, 40nm
 500µA/MHz, 35µA deep standby
500 DMIPS, Low Power
 Automotive & Industrial, 90nm
 600µA/MHz, 1.5µA standby
165 DMIPS, FPU, DSC
 Industrial, 40nm
 200µA/MHz, 0.3µA deep standby
165 DMIPS, FPU, DSC
 Industrial, 90nm
 200µA/MHz, 1.6µA deep standby
8/16-bit
25 DMIPS, Low Power
 Industrial, 90nm
 1mA/MHz, 100µA standby
 Industrial & Automotive, 150nm
 190µA/MHz, 0.3µA standby
44 DMIPS, True Low Power
10 DMIPS, Capacitive Touch
 Industrial & Automotive, 130nm
 144µA/MHz, 0.2µA standby
 Industrial
Automotive, 130nm
Wide
Format&LCDs
 350µA/MHz, 1µA standby
3
Embedded Security, ASSP
© 2012 Renesas Electronics America Inc. All rights reserved.
‘Enabling The Smart Society’
 Collecting, analyzing and transmitting real-world signals is a
major focus of the smart society. Real-world signals are
analog, so converting these signals to digital is a key focus
for the smart
 Understanding the specifications and hidden errors in ADC
circuits will enable designs that meet the intended
specifications
4
© 2012 Renesas Electronics America Inc. All rights reserved.
Agenda
 What does the “resolution” spec really mean
 Some standard converters and resolution
 DC accuracy specifications
 Review offset, gain, DNL and INL errors
 How the ADC is tested
 What those errors don’t tell you
 AC specifications
 SNR
 ENOB
 System errors and resolution requirements
 ADC required accuracy
 Reference errors
 Source impedance errors
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© 2012 Renesas Electronics America Inc. All rights reserved.
Resolution
 What does the term resolution mean to you?
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Successive Approximation (SAR) ADC
ADC Register
Vref
DAC (R2R Ladder)
AVss
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Comparator
Input Analog
Mux
7
DC Specs primarily define this
section of ADC performance
Sample and
Hold Circuit
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Slope Converter
 Measure value R
– Thermistor or sensor
Vcc
CPU
R
Start Conversion
Started
Stopped
 Operation
L
GPIO
Timer
– Stopped
Enable
• GPIO = L
• Timer stopped
Vref
– Begin conversion
Clock
• GPIO = Hi-Z
• Timer started
L
H
• Comp out = H
– Conversion ends
• Vc > Vref
• Comp out = L
• Timer stops
 Timer value is proportional to RC time constant
 Resolution?
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8
Delta Sigma Converter
5V
0V
+V
Vin
4V
∑
∫
H
H
Ref
D
CK
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Digital
Filter
Result
Register
Delta Sigma Converter
Vin
∑
∫
Ref
D
Digital
Filter
Result
Register
CK
 Oversampling frequency (flip flop clock rate, e.g. RX21A 3.125MHz)
 Minimum Conversion time – rate the result register is updated
(81.92 uS or 12.2 kHz on RX21A )
– This is based on the decimation factor of the digital filter
– Some converters allow reducing decimation factor
• Faster conversion
• Lower resolution
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© 2012 Renesas Electronics America Inc. All rights reserved.
Oversampling
 Oversampling can increase resolution of ADC
ADC
Transition
Voltages
03
02
01
S1
x
S1
x
S2
x
S2
x
S3
x
S3
x
S4
x
S4
x
ADC Input
Voltage
00
Result will be 04 when samples are added
Result will still be 04 when samples are added if no noise
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Oversampling
 How noise helps oversampling
03
x
ADC
Transition
Voltages
S3
x
S1
02
S2
x
01
ADC Input
Voltage
with noise
00
Result is now 06
12
x
S4
ADC Input
Voltage
© 2012 Renesas Electronics America Inc. All rights reserved.
Oversampling
ADC
Transition
Voltages
03
x
02
S3
x
S1
S2
x
01
x
S4
ADC Input
Voltage
with noise
00
Result is now 04
 Oversample 2X results in ½ bit increase resolution
 To increase resolution by n bits
– Oversample 4n and decimate 2n
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ADC Input
Voltage
© 2012 Renesas Electronics America Inc. All rights reserved.
ADC Accuracy Specifications
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© 2012 Renesas Electronics America Inc. All rights reserved.
An Explanation of DC Specifications
 DC accuracy specifications
 These specifications look at DC or very low frequency input
errors
Full Scale
Non-Linearity
Error
Ideal Curve
ADC
Counts
Corrected
Curve
Absolute
Error
Real Curve
0V
Vfull Scale
Offset Error
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Input Voltage
AC Specifications
 DC testing does not describe dynamic characteristic
 Sample and hold errors
 AC noise errors
 Comparator hysteresis
 AC testing method
 Input sine wave to ADC input
 Perform FFT
 Measure SNDR, SNR and/or Spurious Free Dynamic Range
 SNR, SNDR – Ratio of RMS value to noise
 SNDR (SINAD) includes harmonics or distortion
 SFDR - ratio of the RMS value of input sine wave to the RMS
value of the largest spur
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SNDR Results
(PGA x1)
FFT plot
200
180
PGA
Gain
SNDR
x1
86.58dB
x2
86.37dB
x4
81.38dB
x8
78.37dB
x16
74.71dB
x32
71.49dB
x64
64.74dB
160
Level[dB]
140
120
100
80
60
40
20
0
1
17Hz
10
100
Frequency[Hz]
1.71kHz
1000
SNDR
calculation range
Why does SNDR go down as PGA gain goes up
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10000
Interpreting
 We can calculate the equivalent perfect ADC from equation
ENOB = (SNDR -1.76)/ 6.02
 The 6.02 term in the divisor converts decibels (a log10 representation)
to bits (a log2 representation).
 The 1.76 term comes from quantization error in an ideal ADC
 86 dB would then have the equivalent resolution of a 14 bit perfect ADC
ENOB = log2 [full-scale input voltage range/(ADC RMS noise × √12)]
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© 2012 Renesas Electronics America Inc. All rights reserved.
Interpreting Specification
 AC testing does not provide linearity data
 DNL and INL do affect SNDR
 DNL affects SNR
 INL affect THD
 Oversampling is still valid and reduces the average noise if
Gaussian distribution
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Example
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Understanding the Errors an Example
 Requirements
 Input = 0V – 2.0V
 +/- .25% of full scale accuracy (+/- 5 mV)
 Vref = 3.0V
Vdd
Vdd
 ADC range and resolution
 LSB must be < 10 mV

– 0.25% * 2.0V = 10 mV
– 10 mV / 3.0V = 1/300
– 9 bit ADC required
AVREFP
3V
AVREFM
MCU
A
ADCin
0-2 V
Vss
 Decreasing Vref to 2.5V
– 10 mV / 2.5V = 1/250
– 8 bit ADC meets resolution requirement
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© 2012 Renesas Electronics America Inc. All rights reserved.
A
D
Understanding the Errors an Example
 Assume Vref = 2.56V, 8 Bit ADC (10 mV per step)
Output
Code
Indicated Voltage (mV)
40 mV
04
03
30 mV
02
20 mV
01
10 mV
00
½ LSB Offset
0
22
5
10 15 20
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30
0
40 Actual Voltage (mV)
Understanding the Errors an Example
 Can we use a 10 bit ADC with +/- 2 bits INL
 Each LSB error = 2.5mV (2.56V / 1024)
 Error for 2 LSB = 5 mV
 5 mV/2.0V = 0.25%
 But there is still an additional ½ LSB quantization error
 6.25 mV total error = 0.31%
 What about 1 bit of error
 Worst case ADC error is 2.5 mV + 1.25 mV
 0.1875% error
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© 2012 Renesas Electronics America Inc. All rights reserved.
Understanding the Errors an Example
 Assume Vref = 2.56V, 10 Bit ADC (2.5 mV per step)
Indicated Voltage (mV)
10 mV
1.251 mV code 01
Output
Code
04
03
With 2 LSB error
02
5 mV
01
2.5 mV
00
0
0 1.2 5
24
7.5 mV
2.5
© 2012 Renesas Electronics America Inc. All rights reserved.
5
7.5
10
Actual Voltage (mV)
When is a 16 Bit ADC Not 16 Bit?
Specification
TUE - Unadjusted
DNL
INL
Efs -Full Scale
Eq - Quantization
ENOB
SINAD
THD
25
Condtion
12 Bit Mode
12 Bit Mode
12 Bit Mode
12 Bit Mode
16 Bit Mode
≤ 13 Bits
16 bit single
ended mode
avg = 32
avg = 4
See ENOB
16 bit single
ended mode
© 2012 Renesas Electronics America Inc. All rights reserved.
Min
Typ
-
12.2
11.4
-
Max
±4
± 0.7
± 1.0
±4
-1 to 0
Units
± 6.8
LSB
-1.1 to +1.9 LSB
-2.7 to +1.9 LSB
± 6.8
LSB
± 0.5
13.9
13.1
6.02 X ENOB + 1.76
-85
-
LSB
bits
bits
dB
dB
System Considerations
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© 2012 Renesas Electronics America Inc. All rights reserved.
Errors That Are Sometimes Forgotten
 System noise
 Clocks
 IO port toggles
 Sensor and reference error
 Accuracy vs. drift
 Temperature , age and voltage effects
 Calibration
Vdd
Vdd
AVREFP
Vref
 Input system effects
AVREFM
MCU
A
ADCin
T
GPIO
Vss
A
D
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© 2012 Renesas Electronics America Inc. All rights reserved.
Check Accuracy Conditions
 Specification may expect:
 MCU in a sleep mode
 No IO toggling
 Specified ADC clock speed
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© 2012 Renesas Electronics America Inc. All rights reserved.
What is the ADC Reading for the Circuit Below?
+Vref
1. Depends on Vref
2. Depends on Vcc
3. Need to know resistor
values
4. 512
5. Ask the HW engineer
Vcc
Vref
R1
R2
R1=R2
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© 2012 Renesas Electronics America Inc. All rights reserved.
+V
MCU
10 bit AD
Input
Ratiometric and Non-Ratiometric Conversions
+V
+V
+Vref
Vcc
Vref
+Vref
Vcc
Vref
Vcc
Vref
Vcc
Vref
MCU
MCU
MCU
MCU
AD Input
AD Input
AD Input
AD Input
a) ratiometric
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+V
+V
b) ratiometric
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c) non-ratiometric
d) non-ratiometric
Understanding Reference Errors
 Vref is a power supply pin
+V
 Vref powers R2R ladder
Zt
Vcc
Vref
Rt
T
MCU
Vm
AD Input
Rref
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 Treat as power supply pin
– Typically <100 uA
– Bypass properly
 3 mV ripple = 1 LSB error on
10bit 3V ADC
Understanding Ratiometric Reference Errors
 Vcc ≠ Vref
+V
 Sensor biased from Vref
Loads
 Vref can pick up noise
Vcc
Vref
C2
MCU
Rt
T
AD Input
Rref
C3
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© 2012 Renesas Electronics America Inc. All rights reserved.
C1
 Bypassing ADC input can help
Reference Errors – External References
 Consider design example
Vcc
 Measure 0 – 2V with < 0.5% FS error
 2.5V reference
 This measurement is non-ratiometric
 Assume 10 bit ADC with 1 LSB INL used
 Previously calculate 0.1875% error from ADC
 Can I use a 2.56V 0.5% accurate reference diode?
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© 2012 Renesas Electronics America Inc. All rights reserved.
Vref
MCU
AD In
Reference Errors – Reference Accuracy
 Can use 0.5% accuracy diode?
 If no calibration – no
 If calibrate is performed?
– Depends on drift and temp range
 LM4040 0.5% accuracy w/ 100 ppm/C
 20 ppm typical
 If operating range is 0-50C max drift
– 100 ppm/C * 25C = .25% drift
– Total error still only 0.4375%
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© 2012 Renesas Electronics America Inc. All rights reserved.
Source Resistance Errors
Vref
10k
Rs
ADC Input Ckt Equivalent
Req
10k
To AD
Converter
Block
S1
Ceq
For M16C/62P
Req = 7.8k
Ceq = 1.5 pF
S1 closed for 3 fAD cycles
RC time constant of source resistance and sampling cap can
cause error
35
© 2012 Renesas Electronics America Inc. All rights reserved.
Source Resistance Limitation (An Intuitive Approach)
 Desired charge error much less than
1/1024 (0.1%)
 Allow 10 time constants (0.005%)
 Sampling occurs for 300 nSec
 (3 cycles of 10 MHz AD clock)
 10 time constants = 300 nSec 1 TC = 30 nSec

C = 1.5 pF so Rtotal (Rs + Req) must be 20Kohm or less
 (300 nSec/1.5 pF)
 Rsource can not be greater than 12.2 K ohms
 Equivalent resistance of the AD circuit is 7.8K
 (Strict analysis indicated 13.8 kOhm)
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© 2012 Renesas Electronics America Inc. All rights reserved.
Source Resistance Errors
 What can we do?
 Decrease Rs
Vref
– Could add buffer
– Buffer adds offset
 Increase sampling time
 Add capacitor
40k
30k
To AD
Converter
Block
Rs
Req
S1
C1
Ceq
For M16C/62P
Req = 7.8k
Ceq = 1.5 pF
S1 closed for 3 fAD cycles
37
© 2012 Renesas Electronics America Inc. All rights reserved.
Summary
 What does the “resolution” spec really mean
 Some standard converters and resolution
 DC accuracy specifications
 Review offset, gain, DNL and INL errors
 How the ADC is tested
 What those errors don’t tell you
 AC specifications
 SNR
 THD
 ENOB
 How does this affect my application
 Errors and considerations
38
© 2012 Renesas Electronics America Inc. All rights reserved.
Questions?
39
© 2012 Renesas Electronics America Inc. All rights reserved.
‘Enabling The Smart Society’
 Collecting, analyzing and transmitting real-world signals is a
major focus of the smart society. Real-world signals are
analog, so converting these signals to digital is a key focus
for the smart
 Understanding the specifications of an ADC and the effects
of system device selections will help the information
delivered by the smart society provide an accurate picture of
the world
40
© 2012 Renesas Electronics America Inc. All rights reserved.
Renesas Electronics America Inc.
© 2012 Renesas Electronics America Inc. All rights reserved.
Also Check the Conditions
 K10P100M100SF2 Data Sheet Rev 6
42
© 2012 Renesas Electronics America Inc. All rights reserved.
Delta Sigma Converter
47
4
© 2012 Renesas Electronics America Inc. All rights reserved.
Effect of Adding Capacitor to Input Pin
Adding capacitor creates a low pass filter
fc
To AD Converter
Block
Rs
Req
C1
Gain
Freq
fc = 1/2πRC
20k Rs and .0015 uF = 5.3 kHz corner
48
4
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S1
Ceq
Notes
 Below a certain frequency, THD is only dependent on the
overall INL of the converter
 For an example, if the converter depicted in Figure 2 is
being used to digitize a signal which can slew at an
equivalent rate to that of a 10kHz signal, then the "THD"
performance of the converter will be roughly -86dB. This
figure means that the harmonic distortion is 86dB below the
converter's full-scale range. Since the full-scale range of this
16-bit converter is ±32,768, then the harmonic distortion
represents roughly ±1.6 LSB of error.
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© 2012 Renesas Electronics America Inc. All rights reserved.