MULTIBOOT AND
SPI FLASH MEMORY
IFIC (CSIC – Universidad de Valencia)
25 Sept. 2013
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MULTIBOOT:
Status
• VHDL reconfiguration
• Integrate as Wishbone slave
• Create libraries and driver
•Slow control using embedded software
• Write the multiboot images in flash memory using LM32
2
SPI INTERFACE: LM32 Wishbone slave
Tx_data2buf
Tx Stream
Select
Tx_pkt2mac
Flags
TxPort 1
TxPort 2
TDC0
Fifo
TDC
30
S
Management
& Control
ADC
Fifo
S
31 PMTs
Time Slice Start
RxPort_m
Management
& Config.
Pause Frame
TxPacket
Buffer
32KB
RxPort 1
RxPort 2
Fifo
Management
& Control
Multiboot
TxPort_m
S
M
S
M M
Management
& Control
Nano
Beacon
M
S WB Crossbar
M
M
(1x8)
M
M M
M
Xilinx
Kintex-7
MEM S
Data
Control
Wishbone bus
M
M WB Crossbar
(3x2)
M
S
S
M
2nd CPU
LM32
UTC time & Clock (PPS, 125 MHz)
Point to Point interconnection
S
Hydrophone
Flags
31 TDCs
State Machine
Rx_mac2buf
RxPacket
Buffer
64KB
Rx_buf2data
Rx Stream
Select
IP/UDP Packet Buffer
Stream Selector (IPMUX)
Start Time Slice UTC &
Offset counter since
S
SPI
UART
SPI
Flash
Debug
RS232
S
I2C
Temp
S
I2C
Debug
LEDs
S
GPIO
Compass
Tilt
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SPI FLASH: MEMORY
MAP
• First approach using SPI flash memory available in Kintex 7 Evaluation board
• CLBv2 flash memory: larger but with similar command set
KC705 EV. BOARD
CLBv2
Flash Memory
N25Q128 (16 Mbytes)
N25Q1Gb (128 Mbytes)
Sectors
256 (64 Kbytes each)
2048 (64 Kbytes each)
Pages
65536 (256 bytes each)
524288 (256 bytes each)
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CLBv2 SPI FLASHl : MEMORY MAP
48 Mbytes
Free Space
Space available in
SPI flash memory
16 Mbytes
Conf.Parameters
Configuration
parameters
16 Mbytes
Multiboot Image 3
16 Mbytes
Multiboot Image 2
16 Mbytes
Multiboot Image 1
16 Mbytes
Golden Image
Diferent Images to
reconfigure
the system
Stable Image to start
up and recovery
the system
Base Address
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LM32 WB SLAVE:
SPI DRIVER
SPI Opencores: From the WR repository
slave enable
SERIAL
INTERFACE
WISHBONE INTERFACE
WISHBONE
BUS
SPI DRIVER
mosi
STARTUP
PRIMITIVE
spi_clock
miso
CLOCK
GENERATOR
6
LM32 WB SLAVE:l SPI PROTOCOL
• SPI PROTOCOL: 4 signals
•Slave Enable (Memory is selected by driving this signal low)
•SPI clock
•MOSI (Master Out Slave In) Data from LM32 to flash memory
•MISO (Master In Slave Out) Data from flash memory to LM32
Slave Memory Enable
SPI clock
Data to memory (MOSI)
Data from memory (MISO)
7
LM32 WB SLAVE:l SLOW CONTROL
Library functions implemented:
•Read Identification
•Sector Erase
•Bulk Erase
•Write status register
•Read Status register
SUCCESSFUL TEST!
•Write enable
•Write disbale
•Page program
•Read
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FLASH PROGRAMMING
CHAIN
• To create the new programming chain (proposed by Vincent)
• Check the spi driver in the new embedded software (modifiy if needed)
Slow Control
Module
Storage
Module
Flash memory
Driver
SPI
Driver
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FLASH PROGRAMMING
TEST
• Create firmware (HEX or BIN) File
•MCS file contain information about address and checksum (maybe
not needed)
•Send firmware file to FPGA over serial link (UART Communication)
•Store it in flash memory using LM32-SPI slow control
• Reboot FPGA using multiboot slow control
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