256Mb: x4, x8, x16
SDRAM 3.3V
SYNCHRONOUS DRAM
Features:
•
•
•
•
•
•
•
•
•
•
•
Intel PC133 (3-3-3) compatible
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access precharge time
Programmable burst lengths: 1, 2, or 4 using
Interleaved Burst Addressing
Auto Precharge and Auto Refresh modes
64ms, 8,192-cycle refresh
Self Refresh mode option 1
LVTTL-compatible inputs and outputs
Single +3.3V ±0.3V power supply
The x16 devices are optimized for both single and
dual rank DIMM applications. The x8 devices are
optimized for single rank DIMM applications. The
x4 devices are optimized for registered single-rank
DIMM applications
Options:
Designation:
Family:
SpecTek Memory
SAA
Configuration:
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
Design ID
SDRAM 256 Megabit Design
(Call SpecTek Sales for details on
availability of “x” placeholders)
64M4
32M8
16M16
Yx6x
NOTES: 1. Only when specified. Consult Sales
2. Not available in x16 configuration
Voltage and Refresh:
3.3V, Auto Refresh, 8K refresh
3.3V, Self or Auto Refresh, 8K refresh
L8
M81
Package Types:
54-pin plastic TSOP (400 mil)
60-ball FBGA (8mm x 16mm)
60-ball FBGA (11mm x 13mm)
TW
FB2
FC2
Timing Types:
PC133 (3-3-3)
-75A
Part number example:
General Description:
The 256Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268,435,456 bits.
Each is internally configured as a quad-bank DRAM.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ
or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select
the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 select the row). The address bits registered
SAA32M8Y16AL8TW-75A
(For part numbers prior to December
2004, refer to page 10 for decoding.)
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
1
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SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek
256Mb: x4, x8, x16
SDRAM 3.3V
coincident with the READ or WRITE commands are used
to select the starting column location for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, or 4 locations with burst
terminate option using the Burst Interleaved Addressing
mode only. An AUTO PRECHARGE function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while
accessing one of the other three banks will hide the
precharge cycles and provide seamless high-speed,
random-access operation.
The 256Mb SDRAM is designed to operate in 3.3V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM
operating performance, including the abilities to
synchronously burst data at a high data rate with
automatic column-address generation, to interleave
between internal banks in order to hide precharge time,
and to randomly change column addresses on each clock
cycle during a burst access.
The x8 devices are optimized for single bank DIMM
applications. The x16 devices are available for both
single and dual bank DIMM applications. The x4 devices
are optimized for registered single-bank DIMM
applications.
____________________________________________
Disclaimer:
Except as specifically provided in this document, SpecTek
makes no warranties, expressed or implied, including, but not
limited to, any implied warranties of merchantability or fitness for
a particular purpose.
Any claim against SpecTek must be made within one year
from the date of shipment from SpecTek, and SpecTek has no
liability thereafter. Any liability is limited to replacement of the
defective items or return of amounts paid for defective items (at
buyer’s election). In no event will SpecTek be responsible for
special, indirect, consequential or incidental damages, even if
SpecTek has been advised for the possibility of such damages.
SpecTek’s liability from any cause pursuant to this specification
shall be limited to general monetary damages in an amount not
to exceed the total purchase price of the products covered by
this specification, regardless of the form in which legal or
equitable action may be brought against SpecTek.
____________________________________
ABSOLUTE MAXIMUM RATINGS:
Voltage on Vdd Supply relative to Vss
Operating Temperature TA (Ambient)
Storage Temperature
Power Dissipation
Short Circuit Output Current
-1 to +4.6V
+25° to +70 °C
-55° to +150 °C
1W
50 mA
Stresses beyond these may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at or beyond these conditions is not implied.
Exposure to these conditions for extended periods may affect
reliability.
CAPACITANCE:
(Note 2)
Parameter
Input Capacitance: CLK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
Symbol
CI1
CI2
CIO
2
www.spectek.com
Min
2.5
2.5
4.0
Max
3.5
3.8
6.0
Units
pF
pF
pF
NOTES
29
30
31
SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek
256Mb: x4, x8, x16
SDRAM 3.3V
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS:
(Notes: 1, 5, 6: Vdd = 3.3V ± 10%V, Temp. = 25° to 70 °C)
Parameter
Supply Voltage
Input High (Logic 1) Voltage, All inputs
Input Low (Logic 0) Voltage, All inputs
Input Leakage Current Any input = 0V < VIN < Vdd All other pins not under test =
0V
Output Leakage Current DQs are disabled; 0V < VOUT < VddQ
Output High Voltage (IOUT = -4 mA)
Output Low Voltage (IOUT = 4 mA)
Symbol
Vdd/Vddq
VIH
VIL
II
Min
3.0
2.2
-0.3
-10
Max
3.6
Vdd + .3
0.8
10
Units
V
V
V
µA
IOZ
VOH
VOL
-10
2.4
10
µA
V
V
Supply Current
OPERATING CURRENT: ACTIVE mode, burst = 1, READ or WRITE, tRC > tRC
(MIN), one bank active, CL=3
STANDBY CURRENT: POWER-DOWN mode, CKE = LOW,
Standard parts
no accesses in progress
Self refresh parts
STANDBY CURRENT: CS# = HIGH, CKE = HIGH, all banks idle
Symbol
Idd1
-75A
165
Units
mA
Notes
3, 19, 32
Idd2
Idd2
Idd3
9
3
75
mA
mA
mA
32
32
3, 12, 19,
32
STANDBY CURRENT: CS# = HIGH, CKE = HIGH, all banks active after tRCD
met, no accesses in progress.
OPERATING CURRENT: BURST mode after tRCD met, continuous burst, READ,
WRITE, all banks active, CL=3
AUTO REFRESH CURRENT tRC > tRC (MIN)
CL = 3
Idd4
75
mA
Idd5
165
mA
Idd6
265
mA
AUTO REFRESH CURRENT tRC= 7.8µs
Idd7
50
mA
Idd8
3
mA
0.4
Units
22
22
Idd OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6, 11, 13: Vdd = 3.3V ± 10%V, Temp. = 25° to 70 °C)
CL = 3
SELF REFRESH CURRENT (Self refresh parts only, part M)
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
3
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3, 18, 19,
32
3, 12, 18,
19, 33
3, 12, 18,
19, 33
SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek
256Mb: x4, x8, x16
SDRAM 3.3V
AC ELECTRICAL CHARACTERISTICS:
(Notes: 5, 6, 8, 9, 11. Vdd = 3.3V ± 10%V, Temp. = 25° to 70°C)
AC CHARACTERISTICS
PARAMETER
Access time from CLK (positive edge) CL = 3
Access time from CLK (positive edge) CL = 2
Address hold time
Address setup time
CLK high level width
CLK low level width
Clock cycle time CL = 3
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high impedance time
Data-out low impedance time
Data-out hold time
ACTIVE to PRECHARGE command period
AUTO REFRESH to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8,192 cycles)
PRECHARGE command period
ACTIVE bank A to bank B command period
Transition time
Write recovery time
Exit SELF REFRESH to ACTIVE command
SYMBOL
tAC
tAC
tAH
tAS
tCH
tCL
tCK
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ
tLZ
tOH
tRAS
tRC
tRCD
tREF
tRP
tRRD
tT
tWR
tXSR
-75A
MIN
-75A
MAX
5.4
N/A
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
1.5
0.8
1.5
9
1
2.7
44
60
22.5
16K
64
22.5
15
0.3
20
8
2
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
tCK
NOTES
27
23
10
7
15
20
AC ELECTRICAL CHARACTERISTICS:
(Notes: 5, 6, 7, 8, 9, 11. Vdd = 3.3V ± 10%V, Temp. = 25° to 70°C)
PARAMETER
READ/WRITE command to READ/WRITE command
CKE to clock disable or power down entry mode
CKE to clock enable or power down exit setup
DQM to input data delay
WRITE command to input data delay
Data-in to ACTIVATE command w/ Auto precharge
Data-in to precharge
Last data-in to precharge command
LOAD MODE REGISTER command to command
Data-out to high impedance from precharge
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
SYMBOL
tCCD
tCKED
tPED
tDQD
tDWD
tDAL
tDPL
tRDL
tMRD
tROH
-75A
1
1
1
0
0
5
2
2
2
3
4
www.spectek.com
UNITS
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
NOTES
17
14
14
17
17
15, 21
16, 21
16,21
26
17
SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek
256Mb: x4, x8, x16
SDRAM 3.3V
14. Timing actually specified by tCKS; clock(s)
specified as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC
functionality and are not dependent on any timing
parameter.
18. The IDD current will increase or decrease
proportionally according to the amount of frequency
alteration for the test condition.
19. Address transitions average one transition every two
clocks.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on tCK = 10ns for –75A.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width ≤3ns, and the pulse width cannot begreater
than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width ≤3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access
or precharge states (READ, WRITE, including tWR,
and PRECHARGE commands). CKE may be used
to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins 7.5ns for –75A after the first
clock delay, after the last WRITE is executed. May
not exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for –75A at CL = 3 with no load is 4.6ns and is
guaranteed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For –75A, CL = 3 and tCK = 7.5ns.
33. CKE is HIGH during refresh command period tRFC
(MIN) else CKE is LOW. The IDD6 limit is actually
a nominal value and does not result in a fail value.
NOTES
1.
2.
3.
4.
5.
6.
7.
8.
9.
All voltages referenced to VSS.
This parameter is sampled. VDD, VDDQ = +3.3V; F =
1 MHz, TA = 25°C; pin under test biased at 1.4V.
IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle time
and the outputs open.
Enables on-chip refresh and address counters.
The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is ensured; (25°C ≤TA ≤+70°C).
An initial pause of 100µs is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (VDD and VDDQ
must be powered up simultaneously. VSS and VSSQ must
be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the
tREF refresh requirement is exceeded.
AC characteristics assume tT = 1ns.
In addition to meeting the transition rate specification,
the clock and CKE must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
Outputs measured at 1.5V with equivalent load:
10. tHZ defines the time at which the output achieves the
open circuit condition; it is not a reference to VOH or
VOL. The last valid data element will meet tOH before
going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V,
with timing referenced to 1.5V crossover point. If the
input transition time is longer than 1 ns, then the timing
is referenced at VIL (MAX) and VIH (MIN) and no
longer at the ISV crossover point.
12. Other input signals are allowed to transition no more
than once every two clocks and are otherwise at valid
VIH or VIL levels.
13. IDD specifications are tested after the device is properly
initialized.
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
5
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SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek
256Mb: x4, x8, x16
SDRAM 3.3V
54-PIN PLASTIC TSOP (400 mil)
(package TW)
NOTE:
1. All dimensions in millimeters MAX/MIN or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
6
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SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek
256Mb: x4, x8, x16
SDRAM 3.3V
FBGA PIN ASSIGNMENT
(Top View)
64Meg x 4 SDRAM
32Meg x 8 SDRAM
“FB” and “FC” packages
“FB” and “FC” packages
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
7
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SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek
256Mb: x4, x8, x16
SDRAM 3.3V
NOTE:
1. All dimensions in millimeters.
2. Recommended Pad size for PCB is 0.33mm±0.025mm.
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
8
www.spectek.com
SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek
256Mb: x4, x8, x16
SDRAM 3.3V
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
9
www.spectek.com
SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek
256Mb: x4, x8, x16
SDRAM 3.3V
PART NUMBERS FOR PRODUCT PRIOR TO DECEMBER 2004
Options:
Marking:
Architecture:
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
S40064
S80032
S160016
Voltage and Refresh:
3.3V, Auto Refresh
3.3V, Self or Auto Refresh1
LL
ML
Device Configuration:
64 Meg x 4
32 Meg x 8
16 Meg x 16
B
C
D
Package Types:
54-pin plastic TSOP (400 mil)
60-ball FBGA (8mm x 16mm)
60-ball FBGA (11mm x 13mm)
TW
FB2
FC2
Timing Types:
PC133 (3-3-3)
-75A
Part number example:
S80032LLCTW-75A
NOTES: 1. Only when specified. Consult Sales
2. Not available in x16 configuration
http://www.spectek.com/menus/part_guides.asp
PDF: 09005aef80457d0d / Source: 09005aef8043e207
256Mb SDRAM
Rev: 11/23/2004
10
www.spectek.com
SpecTek reserves the right to change products or
specifications without notice.  2001, 2002, 2004 SpecTek