Will Avalanche Photodiode Arrays Ever Reach
1 Megapixel?
Edoardo Charbon
Swiss Federal Institute of Technology, CH-1015 Lausanne, Switzerland
one microsecond in CCD [4] and a few nanoseconds in
CMOS APS [5] have been demonstrated. While CCD streak
cameras can achieve a resolution of a few picoseconds, they
require a 2D pixel array to resolve a string of photon
arrivals. Moreover, long acquisition latency and the added
complexity to form and deflect the photoelectron beam
make this device unsuitable for miniaturization and lowcost operation.
Sensors based on solid-state APDs have been proposed
decades ago to simultaneously achieve high sensitivity and
dynamic range, and low timing uncertainty [6]. In APDs,
carriers generated by the absorption of a photon in the p-n
junction, are multiplied by impact ionization thus producing
an avalanche. APDs can reach timing uncertainties as low
as a few tens of picoseconds, thanks to the speed at which
an avalanche evolves from the initial carrier pair forming in
the multiplication region.
An APD is implemented as photodiode reverse biased
near or above breakdown, where it exhibits optical gains
greater than one. When an APD is biased below breakdown
it is known as proportional or linear APD. It can be used to
detect clusters of photons and to determine their energy.
When biased above breakdown, the optical gain becomes
virtually infinite. Thus, with a relatively simple ancillary
electronics, the APD becomes capable of detecting single
photons. The APD operating in this regime, known as
Geiger mode of operation, is called single-photon
avalanche diode (SPAD).
Abstract— In this paper the miniaturization and performance
potential of solid-state avalanche photodiodes is discussed in
the context of large multi-pixel sensors. Technological and
design trade-offs are discussed in view of recent advances in
CMOS imaging technologies and the emergence of new
multiplication based architectures.
I.
INTRODUCTION
In the last four decades, solid-state multiplication based
photodetectors have gradually evolved from relatively
crude devices to the sophistication of today. Almost every
imaging technology has one such device and the range of
implementations is quite wide [1]. In this context, silicon
avalanche photodiodes (APDs), thanks to their relative
simplicity and ease of fabrication, have recently attracted
significant interest.
There are two main lines of research in silicon APDs:
one that advocates the use of highly optimized processes to
boost performance and one that proposes to adapt APD
design to existing processes to reduce cost and to maximize
miniaturization.
In this paper we focus on the latter approach and we
discuss how the latest advances in imaging CMOS
processes may be used to maximize performance and to
boost miniaturization. We also discuss how advanced
processes can ensure in-pixel and on-chip processing of
ultra-high-speed signals that are typical of single-photon
detectors.
II.
SINGLE-PHOTON DETECTION AND SILICON APDS
III.
Devices for single-photon detection are realizable in
many solid-state and non-solid-state implementations.
While an in-depth discussion on the subject is beyond the
scope of this paper, we mention here two classes of
detectors that are currently the solution of choice in many
applications: multichannel or microchannel plates (MCPs)
and photomultiplier tubes (PMTs) [2].
A number of solid-state solutions have been proposed as
a replacement of MCPs and PMTs using conventional
imaging processes. The challenge though has been to meet
single-photon sensitivity and low timing uncertainty.
To address the sensitivity problem, cooled and/or
intensified CCDs, and ultra-low-noise CMOS APS
architectures have been proposed. Multiplication of
photogenerated charges by impact ionization has also been
used in conventional CCDs [3].
Meeting PMT’s picosecond timing uncertainty however,
to the best of our knowledge, has not been possible in
CCD/CMOS imagers, even though uncertainties as low as
APD DESIGN IN STANDARD CMOS PROCESSES
A. Basic Structure Design
There exist two main implementation styles for APDs.
The first, known as reach-through APD (RAPD) [7], is a
vertical structure, incompatible with planar CMOS
processes. The second involves a shallow p or n layer to
form high-voltage pn junctions. Cova and others have
investigated devices designed in this style since the 1970s,
yielding a number of structures equipped with a zone
designed to prevent premature edge breakdown (PEB) [8].
An early example of one such structure is shown in Fig. 1.
n+
p+
p-epi
n-substrate
FIG. 1. C ROSS-SECTION OF APDS THAT CAN BE FABRICATED IN A PLANAR
PROCESS.
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More recently, researchers have developed APDs both
in linear and Geiger mode using dedicated processes,
achieving superior performance in terms of sensitivity and
noise. A good example is the work of Kindt [9]. The main
disadvantage of using dedicated processes is the lack of
libraries that can support complex functionalities and deepsubmicron feature sizes, thus limiting array sizes. An
interesting alternative is the use of a hybrid approach
whereby the APD array and ancillary electronics are
implemented in two different processes, each optimized for
APD performance and speed, respectively [10].
In 2003 the integration of linear and Geiger mode APDs
in a low-cost CMOS process has become feasible [11].
PEB prevention is accomplished forcing the electric field
everywhere to be lower than that on the planar
multiplication region, where it should be uniform.
of charges to be easily detected and thus requiring no
further amplification.
SPADs however require mechanisms to quench the
avalanche. There exist two main quenching mechanisms:
passive and active. In passive quenching the avalanche
current is used to drop the voltage across the diode. This is
generally accomplished via a ballast resistor placed on the
anode or the cathode of the diode, as shown in Fig. 3.
Avalanche detection is accomplished measuring the voltage
across the ballast resistance (Fig. 3a, b) or the current
across a low- or zero-resistivity path (Fig. 3c, d). Pulse
shaping may be performed using a comparator (Fig. 3e).
Excess bias voltage equals |VOP| - |Vbd|, where Vbd is the
breakdown. The resistances may be implemented in
polysilicon [11],[12] or exploiting the non-linear
characteristics of PMOS or NMOS devices [13],[14].
VOP
p+
p
n+
VOP
n
X
Ix R
Vx
Vx
X
Vth
Ix R
b)
e)
a)
p
VOP
pn
a)
VOP
p
b)
c)
d)
FIG. 3. PASSIVE QUENCHING VARIANTS . VOLTAGE DETECTION MODE
(LEFT); CURRENT DETECTION MODE (RIGHT).
In active quenching mode, the avalanche activates an
active device to stop it. The literature on the subject is
extensive. In [15] some of the existing schemes can be
found. Other authors have recently revisited the issue [16].
After quenching, the device enters another phase known
as recharge. During this phase the photodiode bias voltage
must return to the pre-avalanche state as quickly as
possible. Again, there are passive and active schemes to
achieve recharge. The simplest approach is shown in Fig. 3.
The diode will automatically recharge to VOP via the ballast
resistance. The recharge, in this case, follows the RC
exponential, where R is the equivalent quenching resistance
and C the total parasitic capacitance at node X.
In active recharge schemes, the photodiode is forced to
the initial state generally via a fast switch controlled by a
current sense amplifier. Even though these schemes are
attractive, they usually require extra complexity to a pixel,
thus potentially hindering miniaturization.
The quenching and recharge times are collectively
known as dead time. Dead time in passive
quenching/recharge methods is potentially longer than in
their active counterparts. However, the advantage of a
reduced dead time in large array may be preempted by
limited speeds of pixel readout schemes.
n
c)
FIG. 2. TECHNIQUES FOR PREVENTION OF PREMATURE EDGE BREAKDOWN
(PEB) IN PLANAR PROCESSES.
Fig. 2 shows some of the most used structures. In a) the
n+ layer maximizes the electric field in the middle of the
diode. In b) a lightly doped p- implant reduces the electric
field at the edge of the p+ implant. In c) a floating p
implant locally increases the breakdown voltage. With a
polysilicon gate one can further extend the depletion region
(gray line in the figure). The figure also shows a 3D crosssection of b) including a p-substrate and an n-well isolation.
Modern imaging processes (with or without STI)
provide several lightly doped implants at three or more
depths. Thus, an optimal layer combination (p+/p-/n-well)
generally exists that can yield a good trade-off between
timing uncertainty and noise. However, care should be used
so as to avoid full depletion of the well and punchthrough’s between shallow tubs and substrate. Buried
layers should also be used with care to prevent punchthrough across the n-well.
C. The Importance of Miniaturization
The first SPAD implementations in 0.35µm CMOS
technology have demonstrated fully scalable pixels at a
pitch of 25µm. However, for a realistic Mpixel sensor
realization, this limit should be further reduced.
Pixel miniaturization has other benefits too. The
reduction of anode and cathode areas, in SPADs generally
reduces the dark count rate (DCR), i.e. the average
frequency of spurious pulses in the dark [11]. It also
reduces parasitic capacitance at node X (Fig. 3), thus
possibly reducing dead time. In addition, the number of
carriers involved in an avalanche is also reduced, thus
B. Quenching and Recharge Mechanisms
Linear APDs are multi-photon detectors, when used as
charge accumulators. Charges generated at each avalanche
are integrated and amplification may not be needed. In
single-photon detection mode, fast amplifiers are generally
used, adding to jitter and dark noise. SPADs on the
contrary can only operate in single-photon mode. This is
achieved operating the diode above breakdown by a voltage
known as excess bias voltage. Upon photon absorption, an
avalanche may be triggered involving a sufficient number
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decreasing the probability of carrier trapping and,
consequently, of afterpulsing. Finally, fewer carriers
involved in impact ionization will cause smaller photon
emission, hence causing less interference with other pixels.
IV.
[19],[20]. In this readout scheme, the column is organized
as a digital bus. When a photon is detected, the
corresponding pixel takes ownership of the bus, sending
timing related information as well as the ID of the pixel
generating such information to the exterior of the array.
An alternative approach for non-LLL situations is the
use of a latchless pipeline scheme. In this approach, the
absorption of a photon causes the SPAD to inject a digital
signal onto a delay line that acts as an ultra-fast conveyor
belt [21]. This method allows detection of photons
simultaneously on a column even though some restrictions
apply on the timing of the optical setup. Fig. 5 shows the
photomicrograph of chip implementing this readout style.
ACHIEVING MINIATURIZATION
A. Pixel Miniaturization
The first ingredient towards pixel miniaturization in a
given process is the simplest possible avalanche detection
mechanism. One possible solution consists of shifting VOP
to VDD, and ground to a negative voltage VP+. Hence, node
X (Fig. 3) can be made vary between VDD and ground,
thereby enabling the replacement of a relatively large
comparator by a simple properly designed inverter [11],
[12]. Fig. 4 shows an example of one such detector.
The second ingredient is the reduction of feature size
through processes that represent a good compromise
between available layers, doping profiles, and design rules.
Particularly important factors are the well-to-well minimum
distance, the doping levels in the multiplication regions,
and the level of defects in the lattice.
Circular
SPAD
VDD
Quenching
& Gating
X
25 µm
FIG. 5. PHOTOMICROGRAPH OF A SINGLE -PHOTON
LATCHLESS PIPELINE READOUT.
D ETECTOR WITH
10µm
VP+
V.
PERFORMANCE ISSUES IN LARGE APD ARRAYS
CMOS APDs are characterized by means of the same
parameters of conventional photodiodes, except for an
optical gain higher than one. APDs operating in Geiger
mode on the contrary require a specific set of parameters.
FIG. 4. PHOTOMICROGRAPH OF A S PAD IMPLEMENTED IN CMOS
TECHNOLOGY. A GUARD RING SURROUNDS THE ANODE FOR P E B
PREVENTION.
The third ingredient is the readout scheme. In general,
simpler pixel-level processing enables smaller sizes but it
may have an impact on performance. Alternatively, more
pixel parallelism may impact pitch.
A. Fill Factor
Due to the geometry of guard rings for PEB prevention,
in SPADs the fill factor may be as low as 1%. Using
modern readout techniques, fill factors of up to about 9%
have been demonstrated [21]. We have also demonstrated a
fill factor reclaim ratio of 15 using commercial microlense
arrays [22].
B. Pixel Sharing
Due to the need for independent quenching and recharge
in a SPAD array, the level of sharing cannot be pushed
unless one accepts time-sharing as well. This scheme
however may not be appropriate for photon-starved
applications. For low photon-count, time-resolved
applications it is possible for an entire pixel array or
column to share high-resolution time discriminators at a
cost of a higher sensor complexity.
B. Dead Time
In passive quenching/recharge devices dead time is
generally dominated by the recharge time, about 30-50ns,
and it varies a few percentage points across the array as a
function of temperature and process variability. This results
in mild saturation non-uniformity and time variability.
C. Readout Techniques
APDs can potentially be read out using a conventional
scheme similar to CMOS APS architectures. SPADs on the
contrary, generate a digital pulse for each detected photon.
To avoid missing photon counts, a pixel-level counter or
time discriminator can be used [17],[18]. However, large
counters are not desirable due to the fill factor loss and/or
extra time required to perform a complete readout. A partial
solution to this problem is the reduction of the counter
resolution (ultimately 1 bit), requiring more frequent
readouts and/or lower saturation. Another solution is to
access every pixel independently but sequentially using a
digital random access scheme [12],[13].
In low-light-level (LLL) applications, an alternative
approach may be used known as event-driven readout
C. Time Uncertainty or Jitter
In integrated SPADs jitter is limited from below by
geometry and process technology considerations. In arrays
of significant size, jitter generally degrades from 50ps to as
much as several hundreds of picoseconds due to electrical
path and electrical supply ripple. Techniques derived from
memory design, such as non rail-to-rail readout and
shielding should be exploited.
D. Photon Detection Probability (PDP)
The sensitivity is characterized in SPADs by the photon
detection probability (PDP) and it is the overall probability
that an impinging photon triggers a digital pulse. Detailed
physical models for PDP and its mechanisms can be found
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in [11]. PDP is dependent on temperature and excess bias
voltage. A good pixel-to-pixel uniformity is generally
observed. Based on on-going research, we expect that deepsubmicron SPADs achieve up to 40-50% PDP. In more
advanced deep-submicron processes, the multiplication
region will move to the surface and will be thinner. Thus,
sensitivity in shorter wavelengths will be reinforced. Fig. 6
plots PDP as a function of wavelength for two CMOS
technologies. In the inset PDP uniformity is shown [14].
This research was supported by a grant of the Swiss
National Science Foundation. The author is grateful to his
graduate students.
REFERENCES
[1] E. Charbon, “Will CMOS Imagers Ever Need Ultra-High Speed?”,
IEEE International Conference on Solid-State and IC Technology,
Vol. 3, pp. 1975-1980, Oct. 2004.
[2] J. McPhate, J. Vallerga, A. Tremsin, O. Siegmund, B. Mikulec, A.
Clark, “Noiseless Kilohertz-frame-rate Imaging Detector based on
Microchannel Plates Readout with Medipix2 CMOS Pixel Chip”,
Proc. SPIE, Vol. 5881, pp. 88-97, 2004.
PDP
40%
[3] J. Hynecek, “Impactron – A New Solid State Image Intensifier”, IEEE
Trans. on Electron Devices, Vol. 48, N. 10, pp. 2238-2241, Oct. 2001.
30%
[4] T. G. Etoh et al., An Image Sensor Which Captures 100 Consecutive
Frames at 1,000,000 Frames/s, IEEE Trans. on Electron Devices, Vol.
50, N. 1, pp. 144-151, Jan. 2003.
20%
10%
[5] G. Patounakis, K. Shepard, and R. Levicky, “Active CMOS Biochip
for Time-Resolved Fluorescence Detection“, IEEE Symposium on
VLSI, pp. 68-71, June 2005.
0.35µm CMOS
5%
0.8µm CMOS
400
500
600
700
800
900
[6] R.H. Haitz, “Studies on Optical Coupling between Silicon p-n
Junctions”, Solid-State Electronics, Vol. 8, pp. 417-425, 1965.
Wavelength [nm]
[7] R.J. McIntyre, “Recent Developments in Silicon Avalanche
Photodiodes”, Measurement, Vol. 3 N.4, pp. 146-152, 1985.
FIG. 6. PHOTON DETECTION PROBABILITY (PDP) AS A FUNCTION OF
IMPINGING RADIATION WAVELENGTH.
[8] S. Cova, A. Longoni, and A. Andreoni, “Towards Picosecond
Resolution with Single-Photon Avalanche Diodes”, Rev. Sci. Instr.,
Vol. 52, N. 3, pp. 408-412, 1981.
E. Dark Count Rate
As mentioned earlier, DCR is a function of detector
area. It is also a function of temperature and excess bias
voltage. On a large chip, DCR may vary widely from a
minimum of a few Hertz to a few kilohertz. Generally,
noisy pixels are less than 1% of the array, depending upon
the distribution of traps across the chip and the overall
quality of the process. Hence, it is always a good practice
to foresee means to shut off pixels either temporarily or
permanently, depending on applications.
[9] W.J. Kindt, “Geiger Mode Avalanche Photodiode Arrays for Spatially
Resolved Single Photon Counting”, Ph.D. Thesis, Delft University
Press, ISBN 90-407-1845-8, 1999.
[10] B. Aull et al., “Geiger-Mode Avalanche Photodiodes for ThreeDimensional Imaging”, Lincoln Laboratory Journal, Vol. 13, N. 2,
pp. 335-50, 2002.
[11] A. Rochas, “Single Photon Avalanche Diodes in CMOS Technology”,
Ph.D. Thesis, Lausanne, 2003.
[12] C. Niclass, A. Rochas, P.A. Besse, and E. Charbon, “A CMOS Single
Photon Avalanche Diode Array for 3D Imaging”, IEEE ISSCC, pp.
120-121, Feb. 2004.
F. Afterpulsing
Afterpulses are the result of secondary avalanches
related to earlier photon detections. The mechanisms
behind afterpulsing are well understood and the literature
on the subject is extensive [11]. In active recharge schemes,
a minimum recharge time needs to be allocated to allow for
single-photon detectors to recover from an avalanche, thus
keeping afterpulsing probability below a threshold. Fewer
impact ionizations and fewer traps can reduce this time.
[13] C. Niclass and E. Charbon, “A Single Photon Detector Array with
64x64 Resolution and Millimetric Depth Accuracy for 3D Imaging”,
IEEE ISSCC, pp. 364-365, Feb. 2005.
[14] C. Niclass A. Rochas, P.A. Besse, and E. Charbon, “Design and
Characterization of a CMOS 3-D Image Sensor Based on Single
Photon Avalanche Diodes”, IEEE JSSC, Vol. 40, N. 9, Sep. 2005.
[15] S. Cova, M. Ghioni, A. Lacaita, C. Samori, F. Zappa, “Avalanche
Photodiodes Quenching Circuits for Single-Photon Detection”,
Applied Optics, Vol. 35, N. 12, pp. 1956-1976, 1996.
[16] J. Richardson, R. Henderson, and D. Renshaw, “Dynamic Quenching
for Single Photon Avalanche Diode Arrays”, to appear, Intl. Imaging
Sensor Workshop, June 2007.
G. Crosstalk
Crosstalk can be optical and electrical. In optical
crosstalk, luminescence released by an avalanche elsewhere
may cause avalanches. In electrical crosstalk, a carrier
generated elsewhere may trigger avalanches. The
techniques for preempting optical crosstalk include optical
shields between pixels [6]. Electrical crosstalk is strongly
reduced insulating the multiplication region, for example,
with a well (Fig. 2). The drawback of this approach is the
reduction of fill factor and/or the increase of overall pitch.
VI.
[17] E. Charbon, “Techniques for CMOS Single Photon Imaging and
Processing”, IEEE ASICON, Oct. 2005.
[18] D. Stoppa et al., “A CMOS 3-D Imager based on Single Photon
Avalanche Diode”, to appear, Trans. Circuits and Systems I, 2007.
[19] C. Niclass, M. Sergio, E. Charbon, “A Single Photon Avalanche
Diode Array Fabricated in Deep-Submicron CMOS Technology”,
Design Automation & Test in Europe (DATE), Mar. 2006.
[20] C. Niclass, M. Sergio, E. Charbon, “A 64x48 Single Photon
Avalanche Diode Array with Event-Driven Readout”, European
Solid-State Circuits Conference (ESSCIRC), Sep. 2006.
CONCLUSIONS AND ACKNOWLEDGMENTS
[21] M. Sergio, C. Niclass, E. Charbon, “A 128x2 CMOS Single Photon
Streak Camera with Time-Preserving Latchless Pipeline Readout”,
IEEE ISSCC, pp. 120-121, Feb. 2007.
In the near future optical sensors might look
increasingly like memories; pixels like single-photon
detectors, thus generating increasing interest in linear and
Geiger-mode APDs [23]. Yet, despite recent advances,
integrated APD technology still lags behind CCD and
CMOS APS. This paper addresses those issues and
technological solutions for high-density APD arrays.
[22] Süss MicroOptics, http://www.suss-microoptics.com
[23] E. Fossum, “What To Do With Sub-Diffraction-Limit (SDL) Pixels?
A Proposal for a Gigapixel Digital Film Sensor (DFS)”, I E E E
Workshop on CCDs and Advanced Image Sensors, pp. 214-217, June
2005.
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