Integration of Millimeter-wave Components in SOI
CMOS Processes
Mehmet Parlak, and James F. Buckwalter
California Institute for Telecommunications and Information Technology (CALIT2) and
Department of Electrical and Computer Engineering; Jacobs School of Engineering, University of California San Diego, CA 92093
Motivation and Applications
Challenge with Satellite Front-end Electronics
Should provide high-power ( e.g. >1 W) and
low-noise operation (e.g. <2 dB).
Should be radiation hardened integrated
circuits.
Commercial Applications
Network
HUB
Internet
Branch Offices
Q-Band Low Noise Amplifier
Problems with Milstar
Weight - Each satellite weighs 10,000 lbs.
Limited Coverage - 5 thousand users at a time.
Cost - $800 million per unit costly process
and electronics.
The chip area is 0.35mm x
0.40mm = 0.14mm2 excluding
the pads.
All interconnects are
implemented using the 9-8-9
µm (50 Ω) CPW line.
Military Applications
High Data Rate
Applications
• Credit Card Validation
• ATM/Pay at the Pump
• Inventory Control
• Store Monitoring
• Electronic Pricing
• Training Videos
• In-Store Audio
• Broadband Internet
Access
• Distance Learning
Corporate Offices Residential Corporate Data
Center/HQ
Schematic and EM illustration
MILSTAR = Military Strategic and Tactical
Relay satellite
United States government satellite comm.
system
EHF uplink: Q-band (44-GHz)
Secure, point to point comm.
Passive I/Q Mixer
Chip microphotograph
All of the metal and polysilicon layers at the transistor gate and drain are extracted up to M2 using an
R/C parasitic extraction tool (Calibre).The metal layers from LB down to B1 are modeled using the thickmetal model in Sonnet with multiple number of sheets.
Top metal and B3 is both GND through the chip & shorted with vias.
Chip microphotograph
Schematic and EM illustration
No T/R switch,
- Two antennas for RX/TX;
- Bigger size package,
- Routing loss (array size),
- Highly scaled arrays T/R switch
- Sharing the antenna;
- Less area, less cost,
- Less routing loss,
2-stage cascode; 1st stage biased at 0.23 mA/µm (gain, and
noise purpose), 2nd stage biased at 0.28 mA/µm (gain purpose)
Input/output matched to 50Ω with input and output M.N.
NF measurement with Agilent
346CK01 noise source & Agilent
E4448A. A Q-band preamplifier
for 0.15 dB NF uncertainty.
The measured return loss of the RF and LO port is better than -14 dB and -32 dB at 45 GHz
The conversion loss is 8.35 dB and gain and phase imbalance is 1 dB / 2 degrees, respectively/
The mixer results in a gain compression point (P1dB) of 4.5 dBm at 48 GHz.
Comparison Tables
45-nm Digital SOI CMOS
Limitations of bulk CMOS MOSFETs
RF loss / coupling through the substrate
Parasitics capacitance of the MOS structure,
Its relatively high on-resistance,
Limited power handling capability.
CMOS Technology
of the LNA
Freq.
(GHz)
Gain
(dB)
Noise
Figure
(dB)
PO1dB
(dBm)
130nm CMOS [1]
40
19
N/A
-0.9
36
N/A
130nm CMOS [2]
38
14.3
3.8
-6
28.8
0.062
Silicon-on-Insulator
Si layer on top of an insulator layer (SiO2) to
build active devices and circuits.
Benefits of Digital CMOS 45nm SOI
High ft and fmax
Integration with other subsystems
Low parasitics, i.e. the junction diode
between the source/drain node and subs.
Low leakage (high isolation),
Resistance to ionization by radiation
The immunity to latch-up
Good trade-off of off-capacitance
(isolation) & on-resistance (insertion loss)
Low power consumption, low noise
11 Metal Layers
Top Metal Thickness = 2.2 µm
Distance from top metal to silicon = 11. 75 µm
Isolation; BOX (145nm) + STI (80nm) = 225nm
Substrate Resistivity = 13.5 Ω-cm
EM Simulations (Sonnet)
Over 3 chips
The gain is 18.5 dB at 48 GHz, 3-dB bandwidth is 10 GHz (43 to 53 GHz), input & output return losses < -15dB.
Between 40 -60 GHz; the gain is greater than 10 dB and input return loss is greater than 6 dB.
The IIP3 = -3 dBm and OIP3 = 14 dBm (At 48GHz spaced by 50MHz), input P1dB = -15dBm, Psat = 7 dBm.
Single Pole Double Throw Switch
Circuit model of NMOS
Channel resistance
Schematic and EM illustration
Chip microphotograph
Insertion
Loss(dB)
Isolation
(dB)
Speed
Linearity
(P1dB)
40
14
3.6
N/A
19.2
N/A
34
23.5
2.9
-6
11
0.024
90nm SOI [5]
35
11.9
3.6
4
40
0.049
65nm CMOS [6]
42
6
6
43.2
45nm SOI [7]
48
2.9
3
22.8
0.092
Noise Figure
(dB)
OIP3
(dBm)
Pdc
(mW)
InP HEMT–Lo (1993)
43-46
25
2.3
N/A
12
InGaAs HEMT- Duh (1993)
36-46
20
3.5
21
N/A
InP and GaAs –Aust (1996)
43-46
20 / 28
1.8 / 2.7
N/A
N/A
InP HEMTs-Isobe (2002)
43-45
22
2.1
N/A
GaN –Moyer (2008)
42-47
19
3.1
28
400
mHEMT-Lynch (2010)
40-44
11
3.5
N/A
N/A
43-53
18.5
2.9
14
22.8
Power
Cons.
Bias/Voltage
Control
Cost
In
t.
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Insertion
Loss
(dB)
Isolation
(dB)
Topology
130nm CMOS
Series-shunt
DC-35
2.4@35GHz
31
130nm CMOS
Series-shunt
DC-30
3.1@30GHz
>25
9
130nm CMOS
Series-shunt
DC-70
3.5@67GHz
>25
9-10
90nm CMOS
Transformer
40-55
3.4@50GHz
13.7
14
>9
14
Shunt SPST
DC-94
1.6@94GHz
30
45nm SOI
Distributed
DC-94
5.3@94GHz
20.5
GaAs HJFET
Series-shunt
DC-60
1.64@60GHz
20.6
21
GaAs FET
Shunt
55-65
1.8@60GHz
40
N/A
MEMS
N/A
DC-40
2.4@35Gz
13
IIP3>65 @ 1GHz
MEMS
direct contact
35-60
0.34@50GHz
15.5
N/A
PIN Diode
N/A
36-84
2 @58GHz
2.5@60GHz
111
PO1dB (dBm)
Technology
Series-shunt
0.031
Gain
(dB)
SOI
DC-60
18.5
Freq. (GHz)
GaAs
65nm CMOS
14.3
Other Technologies
CMOS
This Work
45nm SOI
11
>27
25
>25
7.1
Summary
BOX conductivity has a very small effect when substrate resistivity is small.
BOX conductivity has a big effect when substrate resistivity is nominal or high.
Altering the substrate resistivity in SOI, quality factor changes from 11 to 14.1
LNA Design for Simultaneous Noise and Power Matching (CICC 2011)
Q-band LNA: 2.9 dB NF (state of art), 18.5 dB gain, output P1dB = 2.5dBm, and OIP3 = 14dBm.
Proper sizing of series FET gate width, M1 and shunt FET gate width, M2
Trade-off between on resistance (Rch) in the triode region (insertion loss) and Cds in cut-off region (isolation).
BOX thickness has the max. /min. effect when substrate
resistivity is low/ high, respectively. Altering the substrate
resistivity, quality factor changes 2.2 at max .
120nm SOI [3]
PIN-D.
BW
(GHz)
FOM
120nm SiGe [4]
45nm SOI – This Work
Tech.
Pdc
(mW)
An insertion loss of 1.7 dB, isolation of 25 dB at 45 GHz,
The insertion loss and isolation changes 0.2 dB and 2 dB when gate control voltage is varied from 0.9 V to 2.1 V.
Bias resistance Rgate Insertion loss, parasitics, switching time, linearity
Switching time R –C time constatnt for this design is 5RC = 360ps. Capable of settling in half ns.
SPDT Design for Low Insertion Loss and High Isolation (CSICS 2011)
DC-60GHz Series Shunt SPDT: 1.75dB insertion loss at 45 GHz, 25dB isolation, 7dB P1dB
Passive Resistive I/Q Ring M ixer Design for low gain and phase imbalance and loss (in prep.TMTT 2012)
A conversion loss of 8.35 dB and input P1dB of 9 dBm at 43 GHz.
The gain and phase imbalance is 1 dB and 2 degrees, respectively and is minimized using 8 DC pads.
SOI is a good technology candidate in minimizing the cost , and size of the satellite front end electronics,
and will be highly beneficial in highly scaled beamforming and phased array systems.