DEGREE PROJECT, IN COMPUTER SCIENCE , FIRST LEVEL
STOCKHOLM, SWEDEN 2015
Factorization patterns in 3-SAT
ANALYSIS OF CLAUSE ORDERING FOR
REDUCTIONS OF THE
INTEGERFACTORIZATION PROBLEM
ADRIAN HÄGGVIK, MARWAN KHALILI
KTH ROYAL INSTITUTE OF TECHNOLOGY
CSC SCHOOL
Factorization patterns in 3-SAT
Analysis of clause ordering for reductions of the integer
factorization problem
Adrian Häggvik
Marwan Khalili
Degree Project in Computer Science, DD143X
Supervisor: Per Austrin
Examiner: Örjan Ekeberg
CSC, KTH 2015-05-08
Abstract
Dividing a large integer into factors is a well-known difficult problem
that is heavily used in modern cryptography. One approach to achieve
faster factorizations is to reduce the Integer factorization problem to another difficult problem, for example the Boolean satisfiability problem.
Many studies have been done on the optimization of algorithms that
can solve the Boolean satisfiability problem effectively and multiple programs have been created for the purpose of achieving efficiency. This
study focuses on one of these programs, MiniSAT, with the objective of
finding patterns in the input that result in faster runtimes for solving
reduced instances of the Integer factorization problem.
The method used for finding these patterns was to create different
reductions from the Integer factorization problem to the Boolean satisfiability problem and then solving the reduced instances using MiniSAT.
The order of the clauses in the boolean formulas were changed in order to
analyze which order yields the best results. In total, seven orderings were
tested for factorizing four products using three different reductions.
Our conclusions are that none of the patterns lead to better results
for every test case. Not changing the order of the clauses will achieve
consistent results, however there are cases when shuffles with variance
could be preferable.
Sammanfattning
Uppdelning av ett stort heltal i faktorer är ett välkänt svårt problem som
vardagligen används i modern kryptografi för att kryptera data. Ett visst sätt
att uppnå snabbare tider av faktoriseringen går ut på att reducera instanser
av faktoriseringsproblemet till ett annat svårt problem, till exempel satisfierbarhetsproblemet.
Många studier har gjorts med avseende på optimeringar av algoritmer som
löser satisfierbarhetsproblemet, och flera program har skapats i syftet att lösa
problemet mer effektivt. Denna studie fokuserar på ett av dessa program,
MiniSAT, med målet att hitta mönster i indatan som resulterar i snabbare
lösningstider för reducerade instanser av faktoriseringsproblemet.
Metoden som används för att hitta dessa mönster var att skapa olika reduktioner från faktoriseringsproblemet till satisfierbarhetsproblemet och sedan lösa
de reducerade probleminstanserna med MiniSAT. Ordningen av klausulerna i
de booleanska formlerna ändrades och resultaten för varje ordning analyserades.
Totalt testades sju olika sorteringar för att faktorisera fyra produkter med tre
olika reduktioner.
Våra slutsatser är att inget specifikt mönster ger det bästa resultat för varje
testfall. Att inte ändra ordningen på klausulerna ger konsistenta resultat, men
det finns fall då en ordning som har varierande resultat kan vara att föredra.
Contents
1 Introduction
1.1 Thesis Motivation . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Problem Description . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Background
2.1 FACT to SAT reduction . . . . . . . . .
2.1.1 Long multiplication . . . . . . .
2.1.2 Binary adders . . . . . . . . . . .
2.1.3 Tseitin transformation . . . . . .
2.1.4 Propagation delay . . . . . . . .
2.2 SAT solvers . . . . . . . . . . . . . . . .
2.2.1 Backtracking search algorithm .
2.2.2 Conflict-Driven Clause Learning
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3 Method
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3.1 Literature study . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Circuit construction . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Test method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Results
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5 Discussion
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5.1 Ordering of the clauses . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Adder and product implications . . . . . . . . . . . . . . . . . . . 18
5.3 Test discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Conclusions
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1
Introduction
The art of decomposing a composite number into smaller integers is known as
the Integer factorization problem (FACT). Although the FACT problem has
been known for a long time its complexity has not yet been determined. There
is no published algorithm that can factorize all integers in polynomial time, yet
there is also no definitive proof that such an algorithm does not exist. This
apparent difficulty of factoring large integers is widely used in modern cryptographic algorithms, such as the RSA encryption [1]. Consequently, improving
the modern factorization algorithms is essential to ensure that these cryptographic algorithms can not be exploited.
Although it may be impossible to develop an algorithm that solves the integer
factorization problem in polynomial time for all integers, there are numerous
ways of solving the problem more efficiently. A possible approach is reducing
the FACT problem to an instance of the Boolean satisfiability problem (SAT).
The SAT problem is known to be a NP-complete problem [2]. Since the
FACT problem is known to be in NP [3], it is possible to reduce every instance
of the Integer factorization problem to an instance of the Boolean satisfiability
problem. One way of reducing instances of the FACT problem to SAT is by
creating multiplier circuits and encoding the circuits to boolean formulas of
different SAT variations, most notably 3-SAT (described in Section 1.3). What
makes this a rewarding approach is the fact that SAT-solvers is an area that
has been investigated thoroughly, to the point where contests are being held to
determine the best solvers for various SAT-problems [4].
1.1
Thesis Motivation
The reduction from FACT to SAT comes with a multitude of possibilities considering optimizations. There are a lot of factors that impact how fast an instance
of the boolean satisfiability problem can be solved.
Despite the creation of many high performance SAT-solvers, there exists
other fields where improvements are possible for factorizing integers using SATsolvers. One of these possibilities is to optimize the input that is treated by the
solvers, which can be done by changing the structure of the boolean formula.
Optimizing the input is not as explored as improving the solvers themselves
which makes the area intriguing. There have been some previous studies on
this subject, but only on a basic level. A study made by Gilles Audemard and
Laurent Simon [5] analyzed if the ordering of clauses and literals, in general
SAT instances, affect a SAT solver called MiniSAT. However, the study was
done with the goal of shedding light on new areas that could be investigated.
This thesis will research patterns of the boolean formulas, specifically in reduced
FACT instances, in hope of finding improvements in the field.
4
1.2
Problem Description
This report will analyse how the order of clauses in a boolean satisfiability
formula affect the performance of a typical CDCL-solver MiniSAT (described
in Section 2.2) evoking the following problem description:
Examine how selected reductions of FACT to 3-SAT relate to each other in
regards to time consumption when ordering of clauses in the 3-SAT formula is
changed. Are there patterns for the reduced instances that lead to better results
using MiniSAT and will these patterns be better suited for some specific circuit
designs?
1.3
Terminology
Terms used in this thesis.
FACT Integer factorization problem
SAT Boolean satisfiability problem.
Literal In mathematical logic, a boolean variable.
Clause Proposition for a SAT formula. Each clause is a disjunction of literals.
CNF Boolean formulas composed solely of conjunctions of clauses.
3-SAT CNF with each clause consisting of at most three literals.
Conflict Literal assignments that causes a clause to become indeterminable.
5
2
2.1
Background
FACT to SAT reduction
Stephen Cook and David Mitchell were the first to propose a reduction of a
FACT instance to SAT:
“A SAT instance would be an encoding of a boolean multiplier circuit computing the known product M from unknown inputs P and Q. Variables are the
bits of P and Q (the inputs of the circuit), together with the outputs of the
gates of the circuit. Clauses assert the correct behavior of the gates and assert
that the output of the circuit represent the given value of M.” [6] This theory
can be used as the foundation for reducing FACT instances to SAT.
2.1.1
Long multiplication
When constructing a boolean multiplier circuit the theoretical goal is to implement the functionality of a multiplication method for binary numbers. A natural
way of calculating the product of two factors is by multiplying the multiplicand
by each digit of the multiplier and add up the properly shifted results [7]. Figure
1 shows an example of this approach called long multiplication, which multiplies
42 (multiplicand) by 57 (multiplier) and arrives at 2,394 as the result.
Figure 1: Long multiplication of 42 by 57 in base 2
In order to construct a circuit that multiplies two numbers using long multiplication, as shown in Figure 1, it is necessary to implement circuits that are
able to add up the shifted results. A multiplier circuit that implements long
multiplication for a set size can be seen in Figure 2.
The addition that is done in the long multiplication is distributed among
the logical units such that each row of logical units in the circuit corresponds to
an addition of two rows in the long multiplication method. This circuit design
requires that each logical unit can pass on their calculation to the next unit,
which can be done using binary adders.
6
Figure 2: Circuit for long multiplication of two 5-bit binary factors
2.1.2
Binary adders
Two common logical units used in circuits are the full adder and the half adder.
The use of these binary adders is to add a number of input bits and output the
result as two output values; a sum-bit and a carryout-bit [8].
The full adder is used when adding two input bits and a carryin-bit. There
are many ways to build a full adder with gates but all of them share the same
output given the same input. The truth table represented in Table 1 shows how
variables should behave with given inputs.
Table 1: Truth table for a full adder
Input
Output
A
B
Cin
Sum
Cout
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
7
The half adder is similar to the full adder except that it does not take a
carryin as an input bit [8]. Half adders often find their use at the start of a
circuit where you want to add two inputs before a carryin-bit is needed. A half
adder behaves according to the truth table shown in Table 2.
Table 2: Truth table for a half adder
Input
2.1.3
Output
A
B
Sum
Carry
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
Tseitin transformation
An approach of encoding a logical circuit into a boolean expression is to use
the Tseitin transformation [9], which outputs a 3-SAT formula with a size that
grows linearly relative to the circuit’s gates. The Tseitin transformation will
directly convert the logical gates to their corresponding boolean logic formulas.
Below follows the 3-SAT representation of corresponding logical gates that
will be used in this report, when encoded using Tseitin transformation:
AN D : Z = X · Y → (X ∨ Y ∨ Z) ∧ (X ∨ Z) ∧ (Y ∨ Z)
N AN D : Z = X · Y → (X ∨ Y ∨ Z) ∧ (X ∨ Z) ∧ (Y ∨ Z)
OR :
Z = X + Y → (X ∨ Y ∨ Z) ∧ (X ∨ Z) ∧ (Y ∨ Z)
XOR : Z = X ⊕ Y → (X ∨ Y ∨ Z) ∧ (X ∨ Y ∨ Z) ∧ (X ∨ Y ∨ Z) ∧ (X ∨ Y ∨ Z)
8
Transforming a logical unit
A demonstration of a Tseitin transformation for a logical circuit can be shown
by transforming a half adder into its 3-SAT counterpart.
Figure 3: Circuit of a half adder
As shown in Figure 3, a half adder can be constructed using one XOR-gate
and one AND-gate, which will generate the following clauses when applying the
Tseitin transformation on the gates:
XOR : (A ∨ B ∨ S) ∧ (A ∨ B ∨ S) ∧ (A ∨ B ∨ S) ∧ (A ∨ B ∨ S)
AN D : (A ∨ B ∨ C) ∧ (A ∨ C) ∧ (B ∨ C)
In order to create fully functional clauses, literals have to be used that correspond to the inputs and outputs of the logical circuit unit. Inputs A and B are
assigned to literals 1 and 2 and outputs S and carry C are assigned the literals
3 and 4. The following clauses will be created, where each clause is represented
by the context inside parentheses:
XOR : (1 ∨ 2 ∨ 3) ∧ (1 ∨ 2 ∨ 3) ∧ (1 ∨ 2 ∨ 3) ∧ (1 ∨ 2 ∨ 3)
AN D : (1 ∨ 2 ∨ 4) ∧ (1 ∨ 4) ∧ (2 ∨ 4)
In order to make the boolean formulas readable for MiniSAT the format has
to be changed to a suggested standard format, DIMACS [10]. The DIMACS
format can be achieved by replacing each disjunction with a whitespace character and each conjunction with the number 0. Each negative value is written as
-x where x is the number of the literal. The final clauses for a transformation
of a half adder to 3-SAT will be the following:
-1 -2 -3 0
-1 -2
3 0
1 -2
3 0
1
2 -3 0
-1 -2 -4 0
-1
4
0
-2
4
0
9
2.1.4
Propagation delay
In circuit design, an important goal is to minimize propagation delay through
adding logical gates. However, previous experiments [11] have shown that superior circuit performance does not guarantee efficiency for the SAT solvers.
2.2
2.2.1
SAT solvers
Backtracking search algorithm
Modern SAT solvers work in different ways. Depending on which actions that
are being preformed during the runtime, the solvers can be affected differently
when input data is altered.
One way to explore the space of variable assignments is by employing a
systematic backtracking search algorithm. The algorithm runs by choosing a
literal and assigning a boolean value to it; all clauses which become true under
the assignment are removed and the formula is recursively checked if it still
is satisfiable. If the check fails, the algorithm backtracks and does the same
recursive check with an opposite polarity assigned to the chosen literal [12].
2.2.2
Conflict-Driven Clause Learning
The Conflict-Driven Clause Learning (CDCL) algorithm [13] enhances the backtracking algorithm by simplifying the set of clauses at each step. The simplification is partly done with unit propagation, which is a procedure to simplify a set
of clauses by identifying literals that occur in only one polarity and eliminating
all clauses that contain those literals. The second simplifying procedure, pure
literal elimination, is split into the following steps:
1. Remove all clauses that are satisfiable with the assigned literals.
2. Remove all occurrences of the assigned literals with the opposite polarity.
The main difference between CDCL and earlier versions of SAT solvers is
that CDCL’s backtracking can be non-chronological, in which case it tries to find
an appropriate level for backtracking by analyzing the conflicting assignments
and adding a new clause which explains and prevents repetition of the same
conflict.
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3
3.1
Method
Literature study
A literature study was made in order to get a better understanding of how
a reduction from FACT to SAT can be done and the underlying theories for
those reductions were studied. In addition, the literature study identified flaws
in previous research which could provide a basis for this thesis. The information sources were gathered from electronic libraries, mainly academic publishing
websites.
3.2
Circuit construction
Multiplier circuits were implemented for the reductions with a design similar
to the one described in Figure 2 (see Section 2.1.1). Using the same design
structure, the circuit was expanded with additional gates and adders in order
to handle larger factors.
In order to vary the reduced instances, this study used three different implementations of full adders named FA1, FA2 and FAN1. Both FA1 and FA2 are
full adders consisting of two XOR-gates, two AND-gates and one OR-gate. FA2
was implemented as two half adders and one OR-gate whereas FA1 was coded
as individual gates added together, which can be seen in Figure 4 and Figure 5.
Figure 4: Circuit for the full adder FA1, consisting of separate gates
Figure 5: Circuit for the full adder FA2, consisting of two half adders
11
The designs of FA1 and FA2 are almost identical but implemented differently.
The implementations create different orders of the literals within the clauses,
when the circuits are encoded to 3-SAT.
FAN1 varies from FA1 and FA2 in its structure, being made up of only
NAND-gates, as seen in Figure 6. Apart from having less variation of gates,
there is also a difference in the amount of gates that make up the FAN1 full
adder. While both FA1 and FA2 consist of five gates, FAN1 is constructed with
eight gates, resulting in more literals when the circuits are encoded to 3-SAT.
These adder implementations give the tests a broad variation that includes
changes in both gate structure and literal order, which is essential for establishing whether a pattern is suited for a specific circuit design or if the pattern is
universal.
Figure 6: Circuit for the full adder FAN1, consisting of NAND-gates
3.3
Test method
Each multiplier circuit was implemented and encoded to 3-SAT using Tseitin
transformation on each gate in the circuit. The DIMACS format was used for
the representation of the encoded multiplier circuits in 3-SAT because of its
widespread use and easy conversion to other formats [10].
The program of choice for solving the reductions was MiniSAT [14] for its
good documentation and extensive use in previous studies. The test cases were
executed using MiniSAT version 2.2.1 with the default settings enabled. MiniSAT outputs the performance statistics which includes the CPU time and memory usage required for the execution. The program can also present search
statistics such as the number of literals, conflicts and decisions.
All tests were executed on resource machines provided by Royal Institute of
Technology’s School of Computer Science and Communication that are specifically assigned to run computational tests. This will contribute to the test
results’ credibility since the resource machines have the same specifications and
provide limited interferences.
12
The preliminary tests showed that 24-bit factors was suitable for testing a
relatively large amount of reductions while still factorizing big numbers, which
makes differences in performance distinguishable. Since the factors of all products are of a constant 24-bit size, the implemented circuit structures will not
vary between the numbers, apart from using different full adders.
Since prime numbers are used as factors in cryptographic algorithms [11],
all the test cases will factorize semiprime numbers (a semiprime number is a
product of two prime factors).
The products that were factorized in the test cases are the semiprimes listed
below, followed by their prime factors:
• 112,781,490,138,769 = 10,619,863 x 10,619,863
• 178,084,726,903,849 = 10,619,863 x 16,769,023
• 225,827,040,912,091 = 13,466,917 x 16,769,023
• 281,200,132,374,529 = 16,769,023 x 16,769,023
The products were factorized with the three full adders and seven different
sortings of the clauses. The factorization for each sorting was repeated 20 times
for each product and full adder, resulting in 1680 test cases in total. The seven
sortings are described below.
Unshuffled, UN All clauses keep their original order from the input data. The
clauses that represent the literals of the product that is being factorized,
the product clauses, are placed first and the rest of the clauses, rest clauses,
that represent the encoded gates of the circuit is placed after the product
clauses.
Unshuffled reverse UNR Similar to UN, with the exception that the the
product clauses are placed after all the rest clauses. The order of the
product clauses in relation to each other are still the same. The order of
the rest clauses in relation to each other are also the same.
Productshuffle, PROD The order of the rest clauses remains unchanged
while the order of the product clauses, in relation to each other, are shuffled. Product clauses are placed before rest clauses.
Productshuffle reverse, PRODR Similar to PROD with the exception that
the product clauses are placed after the rest clauses.
Restshuffle, REST The order of the product clauses remain unchanged while
the order of the rest clauses are shuffled, in relation to each other. The
product clauses are placed first.
Restshuffle reverse, RESTR Similar to REST with the exception that product clauses are placed last (after the rest clauses).
Fullshuffle, FULL All clauses are shuffled as a group, every clause is therefore
placed randomly in the input data.
13
4
Results
By compiling all the test results into a graph for each factorization, an overview
can be created for the runtimes of the different clause sortings. These graphs
are shown in Figure 7 to Figure 10.
All graphs are represented as box plots which ”uses the median, the approximate quartiles, and the lowest and highest data points to convey the level,
spread, and symmetry of a distribution of data values.”[15] For the these box
plots, the whiskers correspond to the extrema (minimum and maximum values)
while the horizontal line inside each box corresponds to the median value.
For each graph, the horizontal axis represents the different reduced instances
(varying in clause order and full adder). The vertical axis represents the runtime
for the corresponding tests (in seconds).
Figure 7: Box plot for factorizing the product 10619863 x 10619863
14
Figure 8: Box plot for factorizing the product 10619863 x 16769023
Figure 9: Box plot for factorizing the product 13466917 x 16769023
15
Figure 10: Box plot for factorizing the product 16769023 x 16769023
Factorizing the product 16769023 x 16769023 had remarkably low runtime
results for all of the reduced instances. The test cases for this product had
such low runtimes that patterns can perhaps not be conclusively obtained from
these results. The variance shown in Figure 10 could be caused by unrelated
conditions that varied during the runtime of MiniSAT.
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5
5.1
Discussion
Ordering of the clauses
The results indicate that there is a correlation between the order of the clauses
and the runtime of the MiniSAT solver. By shuffling the clauses, the runtime
in the tested cases could be increased by up to 259000%, corresponding to 1679
seconds (see extrema for FA1 RESTR in Figure 7). This is largely dependant on
how the order of the clauses influence how MiniSAT operates when solving the
SAT instance. In the case mentioned above, the extrema for FA1 RESTR, the
correlation between the number of executed operations and runtime is clear. For
the worst test case, MiniSAT faced 1,492,895 conflicts while only 8,759 conflicts
occurred during the test case with the shortest runtime. Hence, the program
had to solve more conflicts during the execution of the worst test case.
The results showed that the implications of the order had both positive and
negative effects for the runtime of the test cases. The sortings PRODR, REST,
RESTR and FULL produced both the longest and shortest runtimes for all
factorized semiprimes. It would be profitable to use a pattern with variance
if the occasional higher runtimes can be overlooked. That being said, it is
generally preferred to have consistent results in a working environment.
However, changing the order of the clauses does not always affect the results.
If the product clauses are shuffled and placed first among the clauses, the results
do not show any variance. As can be seen in Figure 7 to Figure 9, the maximum
and minimum value for the Productshuffle (PROD) is almost identical to the
mean value. The consistency in the results of PROD indicate that MiniSAT
is not influenced by previous clauses unless they share a literal with the clause
that is being processed. Since there are no literals shared between the product
clauses in any reduction, MiniSAT will not be affected by the order of the
product clauses if they are placed first. In essence, MiniSAT can process product
clauses in any order and achieve consistent results as long as the product clauses
are placed before the rest clauses. This theory is also shown in the graphs by
comparing the box plots for Unshuffled (UN) and PROD, despite the product
clauses being shuffled in PROD they still show similar results as UN for every
test case.
The discrepancy in the results of PRODR compared to PROD could be a
result of how the literals in the product clauses conflict differently with previous literal assignments. If each product clause generates different conflicts
depending on when the clause is processed, the amounts of conflicts will vary
depending on the order of the product clauses. This would mean that the order
of the product clauses does have an impact when they are processed last by
MiniSAT. However, it is not clear from the results if any particular product
clause (for example the clause representing the highest bit of each product) has
a bigger impact on the amount of conflicting literals.
17
5.2
Adder and product implications
As shown in the graphs in Figure 7 to Figure 10, the runtimes varied significantly when different products were factorized. However, for a given product
number the reductions had proportionately similar median values compared to
the differences in their extrema. This implies that the different adder implementations and sortings generally result in similar runtimes. Although with a
small margin, FAN1 persistently showed better results compared to the other
adders, for all the sortings with variance.
5.3
Test discussion
A factor that could have skewed the results were the number of test cases.
In this study, 20 test cases were run for each reduction of the four semiprime
factorizations and this could have led to implications for the resulting data.
Sortings with consistent input data, such as UN, would still show the same
results with more test cases because the sequence of literal assignments in MiniSAT are the same through every test run. This is not the case for the sortings
with variance, these sortings could have given different results over the course
of more test runs. One reason we consider the varying results in this study to
be viable for discussion is because all the test results with high variance have
their first, second and third quartiles within a small interval compared to their
maximum value. The plot for FA2 RESTR in Figure 7 illustrates how small the
box can be compared to the maxiumum, where the three quartiles are equal to
a fourth of the entire interval. This means that a high percentage of the test
results are gathered in a small interval and therefore it is highly likely that the
maximum value is a distinct deviation from the norm.
If this study was to be expanded however, the number of test cases could
be increased to gain more credibility. Also different sorting of the clauses, aside
from the ones used in the study, could be added for comparison. One example
would be sorting the clauses based on the number of literals. This could give
a more clear understanding of the implications that specific clauses orderings
have for the runtime of MiniSAT.
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6
Conclusions
The test results showed that the order of clauses had a definite impact on
the time consumption for solving selected reductions. While FAN1 generally
produced the shortest runtimes among the reductions with variance, all three
of FA1, FA2 and FAN1 had varying results among the other reductions.
There are no evident patterns that lead to better results for every test case
or for a specific circuit structure. Not changing the order of the clauses will
result in consistent runtimes using MiniSAT, which is desirable for avoiding
irregularities. However, it could be profitable to use a pattern with variance if
the occasional higher runtimes can be overlooked.
19
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Figure references
Figure 2
Tree and Array Multipliers. Circuit and System Design Center. Available at:
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Figure 5
4-bit binary full adder Doctronics, Educational Publishing for Design & Technology. Available at: http://www.doctronics.co.uk/images/4008 06.gif
Figure 6
S. Ahmed. 2014. Circuit Diagram of NAND-only Full Adder Available at:
http://students.cs.tamu.edu/tanzir/csce350/handout/files/fulladderNAND.png
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