Computer Arithmetic 4-3 Some of the the slides in this chapter have been compiled using the material provided by the publisher and the lecture notes of the text book’s author Prof. Dave Patterson (CS, UC Berkeley) and Prof. Randy Brynt CPEG 3 2 3 - Fall 2000 (ECE, CMU). 1 Divide: Paper & Pencil 1001 Divisor 1000 1001010 –1000 10 101 1010 –1000 10 Quotient Dividend Remainder (or Modulo result) See how big a number can be subtracted, creating quotient bit on each step Binary => 1 * divisor or 0 * divisor Dividend = Quotient x Divisor + Remainder => | Dividend | = | Quotient | + | Divisor | CPEG 3 2 3 - Fall 2000 2 D I V I D E H A R D W A R E – Use what we have u 32-bit Divisor r e g, 32 - bit ALU, 64- bit Remainder r e g Divisor 32 bits 32-bit ALU “HI” “LO” Shift Left Remainder (Quotient) 64 bits CPEG 3 2 3 - Fall 2000 Control Write 3 Divide Algorithm Remainder 0000 0111 Divisor Start: Place Dividend in Remainder 0010 1. Shift the Remainder register left 1 bit. 2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register. Remainder >= 0 3a. Shift the Remainder register to the left setting the new rightmost bit to 1. Test Remainder Remainder < 0 3b. Restore the original value by adding the Divisor register to the left half of the Remainder register, & place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0. nth repetition? No: < n repetitions Yes: n repetitions (n = 4 here) Done. Shift left half of Remainder right 1 bit. CPEG 3 2 3 - Fall 2000 4 Observations on Divide u Same Hardware as Multiply: just need ALU to add or subtract, and 6 3 -bit register to shift left or shift right u H i a n d L o r e g i s t e r s i n M I P S c o m b i n e t o a c t a s 6 4 - bit register for multiply and divide u S i g n e d D i v i d e s : S i m p l e s t i s t o r e m e m b e r s i g n s , m a k e p o s i t i v e , a nd complement quotient and remainder if necessary – Note: Dividend and Remainder must have same sign – Note: Quotient negated if Divisor sign & Dividend sign disagree e.g., –7 ÷ 2 = –3, remainder = –1 CPEG 3 2 3 - Fall 2000 5 Floating- Point Review u What can be represented in N bits? u Unsigned u 2s Complement - 2N u 1s Complement -2 N - 1 +1 to u fractions .fffff … u But, what about? 0 -1 to 2N to 2 N-1 - 1 2 N - 1 -1 to n n n n n n.f – v e r y l a r g e n u m b e r s ? 9,349,398,989,787,762,244,859,087,678 – very small number? 0.0000000000000000000000045691 – numbers with fractions, e.g., 3.1416 – very small numbers, e.g., .000000001 – very large numbers, e.g., 3.15576 CPEG 3 2 3 - Fall 2000 × 10 9 6 Recall Scientific Notation exponent Sign, magnitude decimal point 23 6.02 x 10 Mantissa -24 1.673 x 10 radix (base) Sign, magnitude u Issues: – Arithmetic (+, -, *, / ) – Representation, Normal form – Range and Precision – Rounding – Exceptions (e.g., divide by zero, overflow, underflow) – Errors – Properties ( negation, inversion ) CPEG 3 2 3 - Fall 2000 7 Floating Point Review u u Representation: ( – 1 )s i g n × – sign, exponent, mantissa: mantissa – more bits for mantissa gives more precision – more bits for exponent increases range × 2exponent How many different numbers can be represented using N bits? CPEG – No more than 2 N – 2 * 2 * 3 2 3 - Fall 2000 bits_in_mantissa * 2 * bits_in_exponent 8 Typical 32 bit Floating Number Representation s CPEG 8-bit exponent 3 2 3 - Fall 2000 23-bit mantissa 9 IEEE 754 floating-point standard u IEEE 754 floating point standard: single precision: 8 bit exponent, 23 bit mantissa – double precision: 11 bit exponent, 52 bit mantissa CPEG mantissa Leading “1” bit of mantissa is implicit Exponent is “biased” to make sorting easier – all 0s is smallest exponent all 1s is largest – bias of 127 for single precision and 1023 for double precision s u m m a r y : ( – 1) s i g n × (1+ mantissa) × 2 e x p o n e n t – b i a s – u exponent – – u s Example: – – d e c i m a l : -.75 = -3/4 = -3/22 b i n a r y : -.11 = -1.1 x 2 -1 – floating point: exponent = 126 = 01111110 – IEEE single precision: 3 2 3 - Fall 2000 10111111010000000000000000000000 10 Floating- Point Arithmetic Representation of floating point numbers in IEEE 754 standard: single precision sign actual exponent is e = E - 127 1 8 23 S E M exponent: excess 127 binary integer mantissa: sign + magnitude, normalized binary mantissa w/ hidden integer bit: 1.M 0 < E < 255 S E-127 N = (-1) 2 (1.M) 0 = 0 00000000 0 . . . 0 -1.5 = 1 01111111 10 . . . 0 Magnitude of numbers that can be represented is in the range: -126 2 (1.0) to 2 127 (2 - 2 23 ) which is approximately: 1.8 x 10 -38 to 3.40 x 10 38 (integer comparison valid on IEEE Fl.Pt. numbers of same sign!) CPEG 3 2 3 - Fall 2000 11 Interpretation of IEEE 754 Floating Point Numbers CPEG 3 2 3 - Fall 2000 12 FP Addition Algorithm For addition (or subtraction) this translates into the following steps: (1) compute Ye - Xe (needed to align binary point) (2) right shift Xm that many positions to form Xm 2 (3) compute Xm 2 Xe-Ye Xe-Ye + Ym if representation demands normalization, then a normalization step follows: (4) left shift result, decrement result exponent (e.g., 0.001xx…) right shift result, increment result exponent (e.g., 101.1xx…) continue until MSB of data is 1 (NOTE: Hidden bit in IEEE Standard) (5) doubly biased exponent must be corrected: Xe = 7 Ye = -3 Excess 8 Xe = 1111 = 15 Ye = 0101 = 5 10100 20 extra subtraction step of the bias amount =7+8 = -3 + 8 4+8+8 (6) if result is 0 mantissa, may need to set the exponent to zero by special step CPEG 3 2 3 - Fall 2000 13 FP Adder Block Diagram Sign Exponent Significand Sign Exponent Significand Compare exponents Small ALU Exponent difference 0 1 0 Control 1 0 Shift smaller number right Shift right Big ALU 0 1 0 Increment or decrement CPEG 3 2 3 - Fall 2000 Exponent Add 1 Shift left or right Rounding hardware Sign 1 Normalize Round Significand 14 FP Multiply Start 1. Add the biased exponents of the two numbers, subtracting the bias from the sum to get the new biased exponent 2. Multiply the significands 3. Normalize the product if necessary, shifting it right and incrementing the exponent Overflow or underflow? Yes No Exception 4. Round the significand to the appropriate number of bits No Still normalized? Yes 5. Set the sign of the product to positive if the signs of the original operands are the same; if they differ make the sign negative Done CPEG 3 2 3 - Fall 2000 15
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