+LJK$VSHFW5DWLR769V)DEULFDWHGE\0DJQHWLF6HOIDVVHPEO\RI*ROGFRDWHG1LFNHO:LUHV
High aspect ratio TSVs fabricated by magnetic self-assembly of gold-coated nickel wires
A. C. Fischer, S. J. Bleiker, N. Somjit, N. Roxhed, T. Haraldsson, G. Stemme and F. Niklaus
KTH Royal Institute of Technology
Osquldas väg 10, 100 44 Stockholm, Sweden
email: [email protected]
Abstract
Three-dimensional (3D) integration is an emerging technology that vertically interconnects stacked dies of electronics and/or
MEMS-based transducers using through silicon vias (TSVs).
TSVs enable the realization of devices with shorter signal lengths,
smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. In
this paper we demonstrate a new manufacturing technology for
high-aspect ratio (> 8) through silicon metal vias using magnetic
self-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enables through-wafer vias with high aspect ratios and superior electrical characteristics. This technique eliminates common issues in
TSV fabrication using conventional approaches, such as the metal
deposition and via insulation and hence it has the potential to reduce significantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications.
Introduction
During the past decades, hybrid integration of IC and MEMS
technology has been dominated by 2-D approaches, resulting in
Multi-Chip Modules (MCM) where different dies are integrated
on a single substrate, and System-on-Chip (SoC) solutions where
different functionalities are merged onto one die. CMOS and
MEMS processing are both well-established and cost-efficient
base technologies that are characterized by short development
times, low fabrication costs and high yields. Separate manufacturing of CMOS integrated circuit dies and MEMS dies and
their subsequent integration into a System-in-Package (SiP)
offers high versatility and low process costs, and thus is an
attractive alternative to SoC solutions. Especially 3D-integrated
System in Package (3D-SiP) solutions, which are based on
vertical chip stacking, are a general trend in many integration
approaches. Not only do 3D-SiPs decrease costs by reducing the
volume and weight of the package, but they also improve system
performance through enhanced signal transmission speed and
lower power consumption which is of importance for various
demanding applications [1, 2]. This is due primarily to the
shorter signal path lengths and lower capacitive, resistive and
inductive parasitic components that are enabled by TSVs [3].
3D-SiP implementations require vertical interconnects through
selected dies in the stack in order to connect their functional
layers. Large development efforts for the realization of reliable
and cost-efficient TSVs are currently ongoing and the first
commercially available devices such as MEMS inertial sensors
and microphones, CMOS imagers and power LEDs successfully
incorporate TSV technology [4–6].
978-­1-­4673-­1965-­2/12/$31.00 ©2012 IEEE
The structure and hence the fabrication of TSVs can be
roughly divided into three major elements: a vertical hole through
the substrate, a conductive core and a dielectric layer acting as an
insulator between conductor and substrate. The exact design of
the via and the fabrication process flow depends very much on
the application.
Typical TSV diameters vary between a few microns [2, 7]
and several hundreds of microns [8, 9]. Basic via designs are
either based on solid or lined metallizations for the vertical
conductor. TSVs can have either straight [7–11] or tapered
sidewall profiles [12, 13] as well as combinations of both [1, 14].
Various methods for the formation of via holes exist and can be
categorized into dry etching [1, 7, 8, 10–14], wet etching [14] and
drilling processes [4]. The majority of TSVs have an aspect ratio
between 1 and 10. The most common techniques and challenges
for the fabrication of the main TSV structures are discussed in
the following sub-sections.
Via Holes — Deep Reactive Ion Etching (DRIE) is by
far the most commonly used technology to form the TSV hole.
DRIE has an excellent process controllability and is capable of
creating high aspect ratio vias with specific sidewall profiles and
topographies. The etch rate of DRIE is aspect ratio dependent
(ARDE) and may cause several topographic imperfections on
the sidewalls such as scalloping, caused by alternating etchand passivation-steps, which results in corrugated sidewalls.
By using state-of-the-art DRIE equipment, these effects can
be minimized [12] and adopted to the demands of subsequent
insulation, barrier and seed-layer deposition steps.
Laser ablation is an emerging low-cost and high-speed process
for drilling TSV holes as it benefits from the absence of any lithographic process steps and is agnostic to different materials. This
results in high process and design flexibility and thus, potentially
lower overall costs compared to DRIE [4, 15]. Laser ablation
however suffers from a high local thermal load, introduction of
crystal defects and particle generation around the perimeter of the
drilled via hole. Additional cleaning steps are therefore required
and reliability issues may arise due to induced stresses on pores
and micro-cracks [15, 16].
Via Insulator — Chemical Vapour Deposition (CVD) is
a well-established CMOS process with moderate temperature
requirements [1, 2, 7, 13] and is therefore the most commonly
used method for a direct deposition of silicon dioxide or silicon
nitride on the sidewalls of the via holes. The use of organic
dielectrics such as Benzocyclobutene (BCB) [9, 13, 17], epoxy-
541
based polymers [8, 13], silicone [13] or Parylene [11] is also
considered as viable option. Polymers, especially low-k types
with a lower relative permittivity compared to silicon dioxide,
are very attractive for the realization of TSVs with improved
electrical characteristics [8]. In addition, polymers can further act
as a buffer for thermo-mechanical stresses caused by coefficient
of thermal expansion (CTE) mismatches [11, 18] as their Young’s
modulus is approximately two orders of magnitude lower as
compared to silicon dioxide or silicon nitride.
Concept of Self-Assembled TSVs
In this work we present the magnetic self-assembly of conductive via cores into through-silicon via holes. Magnetism as a
non-contact force enables a controlled manipulation of ferromagnetic features over long-distances and is insensitive to the surrounding medium and independent of details of the surface chemistry. Magnetic fields can have high energy densities and can influence feature sizes from macro- to nano-scale. These advantageous characteristics are very attractive and have been reported
in various assembly approaches [24]. A proof-of-concept of selfassembled pure nickel-TSVs has been shown by the authors earlier [17]. As depicted in figure 1 a and b, pre-formed ferromagnetic nickel rods are magnetically assembled into deep etched via
holes. For the via insulation the thermosetting polymer Benzocyclobutene (BCB) is used, as shown in figure 1 c. This low-k
insulator material has excellent electrical characteristics and can
be filled void-free into trenches with high aspect ratios [25]. This
method enables high aspect ratio vias with an inherently void-free
conductor and insulator. This method has also been adopted for
the assembly of SMD capacitors into through-silicon holes [26].
Even though the DC resistances of commonly used conductive materials such as copper, gold, aluminum, or tungsten, are
within a very close range to those of ferromagnetic materials like
cobalt, nickel, or iron, there is an enormous discrepancy regarding their performance for high-frequency signal transmission as
depicted in figure 2. Ferromagnetic materials show very poor RF
Silicon
n
Nickel
el
(c)
BCB
B
SiO2
Figure 1: Via formation concept [17]: a) The via hole is formed
by DRIE stopping on a silicon dioxide layer. b) A conductive,
ferromagnetic nickel core is placed in the via hole by magnetic
assembly. c) The remaining hollow space in the via cavity is filled
with the thermosetting polymer Benzocyclobutene (BCB).
conductibility characteristics with sheet resistances that are two
orders of magnitude greater than common TSV conductor materials.
102
Sheet Resistance [Ω/square]
Via Conductor — The via metallization step is the most critical and often most costly part of the via fabrication. Established
processes are electrodeposition of copper [7, 8, 11, 13, 14, 18],
CVD of tungsten [2, 19], CVD of polysilicon [2, 12] and the
use of low-resistivity silicon [10]. Especially electrodeposition of
copper, being a very well-established semiconductor process, is
used by many research groups and implemented in most commercialized devices containing TSVs. Electrodeposition of copper
benefits from widely available tool vendor support and process
maturity as well as being amenable to processing at close to room
temperature, but suffers due to its complexity in terms of process
controllability, reliability and throughput [4]. In particular, high
aspect ratio TSVs with void-free conductive metal cores are difficult to implement [7]. Alternative approaches to plating processes
have therefore been investigated, such as filling with conductive
metal pastes [1, 20, 21], solder [22, 23] as well as the use of wirebonded gold [9].
(b)
(a)
101
100
10−1
Iron
Nickel
Cobalt
Tungsten
Aluminium
Gold
Copper
10−2
10−3
0
20
40
60
80
100
120
Frequency [GHz]
Figure 2: Simulated sheet resistances for various conductive materials in dependence of the frequency. The values for ferromagnetic materials, such as Iron, Nickel, and Cobalt are almost two
orders of magnitude bigger than the values for Tungsten, Aluminium, Gold, and Copper.
In this work we present an automated magnetic assembly process for the fabrication of TSVs that are adopted for the transmission of high frequency RF signals. Two materials are therefore
combined for the conductive via core. Ferromagnetic nickel is
used for the assembly process and a gold layer that is coated on
the nickel wire serves as conductor for the RF signal. Due to
the skin-effect the current density of high-frequency signals in a
542
conductor is largest close to the surface and hence most of the current flows along the outer perimeter of a circular TSV conductor.
Therefore it is sufficient to coat a thin layer of gold on a nickel
core in order realize a TSV with good electrical characteristics
for RF signals.
Wire preparation
The conductive cores of the TSVs are fabricated previous to
the assembly. The electric and mechanical quality of the final via
connection as well as the manufacturability of the wire assembly
is strongly dependent on a thorough preparation of the conductive
via cores. The preparation is divided in two steps, first the coating of a nickel wire with gold by electroplating and second the
cutting of the gold-coated nickel wire to a defined length. Crucial
requirements are perfectly straight nickel wires and a very precise
control of the gold layer thickness. A too thick gold layer would
result in an enlarged diameter of the nickel rods which would then
not fit into the via holes anymore. A distortion of the wires would
have a similar effects since the wires would get stuck half way
into the holes.
In order to ensure a defined fixation and a reliable electrical contact of the wire for the electrodeposition process, a carrier
frame for the wire was manufactured, as depicted in figure 3 a.
The carrier is made of chemically resistant polypropylene (PP)
and holds approximately 2.5 m of nickel wire. The wire that was
used for this experiment was Nickel 270 with a purity of 99.97 %
and a diameter of 35 µm. Prior to the gold-electroplating step,
the native oxide on the surface of nickel wire was removed by a
10 % HCl dip. The gold-coating was performed with the electroplating agent Aurotron H 200 (Atotech GmbH, Germany) at a
deposition rate of approximately 0.3 µm/min.
In order to cut the gold-coated nickel wire into rods of a defined length, a wire cutting process was developed. The carrier
frame with the gold-coated nickel wires was therefore placed on
a carrier wafer. As shown in figure 3 b, the wires were fixated
with blue tape at the outer perimeter of the carrier wafer before
the frame and the excess wire was removed. In order to fixate the
wires on the carrier wafer and protect them from any deformation
R
and burr creation during the cutting process a layer of AZ�
4562
photoresist was spin-coated on the carrier wafer at 1000 rpm for
30 s. As depicted in figure 3 c, the nickel wires were fully embedded in the photoresist matrix. A DAD 320 (DISCO Cooperation,
Japan) wafer dicing tool was used to cut the wires to a length of
350 µm. The accurate alignment of the dicing machine allowed
for perfectly perpendicular cuts and the length of the rods could
be precisely controlled by the step size of the dicing blade. Subsequently the gold-coated nickel rods could easily be released by
dissolving the resist layer with acetone. Since this process allows
for a very precise cutting of many wires in parallel, a large number of nickel rods can be manufactured in a short time, e.g. one
process run of plating, mounting, cutting and releasing produces
approximately 4000 nickel rods.
TSV Fabrication
The detailed fabrication process for the TSVs is depicted
in figure 4 and starts with 350 µm thick double-sided polished,
p-type silicon wafers with a diameter of 100 mm and a resistivity
of 5000 − 8500 Ωcm. A 2 µm thick silicon dioxide layer was
created by thermal wet oxidization at 1100◦ C on both sides. The
silicon dioxide acts both as a hard mask for the DRIE step and
as an electrical insulator for the metal lines, which will finally
connect the via on the front- and back-side of the substrate. A
standard lithography on the front-side of the substrate defines the
circular openings for the vias. The silicon dioxide is dry-etched
by RIE (figure 4 b). As depicted in figure 4 c, a Bosch DRIE
process creates via holes with a diameter of 42 µm and straight
side walls. The etch stops at the silicon dioxide on the bottom of
the cavity. A subsequent thermal oxidation ensures an electrical
insulation of the via sidewalls.
As depicted in figure 4 e, an excess amount of the goldcoated nickel wires is then randomly placed on the front-side
of the substrate. By magnetic manipulation with a permanent
magnet from the back-side, the nickel wires are aligned normal to
the surface (figure 4 f). A lateral movement of the magnet drags
the wires along the surface and forces them into the via cavities
(figure 4 g). For this magnetic assembly process a robotic setup
was devised and constructed based on a wafer handler robot.
a)
b)
Blue Tape
Ni Wire
c)
Photoresist
Dicing
Groove
Ni
Wire
Wafer
Figure 3: After the gold plating (a), the wires are cut by transferring the nickel wires to a dummy wafer (b). The wafer is then spincoated with photoresist (c). Embedded in this protective layer of
photoresist, the wires can be cut with a dicing tool, without the
risk of bending or loosing the wires. (c) shows the top and crosssectional views of a cut nickel wire, still embedded in photoresist.
By dissolving the resist layer the wires can then be released.
543
Via
Formation
Via Filling by
Magnetic Assembly
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
N
S
N
S
(j)
(k)
Via
Contacts
(i)
Silicon
Nickel
Silicon Oxide
Gold
BCB
N
S
Magnet
Figure 4: The TSV fabrication in three main steps: (a - d) Formation of via holes by DRIE. (e - h) Autonomous magnetic assembly of
gold-coated nickel TSV cores and the application of BCB as an insulation layer. (i - k) Opening of the vias on back-side as well as
deposition and patterning of the transmission lines.
Figure 5 shows a schematic depiction of the robot arm that was
modified in order to mount the cubic permanent magnet with an
edge length of 5 mm. This device enables a free movement of
the magnet with three degrees of freedom which can be utilized
to program an assembly motion to drag the nickel wires into
the cavities. Also depicted in figure 5 is a camera which is
mounted directly above the magnet and faces the front-side of the
substrate. It is used to optically inspect the substrate surface and
to monitor the assembly process.
Camera
Wires
The via cavities are subsequently filled with the thermosetR
ting polymer BCB CYCLOTENE�
3022-46 (figure 4 g). In
order to reduce the viscosity of the polymer, the substrate is
placed on a hotplate with a temperature of 60◦ C before the
polymer is manually applied with a syringe. As the polymer is
not spin-coated the resulting polymer layer has a non-uniform
thickness on the order of 100 − 150 µm. The subsequent
hard-curing of the BCB is performed on a hotplate using the
temperature profile according to the manufacturer’s standard
process procedures [27]. The curing procedure was performed in
a vacuum environment at 0.02 mbar in order to prevent any void
formation in the polymer. A grinding and polishing step removes
remaining nickel and BCB from the surface of the substrate
(figure 4 i). A subsequent lithography and RIE of the silicon
dioxide and BCB residues opens the contact area of the via on the
back-side of the wafer, as depicted in figure 4 j. Two consecutive
TiW / Au depositions (50 / 500 nm) on both sides of the wafer
interconnects the nickel/gold core of the via. A lithography,
wet Au etch and dry TiW etch define the transmission lines
(figure 4 k) of the RF test structures.
z
x
Wafer
y
Permanent
Magnet
Robot Arm
Figure 5: Assembly robot setup: The assembly arm consists of a
permanent magnet mounted on an aluminum sheet and a camera
above the magnet.
Experimental Results
Figure 6 shows a scanning electron microscope (SEM) image
of a gold-coated nickel wire. In order to evaluate the thickness of
the electroplated gold layer, a small pit was formed on the wire
surface by focused ion beam (FIB) milling. The gold thickness
was measured to be 1.7 µm. The surface of the gold film has a
rough surface, which is characteristic for electro-deposited layers.
544
Nickel
Gold
Au-coated Ni wire
Figure 6: SEM image of a gold-coated nickel wire. Inset: Crosssection of the Ni/Au interface, generated by focused ion beam
(FIB) milling.
A first unsuccessful fabrication run of non-functional TSVs
was investigated by cross-section grinding and subsequent inspection with a scanning electron microscope (SEM). As depicted in
Figure 7, the lower part of the conductive via core is not in contact
with the metallization on the back-side. The failure was caused by
the DRIE that produced a slightly closing profile of the via sidewalls. As a result, the diameter of the lower part of the via was
smaller than the diameter of the gold-coated nickel rods. This prevented the conductive via core from a complete assembly down to
the silicon oxide membrane. This issue was addressed by an increased etch time and subsequent fabrication runs were successful. Figure 7 indicates that the filling with BCB could be successfully conducted without any visible air-voids or defects after the
complete hard curing procedure. Also, the nickel wire is inherently void-free.
For evaluating the RF performance of the gold-coated
nickel wire TSV, the proposed via structures are employed as
vertical through-wafer interconnections of the micromachined
coplanar-waveguide (CPW) transmission lines implemented on
the front- and back-side of a high-resistivity silicon substrate
(5000-8500 Ωcm) as shown in figure 8. The gold CPW has a
signal line width of 120 µm and a gap of 60 µm, while the length
of the transmission is 2400 µm, thus the unwanted signal coupling between the input and output port is avoided. To extract
the transmission loss from the test structure, a reference CPW
transmission line without any interconnections was fabricated on
the front-side of the wafer. The RF measurement results indicate that the CPW integrated with gold-coated nickel wire interconnections offers an excellent RF performance for a very wide
band from DC to 66 GHz, which is a much larger operation frequencies as compared to other reported TSVs for RF applications [8, 28, 29]. The measured maximum return loss at 66 GHz
is lower than −10 dB, while the maximum insertion loss is better
than −4.62 dB. As compared to the reference CPW transmission
with the same length, a single section of the gold-coated nickel
wire interconnection has an insertion loss of only −0.75 dB.
SiO2
a)
Au
Ni
Si
BCB
Ground
Trace
Signal Trace
b)
Au
SiO2
BCB
Au
Ni
SiO2
Au
Front-Side
Back-Side
TSV
Figure 8: Cross section (a) and top-view (b) of the micromachined
coplanar-waveguide (CPW).
Conclusions
Figure 7: SEM image of a cross section of a TSV with an aspect
ratio of 8. It shows both, a void-free via core and a void-free
BCB-filling.
We demonstrated a novel manufacturing technology for highaspect ratio (> 8) through silicon metal vias based on the magnetic
self-assembly of gold-coated nickel wires. The presented TSV
approach offers an excellent RF performance up to 66 GHz.
545
Acknowledgements
This work has been funded by the European Research Council (ERC) through the Starting Grant (277879). The authors also
would like to thank Umer Shah and Nora Heinig for their collaboration and technical support.
[13]
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