V.Elanangai* et.al. International Journal Of Pharmacy & Technology
Available Online through
www.ijptonline.com
ISSN: 0975-766X
CODEN: IJPTFI
Research Article
IMPLEMENTATION OF FAST SQUARE ROOT CARRY SELECT ADDER WITH LOW
POWER CONSUMPTION
V.Elanangai*, Dr. K.Vasanth
Department of Electrical and Electronics, Sathyabama University, Chennai-119.
Department of Electrical and Electronics, Sathyabama University, Chennai-119.
Email: [email protected]
Received on 05-05-2016
Accepted on 20-06-2016
Abstract
The main design objective in adder design are area, speed and power. Carry Select Adder (CSLA) is one of the fastest
adders which carry out fast arithmetic functions in many data processing processors. However CSLA is not area
efficient since many pairs of Ripple carry adders (RCA) are used to generate partial sum and carry which are selected
by the multiplexers. From the structure of the CSLA, it is clear that there is scope to reduce area and consumption of
power in the CSLA. The result shows that proposed design has occupied less area and consumed less power as
compared to regular SQRT CSLA.
Keywords: CSLA, fast arithmetic function, SQRT CSLA.
I. Introduction
Addition of numbers is performed by an adder circuit in electronics. In modern computers adders are placed in
arithmetic logic unit (ALU). Although adders are used to represent numeric values, the most common adders operate
on binary numbers.
In digital adders the speed of addition is reduced since a carry has to propagate through the adder. Similar to other
circuit designs, the high performance adder design can be approached at different levels. As a result there is always a
tradeoff between the design parameters area, power and speed [1]. There are many ways to design an added. RCA is
more compact but speed is less. Carry propagation is the main concern [3].
This brief is structured as follows. Section II deals with the detailed structure and function of BEC logic and
architecture of the existing square root carry select adder.
Section III presents the structure of the proposed adder. Section IV provides us the implementation results. Section V
is about conclusion.
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II. Existing Square Root Carry Select adder
The basic square-root Carry Select adder has two ripple carry adder with 2:1 multiplexer; the main disadvantage of
regular CSLA is its larger area because of multiple pairs of ripple carry adder. To overcome this Binary- to Excess1(BEC) method is proposed to reduce the maximum delay of carry propagation in final stage of carry save adder [4].
Fig 1 shows that BEC is used in place of RCA in the regular CSLA to get less area and power consumption [4]-[6].
The advantage of BEC logic is lesser number of logic gates than the n-bit Full Adder (FA). To replace the n-bit
RCA, an n+1 bit BEC is required. Fig.2 and Fig. 3 illustrates how the CSLA works basically using mux and 4-bit
BEC. One input of the 8:4 mux is the BEC output and another is (B3, B2, B1, and B0). This produces two outputs in
parallel and the mux selects BEC output or the direct inputs depending on the control signal Cin. The importance of
the BEC logic is area reduction when the CSLA are designed with large number of bits. The Boolean expressions of
the 4-bit BEC is shown below.
Fig.1 Architecture of the Existing CSA.
The function table of 4-bit BEC is shown below.
Table 1: Functional Table of BEC.
Fig.2 illustrations of 2-bit and 3-bit BEC respectively.
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Fig.3 illustrations of 4-bit and 5-bit BEC respectively.
III. Proposed Adder
From the structure shown in fig. 1, there is a scope for reducing the power and area of CSLA. In that we have
replaced RCA with Conditional sum adder (CSA).
Fig. 4 gives us the structure of the proposed square root CSLA.
Fig.5 shows the Circuit diagram of the proposed adder and Fig.6 shows the layout diagram of the proposed adder.
Fig. 5. Circuit Diagram- Proposed square root CSLA.
Fig. 6. Layout Diagram- Proposed square root CSLA.
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IV. Results and Discussions
A. Tabulation
The results of the implementation of various fast adders have been done down. Table 2 shows that the square root
CSLA is fastest and area efficient. Hence conditional sum adder is implemented in square root CSLA. And when
high speed adders are executed using conditional sum adder, square root carry select adder shows better
performance than other adders with less combinational delay time 14.863ns and relatively less number of slices
occupied. Table 3 gives us the amount of power consumed by conventional square root CSLA and Proposed square
root CSLA.
Table-2. Overall Comparison.
16 BIT
ADDERS
RIPPLE
CARRY
ADDER
(CNVNTNL)
CARRY
CARRY
CARRY
SQUARE
SQUARE
LOOK
SKIP
SELECT
ROOT
ROOT CSLA
AHEAD
ADDER
ADDER
CSLA
(CONDITIONAL)
ADDER
(CNVNTNL) (CNVNTNL) (CNVNTNL)
(CNVNTNL)
17
32
56
41
31
AFTER SYNTHESIS
XOR
16
1. NO. OF
SLICES
22
19
22
30
25
25
2. NO. OF I/P
LUT
39
33
39
52
44
43
3. BONDED
IOB
50
50
50
50
49
50
29.388ns
27.814 ns
14.90 ns
14.974 ns
14.863 ns
39
33
52
44
43
25
24
25
28
25
25
3. BONDED
IOB
50
50
50
50
49
49
4.
EQUIVALENT
GATE COUNT
234
198
234
312
267
261
2
2
2
4
4
4
4. DELAY
1. 4 I/P LUT
2. SLICES
OCCUPIED
5. MAX FAN
OUT
29.277 ns
AFTER MAP
39
PLACE AND ROUTE
1. EXTERNAL
IOB
50
50
50
50
49
49
2. NO. OF
SLICES
25
25
25
28
25
25
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Table-3. Power Consumption Comparison.
DIFFERENT
ADDERS
SQUARE ROOT
CSLA USING BEC
POWER
0.220MW
SQUARE ROOT
CSLA USING
CONDITIONAL
0.163MW
SUM
The proposed adder is observed to have less delay time (14.863ns) and low power (0.163mW) consumption
capability if we take the existing adder for comparison. Hence the proposed square root carry select adder using
conditional sum adder is proved to be power and time efficient.
B. Graph
The graph shown in fig 7 proves that when compared to the existing adders the proposed square root csla using
conditional sum adder consumes less power.
Fig. 7. Power consumption of various 16 bit adders.
Fig. 8 Combinational delay path of various 16 bit adders.
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The graph shown in fig 8 proves that the proposed adder has less combinational delay path hence improving the
speed.
V. Conclusion
His paper proposes an architecture to reduce the power and delay time of square root CSLA using conditional sum
adder. Initially all the high speed adders are studied and the square root carry select adder is observed to be an
efficient one. Various adder architectures are also studied and the conditional sum adder is observed to be the
effective. This conditional sum adder is now executed in high speed adders and respective results are obtained.
Front End Results:
The software used for obtaining front end results are XILINX for synthesis and MODELSIM for simulation purpose.
When targeted for XC3s1000-5fg900 for FPGA, the architecture consumed 25 slices of the logic having a
combinational path delay of 14.863ns which is observed to be minimum.
Back End Results:
Since the power obtained using XILINX is not accurate, back end tools called Dschematic and Micro wind are used.
The power results obtained here shows that the proposed architecture consumes 0.163mW of power which is very
less.
As compared to the regular SQRT CSLA the proposed design has reduced power and delay time with only a slight
increase in the area. The proposed adder is observed to have less delay time (14.863ns) and consumes less power
(0.163mW) compared to the existing adder. Therefore the proposed square root carry select adder using conditional
sum adder is proved to be power and time efficient.
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Corresponding Author:
V.Elanangai*,
Email: [email protected]
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