Introduction to Si2 3D-IC Design Exchange
Format Standard for Power Distribution Networks:
Chip-Package Interface Protocol, Version 1.0
Interoperability for 3D Stacked Die Design Flows
Norman Chang, VP and Sr. Product Strategist
Apache Design, Inc. (subsidiary of ANSYS)
DAC June, 2013
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3D-IC Chip-Package Interface Protocol - Goal
•  Power grid analysis with optional package/PCB netlist for DC drop, dynamic
voltage drop, LdI/dt noise, AC analysis (impedance and resonance), and current
density/electromigration for wires, ports, and TSVs
•  Optimization of power distribution networks (PDN) via the interchange of CPIP for
3D-IC what-if analysis and parameterized optimization flow
•  Enabling signal integrity analysis, particularly for jitter analysis of chip-to-chip
communication with vertically stacked-die or through silicon interposer channel
3D Stack
Silicon Interposer Stack
Reusable Die
SoC/Custom Die
Reusable Die 1
TSV
Si Interposer
TSV
Package
2 Innovation Through Collaboration
TSV
SoC/Custom Die
Package
PCB
Chip-Package Interface Protocol - Coverage
•  Unified interface protocol for the following interface definition including
both Power/Ground and Signal ports
–  die <-> die
–  die <-> pkg
–  pkg <-> PCB
•  Compact equivalent circuit in SPICE format for CPIP-compliant models
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The Chip-Package Interface Protocol Need
for Interposer-based Design
Die 1
Die 2
CPIP (die <-> die)
CPIP (die <-> die)
Interposer
CPIP
CPIP (die <-> Pkg)
Package
CPIP (Pkg <-> PCB)
PCB
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The Chip-Package Interface Protocol
Need for Vertically Stacked Die
Die 2
CPIP (die <-> die)
Die 1
CPIP (die <-> Pkg)
Package
CPIP (Pkg <-> PCB)
PCB
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Chip-Package Interface Protocol - Overview
General Info Model Proper<es Signal Ports Power Ground Ports • CPIP Version • Design Name • Units • Info on CPIP-­‐compliant model genera<on such as stack-­‐up, simula<on <me, <me step, command op<ons used, and excita<on seBngs, summary of the model, etc. • CompName PinName ; X,Y loca<on, layer • NodeName ; NetName ; LayerName; SignalPortGroup • PortType (die2die, die2pkg, internal, pkg2die, or other) • All fields same as in signal ports • PadType (power, ground, or other) Innovation Through Collaboration
Example Target Application
•  CPIP-compliant model of a die or dice and CPIP-compliant pkg/PCB model can be
incorporated in a concurrent power integrity simulation of a 3D-IC design
Memory Die (40nm)
Logic Die (28nm)
LEF/DEF/GDS
CPIP-compliant Model
Silicon Interposer Die (65nm)
LEF/DEF/GDS
Package
PKG netlist in CPIP-compliant Model
PCB
PCB netlist in CPIP-compliant Model
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Concurrent
analysis Concurrent 3D-IC Voltage Drop Analysis Example
•  Input multi-die design and corresponding process data (can be of different
technologies), all at once
•  Impact from shared P/G nets and decap in interposer die can be factored into
memory and logic die
Logic Die
LEF/DEF, 28nm tech
Memory Die
LEF/DEF, 40nm tech
Power Integrity
Tool
Concurrent Analysis
Silicon Interposer
LEF/DEF, 65nm tech
Pkg Netlist in
CPIP-compliant model
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CPIP-based Multi-die IR/DvD Analysis Example
•  Most suitable when one die is external without the complete design database
•  CPIP-compliant model is a die model with RLC network and current profile
with a CPIP header, generated by Power Integrity tool(s)
•  Enables simple hand-off and fast turnaround time between design parties
Logic Die
LEF/DEF, 28nm tech
Silicon Interposer
LEF/DEF, 65nm tech
DvD Map of 3
Power Integrity
Tool
CPIP-compliant model
Memory Die
Memory Die
Pkg Netlist in
CPIP-compliant model
LEF/DEF, 40nm tech
Power Integrity
Tool
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- die concurrent analysis
Logic Die
Silicon Interposer
Application of CPIP-compliant Models in 3DIC Test Case
•  Connected in a face2back manner
•  “Top die” connects to “package”
through “bottom die”
•  Bottom die PDN contains TSVs that
connect its M1 to back-side metal,
which connects to top die using
“copper pillars”
•  CPIP-compliant model of package used
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MODEL BASED
CONCURRENT
3D-IC Test Case Description for CPIP-based
Applications
11 Layout view of both die in
concurrent mode; pkg in
CPIP-compliant model
CPIP-ready
model
CPIP-ready
model
Model of top die (CPIPcompliant model) hooked to
bottom die layout; pkg in
CPIP-ready
model
CPIP-compliant model
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Top Die Demand Variation Example of a
3D-IC Transient Analysis with CPIP
Case A: top half of the top die is ac1ve Case B: le4 half of the top die is ac1ve 12 Bottom Die (left) affected by operation of the Top Die (right)
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Summary
•  Current status
Version 1.0 of the PDN standard has been approved by the Open3D TAB and posted as an
Si2 standard
•  Thanks for the hard work of the PDN WG over the past one and a half year
•  Also, thanks to the SRC Interconnect WG for their early exploration of the
3D-IC Interface Standard and for their contribution to the 3D-IC term definition
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Current PDN WG Participants
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Current PDN WG Members
Altera:
ANSYS:
Karthik Chandrasekar ([email protected])
Norman Chang ([email protected])
Aveek Sarkar ([email protected])
Vinayakam Subramanian ([email protected])
Atrenta:
Satish Soman ([email protected])
Cadence:
Peter McRorie ([email protected])
Bradley Brim ([email protected])
GlobalFoundries Ravi Gutala ([email protected])
Helic:
Sotiris Bantas ([email protected])
Intel:
Rob Titus ([email protected])
Michael Zelikson ([email protected])
Invarian:
Jens Andersen ([email protected])
Alex Samoylov ([email protected])
Mentor:
Marko Chew ([email protected])
Qualcomm:
Riko Radojcic ([email protected])
Thomas Toms ([email protected])
TI:
Udaykumar H. ([email protected])
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