IEEE TRANSACTIONS ON COMPIUTERS, VOL. C-23, NO. 2, FEBRUARY 1974
153
Power Minimization Problems of Logic Networks
SHUZO YAJIMA, MEMBER, IEEE, AND KOSAKU INAGAKI
Abstract-As a method for greatly reducing power dissipation in
logic networks, we propose some logic organization techniques for
logic networks. By such techniques, their power dissipation is to be
minimized under certain input conditions, or the average power
dissipation in the whole network should be minimized. A logic network in which these problems are taken into account will be called a
power minimized logic circuit (PML).
In this paper, using so-called asymmetrically power dissipating
elements in which power dissipation varies with on-off conditions,
it is shown that it is possible to considerably reduce power dissipation
in logic networks by only utilzing logic organization methods.
First the power minimization problem of logic networks under
certain fixed input conditions is discussed.
Next a method is presented for synthesizing a PML with asymmetrically power dissipating NAN) elements, and it is proved that
the PML synthesized by this method satisfies the minimum value
of power dissipation under all input conditions. The minimum
number of gates dissipating higher power in an arbitrary singleoutput combinatorial logic network -is zero or one when the output
is 1, and one or two when it is 0. The average power dissipation of
this PML is always theoretically minimal, independent of the occurrence probabilities of input conditions. In practice, the number of
gates would hardly increase very much.
The use of a PML is compatible with the use of low-power logic
elements.
Index Terms-Asymmetrically power dissipating element, LSI,
minimum power realization, NANI) gate, positive (negative) loop,
power dissipation in logic networks, power minimization problem,
power minimized logic circuit (PML), zero power realization.
I. INTRODUCTION
THE development of large-scale integration (LSI) technology is strongly limited by the problem of power
dissipation. Power dissipation constitutes the "heat barrier" which often obstructs the realization of LSI, particularly LSI of fast logic circuits. It causes large installation costs for air-conditioning devices in large computer
systems; furthermore, huge power supplies are also necessary to support such systemis.
If power dissipation of LSI logic circuits is reduced, the
integration scale can be remarkably enlarged; denser
packaging will in turn afford higher operation speed.
In this context, it is important to consider how to minimize the power of logic networks, which we call power minimization problems of logic networks [1], [2]. These probManuscript received September 22, 1972; revised August 12,
1973. This work was supported in part by a Grant from the Science
Foundation of the Mimstry of Education of Japan.
S. Yajima is with the Department of Information Science, Kyoto
University, Kyoto, Japan.
K. Inagaki is with the Department of Electrical Engineering II,
Kyoto University, Kyoto, Japan.
lems include 1) the minimiization of power dissipation of
an actual logic network under certain fixed input conditions, and 2) the mini ization of average power dissipation in this network. This terminology is analogous to the
gate minimization problem. More generally, these problems are to be referred to as power optimization problems;
this term includes the problem of 3) dispersing power dissipation over a logic network. Logic networks in which
these points are taken into account will be called power
minimized logic circuits (PML) and power optimized logic
circuits (POL).
This paper is concerned chiefly with the reduction of
power dissipation in a logic network composed of so-called
asymmetrically power dissipating elements. They are
those logic elements whose power dissipation varies with
their output values. In the following sections we show that
it is possible to reduce power dissipation in a logic network
by the use of logic organization methods alone.
There are two main themes in this paper. The first is
the power minimization problem of a combinatorial logic
network under certain fixed input conditions. These may
correspond, for example, to the resting state of the network. This is discussed in Section IV.
The second is a method of synthesizing a PML with
asymmetrically power dissipating NAND elements [3],
which are of great importance in integrated circuit (IC)
and LSI technology. This method is presented in Section V.
A PML synthesized by this method dissipates theoretically minimal power under all input conditions. In the
case of a single-output PML, the number of gates dissipating higher power is zero or one when its output is 1,
and one or two when its output is 0, whatever combinatorial logic function it may have. The average power dissipation of this PML is always theoreticaHly minimal, independent of the occurrence probabilities of its input conditions. In practice, the number of gates would hardly increase at all, compared with that of the minimum-gate
NAND network.
Sequential networks and actual asymmetrically power
dissipating elements are discussed in Sections VI and
VII, respectively.
A PML will be effective not only for the realization of
LSI of fast logic circuits, but also for ordinary logic networks and for battery-operated logic networks such is
desk calculators or various kinds of equipment in spacecraft. The use of a PML is compatible with the use of low
power logic elements now in common use as a method for
reducing power dissipation in a logic network.
154
IEEE TRANSACTIONS ON COMPUTERS, FEBRUARY
II. POSSIBILITY OF POWER REDUCTION
USING ASYMMETRICALLY POWER
DISSIPATING ELEMENTS
In this section we investigate the possibility of reducing
power dissipation in a logic network composed of so-called
asymmetrically power dissipating elements.
An example is shown in Fig. 1. The combinatorial logic
networks (a) and (b) satisfy the following logic function:
f (xl,2,X3) = XlX2 +
X2X3
1974
(jD- AND
(ai)
Ii>- OR
+ X3X$ + X1X2XI3
It is assumed here that the inputs to the logic networks
are all 0's, which, for example, correspond to the state
that they are not operating. The output value 0 or 1 at
each gate is shown in Fig. 1. We suppose that the power
dissipation at these OR and AND gates for an output 0 is
notably lower than that for -an output 1. In the case of
NOT gates the power dissipation for an output 1 is also
much lower than that for an output 0. Then we notice that
all gates in Fig. 1(a) are not necessarily in a low power
state, but in the case of Fig. 1(b) all gates are in a low
power state. Therefore, assuming these types of gates,
we showed that it is theoretically possible to reduce power
dissipation in an inoperative network by only using the
organization method.
We use the term asymmetrically power dissipating element referring to the logic element whose power dissipation varies with its output values. DTL, RTL, some of
TTL, and MOS logic elements are examples of the actual
circuits which have such characteristics. A high or low
power state of the element is the state that the circuit
dissipates higher or lower power, respectively.
In this paper, we will not consider the restrictions on
fan-in, fan-out, and logic gate levels. The following arguments clearly hold for their duals, too.
III. DEFINITIONS
Let Q denote the set that consists of the two values 0 and
1, i.e., Q = {0, 1 . For an arbitrary given positive integer
n, we consider the Cartesian product Qn = Q x ... x Q.
The members of Qn are 2n ordered n-tuples (xi,-.X.n),
where the ith coordinate xi is a member of the set Q for
every integer i = 1,... ,n. We denote such n-tuples in a
vector form by x. Let X be the set of n variables xi, * *,Xn.
The logic function of n variables is f(x): Qn -+ Q. The
logic sum and logic product of xi and xi are denoted by
xi + xi and x1ix, respectively. The negation of xi is denoted by xi. f-l (1) = { x C Qn f(x) = 1 } and f-l (0) =
{x E Qn f(x) = 0} will be called the on-set and the offset of the logic function f, respectively.
Let ag denote the asymmetrically power dissipating
element g which is in the low power state when its output
is a. It will be depicted as shown in Fig. 2. For example,
an asymmetrically power dissipating NAND element which
is in the low power state when the output is 1, namely,
a 1NAND element, is expressed as shown in Fig. 3. We
sometimes omit the entries 0 or 1 in their symbols when
there is no danger of ambiguity.
-
(b)
Fig. 1. Example of reduction of power dissipation in a combinatorial logic network.
X
~~~or
Fig. 2. Symbols of an asymmetrically power dissipating element
(both are available).
Fig. 3. 1NAND gate.
Organizing a logic network with the minimum power
dissipation when its input is fixed as xo is called minimum
power realization of a logic network under a static input
condition. Under this condition organizing a logic network
with k elements in a high power state is called k-unit power
realization. In particular, 0-unit power realization will be
called zero power realization.
If an m-output logic network which realizes f(x):
Qn Qm is composed of asymmetrically power dissipating logic elements 011gi, - ,-aLgk, and its input condition
is xo, we denote it by F(xo; algi,.--a"gk)
IV. ZERO POWER REALIZATION OF
COMBINATORIAL LOGIC NETWORKS
USING ASYMMETRICALLY POWER
DISSIPATING ELEMENTS
In this section we will consider the zero power realization of logic networks under certain fixed input conditions.
A. Zero Power Realization of Combinatorial Networks Using
OAND, OR, NOT
Proposition 1: Any combinatorial logic network F(0;
0AND, OR, 'NOT) is zero power realizable.
Proof: As f(x) is a combinatorial logic function, it
can be realized by using °AND, °OR, 1NOT without feedback
loops. We will construct one possible network.
155
YAJIMA AND INAGAKI: LOGIC NETWORKS
Under a static input condition 0, we will find a °AND or
0OR element whose output is 1, which disturbs the zero
0
I,
10,
power realization condition. We apply to this element de
0
1
Morgan's law, as shown in Fig. 4. Notice 'NOT elements
,o
1
are canceled out. However, when there is a 1NOT whose
....,
output is also connected to other parts, this 1NOT should
be maintained for these portions. Thus the above-mentioned element can be set in the low power state without
affecting other °AND and °OR elements. The successive application of this method to these elements will finally lead
to the state that all °AND and °OR gates are in the low power
state without contradictions. As the input of a 1NOT eleFig. 4. Transformation by de Morgan's law.
ment is connected with an input terminal or with a oAND
or oOR output, every 1NOT element is in the low power
state, because its input is 0. Hence, any combinatorial
logic network F(O; °AND, °OR, 'NOT) iS zero power real00
Q.E.D.
izable.
01
By the application of this method the total number of
t 1
°AND and OOR gates does not change. Only the number of
10
'NOT gates varies.
(b)
(a)
Let g and gd represent logic elements which realize a
X,X
IXIaO I 1 e0
logic function of exactly two or more variables and its
XOs'2 o, I I lo
dual, respectively. The following proposition holds in the
same manner as Proposition 1.
Proposition 21: Any combinatorial logic network F(Q;
I0
0
09, Ogd, 'NOT) (when g is self-dual, add certain constants)
(d)
(C)
is zero power realizable.
zero
realizable
the
conditions of
5.
power
Fig.
Maps
representing
When arbitrary logic functions are to be realized, it is
F(Ooi,lj; OAND,'OR,'NOT).
of course necessary that g, gd, and NOT constitute a complete set of logic functions.
Next we consider the case where some inputs are l's. value. In particular, in the case of an all-i input condiPermuting input variables, we write
tion, there exists no function of exactly two or more variables which is zero power realizable.
(Xol, .. YXo7,Xll, * Xlj) = (0, * ,01l
5 1),y
When the input condition is fixed and the number of
where {xo,2.. xoj,xj, -.,x,j} - X.
inputs assigned a 1 is j, the number of zero power realUsing subvectors we write
izable functions of n variables is as follows:
,o,.
n
-
Q
x
0
0
E
..
..
(xoi,xi3)
=
..
(Ooilj).
We have the following proposition.
Proposition 3: A combinatorial logic network F(Ooi 1,j;
0AND,OOR,'NOT) is zero power realizable, if and only if each
output satisfies one of the following conditions.
1) If the output is a constant function, it is either 0 or 1
(use a constant 0).
2) If the output is a function of exactly one variable,
it is one of the following functions: xol, * *I,X11) * *
Xij,Xoi,b * **goi.
3) If the output ( fk) is a function of exactly two or
more variables, it satisfies the expression
fk(Ooiyxi)
=
E,
_
constant.
Proof is omitted.
The interpretation of condition 3) of Proposition 3 in
the ease of a logic function of 4 variables X1,X2,X3,X4 is as
follows. Corresponding to the input conditions (0,0,0,1),
(0,0,1,1), (0,1,1,1), and (1,1,1,1), the shaded portions of
each map shown in Fig. 5 should be assigned the same
NzPR
=
2 2-2 +1 + j.
(1)
It is because NZPR corresponds to the number of all possible values which can be written on a map, exclusive of
xil ,..,x,i. Fig. 6 shows the inclusive relation among the
classes of zero power realizable functions, which corresponds to the case that the number of l's in input conditions is successively increasing.
It is readily understood that when the input condition of
any combinatorial logic network F(Oo,ll,;; 0AND,00R,'NOT)
contains j l's, it is at most j-unit power realizable. The
reason is that if j 1NOT elements connected to the input
terminals whose outputs are l's are set in the high power
state, the remaining subnetwork is zero power realizable.
Any combinatorial logic network, which is not zero
power realizable due to the input conditiori containing
l's, can be made zero power realizable by the addition of
the control input xc to this network, as shown in Fig. 7,
where xc = 1 when it is operating and x, = 0 when it is
not operating. However, the output value at the time when
it is not operating has not been taken into consideration.
156
IEEE TRANSACTIONS ON COMPUTERS, FEBRUARY 1974
family
of f (x)
Proposition 5: A combinatorial logic network F(Oo1,j;
where 'g1, .--,'gi are 'negative gates, is zero
power realizable if and only if each output satisfies one
of the following conditions.
1) If the output is a constant function, it is either 0 or 1
(use a constant 0).
2) If the output is a function of exactly one variable,
it is one of the following functions: xol0, .,xo,xxll...xlj,
19,---,'lgj),
Xol *...
Fig. 6.
of zero power
,Xoi.
(3) If the output ( fk) is a function of exactly two or
more variables, it satisfies the expression
fk (Ooi,Xl)
= 1.
(Proof is omitted.)
The result of Proposition 5 is a restriction of that of
Proposition 3. For example, the shaded portions of Fig. 5
should all be assigned l's. When the input condition is
fixed and the number of inputs assigned a 1 is j, the number
NzPR' of zero power realizable functions is as follows:
NZPR'
=
22n-23 + n + 1.
(2)
An inclusive relation similar to Fig. 6 also holds. Logic
functions which are not zero power realizable can be also
x.c Q
made
zero power realizable by the addition of a control
Fig. 7. Zero power realization attained by adding a power control
input.
input.
The interpretation of this realization is found in the duplication of a map. The half portion where x, = 1 corresponds to the original function, and the remaining portion
where xt, = 0 may have any value.
B. Zero Power Realization of Combinatorial Networks Using
°AND,
°OR, °NOT
Proposition 4: A combinatorial logic network F(Ooi 1,j;
°AND,°OR,°NOT) is zero power realizable, if and only if each
output satisfies one of the following conditions.
1) If the output is a constant function, it is either 0 or 1
(use a constant 1).
2) If the output is a function of exactly one variable,
it is one of the following functions: x0o,ll.x
.xl
Xl1, ..* Aj.
3) If the output ( fk) is a function of exactly two or
more variables, it is positive' in xo,,* **,xoi and must also
satisfy the expression
Jk(°i,lj)
=
0.
(Proof is omitted.)
C. Zero Power Realization of Combinatorial Networks Using
'Negative Gates
We assume that any negative function can be realized
by a single gate [5]-[9].
Function
f(x): Qn
Q is positive
(negative)
in
xi
if and
only if
be represented without complemented Xi (uncompilemented
if it positive
xi). A logic function is positive (negative) if and only
(negative) in each of its variables.
it
can
is
V. POWER MINIMIZED LOGIC CIRCUITS
USING NAND ELEMENTS
In this section we synthesize a PML with 'NAND elements. First we will show the necessary and sufficient conditions for zero power realization and 1-unit power realization for output 0 of a single-output combinatorial 1NAND
network.
Next we will present a method of synthesizing a singleoutput combinatorial PML with 'NAND elements. Then
we will obtain the minimum number of high-power elements in a single-output combinatorial logic network.
The result will be stated in Proposition 9. The minimum
number of high-power elements is zero or one when the
output is 1, and one or two when the output is 0, whatever
logic function may be realized. A logic network synthesized
by this method attains minimum power realization under
all input conditions. Therefore, the average power dissipation is always theoretically minimal among those of
other realizations, independent of the occurrence probabilities of input conditions.
In Section V-D we augment this synthesis method and
give an algorithm for minimum-gate realization of a singleoutput combinatorial 1NAND network. Out of many examples only a few of the logic networks, synthesized by
this algorithm, require many more elements in comparison
with networks synthesized without consideration of power
dissipation.
Incompletely specified logic networks and multioutput
logic networks are treated in Sections V-E and V-F, respectively.
157
YAJIMA AND INAGAKI: LOGIC NETWORKS
A. Zero Power Realization of a Combinatorial Network
Composed of 'NAND Elements
Proposition 6: A combinatorial logic function f(x):
Qn > Q of exactly two or more variables is zero power
realizable using 1NAND elements if and only if f(x) can be
expressed in the form
f(x)
= gi +
g(x)
(3)
using some variable xi, where the input condition of xi is 0.
Proof (Necessity): If a logic network attains zero
power realization, then the output of every 'NAND element
must be 1. This means that at least one input to that element is 0. To set the output element in the low power
state, it must be directly fed by some input variable xi,
whose input condition is 0, as depicted in Fig. 8. (The
inputs from other elements are all l's.) Therefore, f(x)
must be expressed in the form (3) using some input variable xi whose value is 0.
(Sufficiency): If f(x) can be expressed as in (3) and
xi = 0, the output element may be set in the low power
state by the organization method shown in Fig. 8.
By virtue of the congruence relation
xjA
=
x xiA
(4)
we can perform a transformation as shown in Fig. 9, so
that all other elements are also set in the low power state.
Consequently, the logic network attains zero power realQ.E.D.
ization.
When all gates are fed by xi, it is evident that when
xi is 0, and whatever values other variables take, the logic
network is in zero power realization condition. This fact
suggests the use of a power control input to a logic network. Namely, when the control input x, feeds all gates,
if we set x, to 0 when the logic network is not operating
and if we set x, to 1 when it is operating, then we can
minimize the power dissipation when it is not operating.
The output value at that time is not, however, taken into
consideration.
Fig. 8. Zero power realizable condition for a logic network composed
of 1NAND elements.
A
0~~~
Xi
Fig. 9. Transformation of a 1NAND gate network by the congruence
relation x,A =
there are no feedback loops, they must be fed by input
variables whose logic value is 0. Therefore, the elements
connected to the output element must be organized as
shown in Fig. 10, and consequently the condition of this
proposition holds.
(Sufficiency): The neighborhood of the output element
can be realized as shown in Fig. 10. If we organize the
logic network that the subnetworks which correspond to
each term of expression (5) are separated from one another,
and perform the transformation depicted in Fig. 9 through
each subnetwork, then the network attains 1-unit power
Q.E.D.
realization for output 0.
Proposition 8: Among the subsets of the off-set f1 (0)
of a combinatorial logic function f(x): Qn + Q of exactly
two or more variables, the subset which is 1-unit power
realizable using 'NAND elements is the one which is the
maximal on-set among the on-set of
H (jl +
* * *
+ xjkj)
(6)
j
B. 1-Unit Power Realization at the Time of Output 0
When the function value of f(x) is 0, xi of Proposition 6 defined from expression (5) of f(x).
Proof: Expression (5) is equivalent to the following:
is constantly 1 and it is dummy for each 1NAND gate, then
we may neglect it in the following discussion. Therefore,
f(x) = SXJi. Xjkj9/(X),
we assume here that a logic network is not zero power
realizable.
+ *-- + X,'k + g9(X).
gj'(X)
Proposition 7: A combinatorial logic function f(x):
Qn Q of exactly two or more variables is 1-unit power
From the result of Proposition 7, when f(x) is 1-unit
realizable using 'NAND elements at the time of output 0 power realizable for output 0, at least one variable among
if and only if f(x) can be expressed in the form
Xj,l * * * Xjki is 0. It means that the value of gj' (x) is 1.
The function f(x) takes the value 0 in the on-set of the
(5) function
f(x) - 2xJ,, ...xikgj(x)
i
f(x) = H [x, + *. + 2i + g,'(x)].
where for each j the input condition of at least one variable
=
among xA, *X
,Xjk is 0.
Proof (Necessity): Since the output value is 0, the The functions #/ (x) are all O's when f(x) is 1-unit power
output element is in the high power state. Hence other realizable for output 0. Therefore, the 1-unit power realelements must all be in the low power state. Provided izable subset of f'-(O) will be expressed by the on-set of
158
IEEE TRANSACTIONS ON COMPUTERS, FEBRUARY
Fig. 10. 1-unit
power
realizable condition for output 0.
expression (6). It is obvious that this on-set should be
Q.E.D.
the maximal one.
We will illustrate this proposition using maps. The portion which is 1-unit power realizable at the time of output
O corresponds to the maximal portion which is to be enclosed in negative loops. A negative loop is a loop on a map
whose Boolean form can be represented by a product of
complements of input variables. As an example, negative
loops in the case of four-variable functions are shown in
Fig. 1 1.
C. Synthesis of a PML Using 'NAND Elements
In this section we present a method of synthesizing a
single-output combinatorial PML with 1NAND elements by
the utilization of a map. The logic network synthesized by
this method attains minimum power realization under all
input conditions. The minimum number of high power
elements in a single-output combinatorial logic network
under an arbitrary input condition is obtained in Proposition 9.
As preparation for the following algorithm, we will define a positive loop on the analogy of a negative loop. A
positive loop is a loop on a map whose Boolean form can
be expressed in a product form of only uncomplemented
input variables. A similar loop is defined as a permissible
loop by Maley and Earle [103. As an example, positive
loops in the four-variable case are shown in Fig. 12.
If the output of a NAND gate is 1, at least one input
must be 0. When it is fed by only input variables, the output is 0 inside the positive loop determined by the product
of input variables, and 1 outside it. According to this, a
1NAND gate is in the high power state inside the positive
loop.
Now we assume that 1NAND gate A is in the high power
state under the input conditions xol and x02, and that 'NAND
gate B is in the high power state under the input conditions x0 and xo3. Thereupon, if we connect gate A to gate
B as shown in Fig. 13, then the output of B is held at 1
at the time of xo0 and x02, when the output of A is 0. At the
time of x0l, as the output of B is originally 1, there is no
effect on it. On the other hand, at the time of x02 the output
of B will be changed from 0 to 1 by the output of A, and
consequently the power dissipation will decrease. This
fact corresponds to the existence of an intersection between the two positive loops which represent the inputs
to those gates on the map. In such a case, by connecting
1974
one gate to the other we can remove the intersection between the two positive loops. We call this manipulation
the inhibition of an intersection between two positive loops.
In the preceding explanation, however, the change in the
output of the network concerned has not been taken into
consideration.
Bearing these things in mind, we present an algorithm
for synthesizing a single-output combinatorial PML with
'NAND elements by the utilization of a map.
Algorithm 1:
1) Examine whether the logic function is zero power
realizable. If the condition of Proposition 6 can hold for
some variable xi when xi = 0, then hereafter we will synthesize a PML neglecting all such variables. At the end
we will feed them to all gates in the network obtained.
2) Examine whether there are 1-unit power realizable
portions where the output is 0. When there are such portions, we will enclose all the portions with negative loops.
Hereafter we will use only positive loops which do not
intersect with the former negative loops. The fact that
the negation of (6) of Proposition 8, >2 x.l... xjki, is composed only of positive loops clearly explains the possibility that the remaining portions of the map can be covered with such positive loops.
3) Look for positive loops which cover the portions
where the output is constantly 0 or 1. This is possible to
do by working successively from smaller ones. Inhibit all
mutual intersections among portions covered by positive
loops. Next, permitting intersections with the above loops,
describe the positive loops which wholly or partly cover
the remaining portions where the output is constantly
1 or 0. Now inhibit all the mutual intersections with the
preceding loops. Repeat this procedure throughout, until
all l's on the map are covered. Each time one loop is made,
draw and connect the 1NAND gate corresponding to it. The
gates which correspond to output 0 and the ones which
correspond to output 1 are separated according to this
synthesis method.
4) Connect the outputs of the gates corresponding to
output 1 to one 1NAND gate. This is the output of the logic
network. It satisfies the given logic function for the reason
as follows. When the given logic function is 0, the outputs
of the 1NAND gates which are connected to the output element are all l's; and when it is 1, only the output of the
gate corresponding to that input condition is 0.
We will apply this algorithm to the following examples.
We will select as large positive loops as possible in each
step.
Example 1: Let us consider the PML of the logic function
f(x1,x2jX3jX4) = X1 + t2X4 + X3X4 + X2X3X4.
The map is shown in Fig. 14(a). Since xi satisfies the
zero power realizable condition, we will ignore it, and use
the map in Fig. 14(b). We draw negative loops around
the 1-unit power realizable portions. These are the hatched
portions of Fig. 14(b).
The smallest positive loop is X2X3X4, in which the output
YAJIMA AND INAGAKI: LOGIC NETWORKS
XIX2
00
Xd,X2
. B_ ~
0001
10
1?
01
o
ol
Xd1X2
001
10
x1Xr2
10
11
00
L
01
10
10
It
159
[rjjj
10 L L I 1
01
C41
10
Fig. 11. Negative loops in the case of four-variable logic functions.
Fig. 12. Positive loops in the
A
case
of four-variable logic functions.
..... t02
X0~~2, Xos3
.._
...._
....
A
I,,X02
8
Fig.
3X4
X
00
01
10
xx2
0o0 o0
11
IJ I2
L
13.
an
F03
intersection between two gates.
X2
0
1O
t
x
00
LI
It
1
01
I
I
Inhibition of
.
10
(a)
L2
ILi
(b)
l
e)
Fig. 14. PML realizing X
is 0. There is no larger positive loop in which the output
is constant. We name the positive ioop x2x3x4 loop A. We
write the letter A in the upper right corner of that square
as in Fig. 14(c). This loop corresponds to the 1NAND gate
with the inputs X2, X3, and X4. Next we will look for the
positive loops which include loop A and 1 entries. The
loop x2x3 is a proper one. Although the loops X2X4 and X3X4
can satisfy this condition, they are included in a larger
positive loop X4. We label these loops X2X3 and X4, B and C,
respectively. The intersections among the loops A, B,
-
2X -3X4
-
(f)
2X3X4.
and C will be inhibited by connecting the output of gate A
to the gates B and C (see Fig. 14(d)).
As all l's on the map have been enclosed with positive
loops, when we connect the gates B and C (corresponding
to output 1) to the 'NAND gate D as shown in Fig. 14(e),
we obtain the PML which realizes the map in Fig. 14(b).
Finally we feed xi to all gates in order to obtain the
PML which realizes the map in Fig. 14(a).
Example 2:
f (xl,x2,x3)
=
XlX2 + X1X3 + X1X3.
.160
IEEE TRANSACTIONS ON COMPUTERS, FEBRUARY
1974
lb)
(a)
Fig. 15. PML realizing x1x2X1x3 -x13.
Fig. 15(a) shows the map of this logic function. This is
neither zero power realizable nor 1-unit power realizable
for output 0.
We draw the positive loops xlxa and xIx2, name them
A and B, respectively, and inhibit the intersections by
connecting gate A to gate B. Next we draw the positive
loops xi and Xs, name them C and D, respectively, and
inhibit the intersections among A, B, C, and D. In order
to encircle the remaining l's, we describe the overall loop
(we call it the unity loop), name it E, and inhibit the intersections by connecting the gates A, B, C, and D to E.
Finally, the gates A, B, and E, which correspond to
output 1, are connected to the 1NAND gate F to complete
the network as shown in Fig. 15(b).
The logic network synthesized by this algorithm obviously attains zero power realization when it satisfies
the condition of Proposition 6, and 1-unit power realization when it satisfies the condition of Proposition 7. If
we exclude the output element, at most one element is in
the high power state in this network under all input conditions. Therefore, when it satisfies neither the condition
of Proposition 6 nor that of Proposition 7, it attains 1-unit
power realization for output 1, and 2-unit power realization for output 0 (including the output element). On the
other hand, a logic network with the output 1 must have
at least one high power element when it does not satisfy
Proposition 6, and with the output 0 it must have at least
two high power elements when it does not satisfy Proposition 7. Consequently, the following proposition holds.
Proposition 9: If a single-output combinatorial logic
where for each j the input condition of at least
one variable among xi,,
,xjk, is 0, then 1-unit
power realization is obtained (Proposition 7);
b) otherwise, 2-unit power realization is obtained.
It is possible to synthesize with 1NAND gates a singleoutput combinatorial PML which attains minimum power
realization under all input conditions.
A logic network synthesized by Algorithm 1 attains the
minimum power realization under all input conditions.
Therefore, if we assume that the power dissipation of a
'NAND gate in the low power state is zero, then we may
conclude that the average power dissipation of that logic
network should always be minimum among those of other
realizations, independent of the occurrence probabilities
of the input conditions.
D. Minimum-Gate Realization
In this section we prove that we can obtain the singleoutput PML of the preceding section with the minimum
number of 1NAND gates only if we select appropriate positive loops in the preceding algorithm. We will also develop
a method for selecting positive loops.
Proposition 10: Regardless of the method to be applied
in synthesizing with the 1NAND elements a single-output
combinatorial PML which satisfies Proposition 9, two
kinds of elements are separated, those which are in the
high power state when the output of the logic network is
0, and those in the low power state when it is 1. There is
no element which is in the high power state for both output
0 and output 1 of the logic network.
network which realizes the logic function f(x): Qn
Q
Proof: Suppose the logic network is not zero power
of exactly two or more variables, is synthesized with
realizable.
When the output of the network is 1, at least
1NAND gates, then its minimum power realization is as
one element connected to the output element is necesfollows:
sarily in the high power state. At most one element is in
the high power state when the output is 1. Therefore, the
1) When its output is 1,
elements which are not connected to the output element
a) if f(x) can be expressed in the form
are all in the low power state.
f(x) = xs + g(x)
On the other hand, when the output of the logic netunder the condition that xi = 0, then zero power work is 0, all elements connected to the output element
realization is obtained (Proposition 6);
must take output 1. So they are all in the low power state.
Therefore, both kinds of elements are separated, those
b) otherwise, 1-unit power realization is obtained.
which are in the high power state when the output of the
2) When its output is 0,
logic network is 0, and those in the low power state when
a) if f(x) can be expressed in the form
it
is 1.
Q.E.D.
f(x) = E.xjl xjk,g,(X)
Such a 1NAND element can exist that is always in the
...
161
YAJIMA AND INAGAKI: LOGIC NETWORKS
low power state for both output 0 and output 1 of the
logic network. But its output is always 1, and it makes no
contribution to the functioning of the logic network. The
elimination of that element with associated interconnection lines does not affect the functioning of the network.
Hence, we may assume that such a 1NAND element does
not exist originally.
We classify the cells of the map into two sets according
to the values of the output, except the portions which are
zero power realizable or 1-unit power realizable for output
0, and divide each set into several disjoint subsets. Among
those finite kinds of divisions, those divisions that realize
a PML will satisfy the condition that each cell set coincide
with the input conditions which correspond to the high
power state of each gate in the PML. A 1NAND gate is in
the high power state only within the positive loop formed
with the input variables or within its portions obtained
by the inhibition of intersections with other 1NAND elements. The preceding algorithm does not contain any
condition about the power dissipation other than that of
Proposition 10 except the above properties of 1NAND elements. Hence the following proposition holds.
Proposition 11: Any single-output combinatorial PML
which satisfies Proposition 9 can be synthesized by Algorithm 1. The number of 1NAND gates can be minimized
only by selection of appropriate positive loops.
We will present an algorithm for minimizing the number
of gates, considering also the interconnection minimization. If there exist several cases in the following algorithm,
the number of interconnections may vary with each case,
although the number of gates is the same in each of them.
We must take into account all these cases that occur.
Algorithm 2:
1) Remove those portions which are zero power realizable or 1-unit power realizable for output 0.
2) Collect those portions which have the same Hamming weight (the number of l's in the input condition)
among the remaining portions and tabulate them into
groups in the order of weight, together with the output
values.
3) Find all input pairs whose outputs are the same,
comparing all the two-groups whose Hamming weights
differ by one. The positive loop which corresponds to the
input having the larger weight can be included by that
which corresponds to the input having the smaller weight.
Write the input value with the smaller weight in the
column H.D.1 (Hamming distance 1) for the one with
the larger weight.
4) Examine which input will include which one by
comparing all the two-groups Whose Hamming weights
differ by two or more. The input with the larger weight
can be included by that with the smaller weight if all
output values are the same when the components which
are different between the two inputs are varied in all possible ways. For example, if the output values corresponding to the input ralues- 111, 10, 01, and 100 are all the
same, then 111 can be included by 100; so write 100 in the
column H.D.2 of 111, and mark off 110 and 101 in the
column H.D.1 of 111 with oblique lines.
5) After the examination of all pairs, if there are inputs
which cannot be included by other inputs, mark them with
asterisks. The positive loops corresponding to them are
essential.
6) Begin with the input with the largest weight. If
there is only one input with a smaller weight which can
include it, encircle this input; examine whether this is
marked with an asterisk; if it is not, mark it with an asterisk. Check off the ones having been included by it with
check marks. If there are several inputs which can include
it, the number of gates is generally fewer when the input
with an asterisk is selected than when it is not selected.
The selection of the input with no asterisk, however, may
lead to the realization of the PML with the same number
of gates, and the number of connections may be fewer in
this case than otherwise. The consideration of all cases
is needed. Going through the table to the bottom, when
all inputs are marked with an asterisk or a check mark,
these manipulations are finished. The reasons we select
larger positive loops are that this selection will surely lead
to the realization with fewer gates and that the number of
interconnections to inhibit intersections are sure to be
fewer.
7) Select the inputs with asterisks for positive loops;
let those with check marks be included by the positive
loops which correspond to the encircled inputs in their
rows; and synthesize the PML by Algorithm 1.
Example 3:
f (xI,X2,x3)
=
X1 + X2f3 + X2X2.
We make a table as described in Step 2) (Fig. 16(a) ) after
the consideration of Step 1). The input 000 is excluded,
as it satisfies the condition of Proposition 7.
We apply Step 3). The input 111 can be included by
110 and 101. The inputs 110 and 101 can be included by
100, 010, and by 100, 001, respectively.
We apply Step 4). There are pairs up to the Hamming
distance 2 in this example. The input 111 can be included
by 100. We mark off 110 and 101 in the column H.D.1 of
111 with oblique lines.
We mark those inputs which are not included by other
inputs with asterisks as in Step 5). The inputs 011, 100,
010, and 001 are marked in this case.
Next, by the application of Step 6), we begin with 111.
The input 111 can be included by 100. Encircle it in the
row of 111, and mark the row of 100 with an asterisk. Encircle 100 in the rows 110 and 101. The inputs 111, 110,
and 101 are checked off. As all inputs are marked with an
asterisk or a check mark, the manipulation is finished.
Example 4:
f(xlIx2lx3)
=-
1X3 +
X2X3.
162
IEEE TRANSACTIONS ON COMPUTERS, FEBRUARY 1974
H. D.
OUTPUT INPUT
I
101
.'
0 1
*
100°
*
0 10
001
1
)
o
i,
v
1I
1
H. D.2
I1 _v X5, ot010o
1 0
0
1
1
_
(a)
OUTPUT INPUT
O
111
o
110
101
0
1
01 1
0
100
010
1
H. D. 1
i
110,
o,
*
E
"
,
*
I001
1
1
1
v
*
*
000
000
(bl
XIX2
00 01
x,x2
10
11
00 01
11
EB
0
B
A
B
0
A
(c)
1
A
A
10
A
(d)
Fig. 16. Selections of positive loops.
The positive loops are determined as shown in Fig.
16(b). Fig. 16(c) shows the map of these positive loops.
If we choose as large positive loops as possible as explained
in Examples 1 and 2, the logic network requires seven
gates including the output element (see Fig. 16(d)). In
the case of Fig. 16(c), however, it is sufficient to take five
gates.
We examined the cases of three-variable logic functions.
It is known that 223 = 256 logic functions of three variables can be divided into 80 equivalence classes according
to the permutations of input variables [11]. As the result
of the comparisons of their PML's and the networks in
the catalog given by Hellerman [12], we could obtain the
following data. Among the 80 logic functions,
The number of logic networks whose power dissipation can be reduced is
68
Among these the number of logic networks whose
number of gates never varies is
56
The number of logic networks whose number of
gates increases by one is
11
The number of logic networks whose number of
gates increases by two is
1
Besides, on the assumption that the occurrence probabilities of input conditions are all the same, the number
of those logic networks is 38 whose average power dissipation is reduced by more than 25 percent. As to the
number of interconnections and gate levels, using the
method developed in this paper, they increase by 0.76
line per gate and 0.75 level per network, respectively, in
comparison with the results obtained by Hellerman. The
number of logic networks whose gate level times power
dissipation is reduced by more than 20 or 25 percent is
24, or 14, respectively. The power dissipation will be reduced even more drastically in the cases of more comnplicated logic functions.
E. Incompletely Specified Logic Functions
The preceding algorithms can be easily extended to the
PML's of incompletely specified logic functions. If unspecified portions correspond to forbidden inputs, they
may be regarded as 0 or 1 arbitrarily, and intersections
with other positive loops may be admitted. We may specify
them, so as to lessen the number of gates. If the inputs
corresponding to unspecified portions are permitted, it
is generally better to assign 1 to them. However, when
they are 1-unit power realizable for output 0, we appropriately assign either 0 or 1 to them.
F. Multioutput Logic Functions
We will extend the preceding algorithms to the case of
a multioutput combinatorial logic network. Let f(x) =
(Afi(x)...f (x)): Qn + Qm represent a completely specified multioutput combinatorial logic function.
We may obtain a positive loop when every output is
constant in it, excluding the portions where all outputs are
either zero power realizable or 1-unit power realizable for
output 0. Notice, in this stage, that the outputs in zero
163
YAJIMA AND INAGAKI: LOGIC NETWORKS
Xi
0
I
Fig. 17. Example of a multioutput PML.
y
c ombinator i al
circuit
zZ
r
oelay
Fig. 18. Schematic diagram of a sequential logic network.
power realizable portions may be regarded as 0 or 1 arbitrarily, because the zero power realizable output 1 can
be obtained by feeding the corresponding input variables
to the output element. We inhibit all the mutual intersections among the positive loops. Each output function is
realized by connecting all 'NAND gates corresponding to
its output 1 to an output 1NAND gate. A zero power realizable output 1 is obtained by feeding corresponding input
variables to the output element.
There are cases in which we can save power dissipation
or gates or interconnections.
1) If the off-set of one logic function can coincide with
the off-set of one 1NAND gate when positive loops are selected, then select this 1NAND gate and take it for the
output of this logic function.
2) If the output of one logic function fi is always 1
when the output of some other logic function fi is 0, then
we may have such possibility. (Notice that if fc-'(1) D
fj-1 (O), then fi-1 (0) C fr-1 (1).) Suppose that logic function fi is 1-unit power realizable for output 0 in some portions, and that only logic functions fil, * ,fJk, whose offsets are all included by the on-set of fi, require the 'NAND
gates corresponding to these portions. In this case, if we
utilize the output of fi for the inputs to fjl,', ,fjk,, then
we can save power dissipation or gates corresponding to
these portions.
We will prove that we can minimize power dissipation
in a multioutput combinatorial network if the network
is organized in the ways stated above.
Power dissipation at output elements is fixed when
output functions are given. Excepting output elements, a
logic network thus organized has at most one high-power
element under any input condition. If we can reduce
power dissipation at some element other than output ones
by utilizing some output element, then, from Proposition 9,
such an element must correspond to zero or 1-unit power
realizable portions of that output function. Since output 1
at the output element cannot reduce power dissipation
-
at other elements, only output 0 is available. We can reduce power dissipation if we can save such 'NAND elements
by utilizing the output of some output element. To this
end, when the output of this output element is 0, the
outputs of the output elements to be fed by this output
element must be all l's.
As to the interconnections, if the union of the off-sets
of some output elements coincides with the union of the
off-sets of some elements other than output ones, we can
generally have interconnections by utilizing the outputs
of these output elements in place of the outputs of such
elements. However, gate levels often increase.
Example 5 (Fig. 17):
f,(X1,X2,X3)
=
ilX2 + X1X3
f2(X12X2jX3) = Xl + X2 + XS.
In this case the portions 000, 010, and 100 are excluded,
because fi is 1-unit power realizable for output 0 and f2
is zero power realizable. First we select positive loop xlx3,
where the outputs of f, and f2 are both constant. We name
this positive loop A and make a corresponding 'NAND
gate for loop A. Next we select positive loops x1X2 and
X2X3, name them B and C, respectively, draw corresponding 1NAND gates, and inhibit all mutual intersections among
A, B, and C by connecting A to B and C. Function f2
coincides with the output function of gate C. Therefore
take this output for function f2. Next select positive loop
x2, name it D, draw a corresponding 1NAND gate, and inhibit all mutual intersections by connecting A, B, and
C to D. Function f' is obtained by connecting A, C, and
D to a 'NAND gate E.
VI. SEQUENTIAL LOGIC NETWORKS
A sequential logic network can be represented as shown
in Fig. 18. Various cases may occur, depending on various
state assignments. Even if the inputs are fixed, a sequential
network may operate autonomously.
164
IEEE
TRANSACTIONS ON COMPUTERS, FEBRUARY 1974
C
(o)
J
0
K
,
(b)
Fig. 19. Master-slave J-K flip-flop synthesized with 1NAND gates.
To the combinatorial logic portion of a sequential network the former discussions are of course applicable. For
example, a sequential network which does not operate
autonomously is zero power realizable by using 0AND, °OR,
1NOT when the input conditions are 0, provided the initial
state is assigned 0.
A sequential network can be regarded as a multioutput
combinatorial network with feedback loops from its outputs to its inputs. Therefore we can, in principle, synthesize a PML of a sequential network using 1NAND elements in the same way as mentioned in Section V, provided the state assignments have been already determined.
In the case of a master-slave J-K flip-flop composed of
1NAND elements, the number of elements in the high power
state is three out of nine, when the clock input C = 0
(Fig. 19 (a)). We can minimize the number of elements in
the high power state to two when the clock is 0 by the
modification shown in Fig. 19(b). Therefore our method
may reduce the power dissipation in registers which might
ordinarily be considered to be very difficult.
VII. ACTUAL ASYMMETRICALLY POWER
DISSIPATING ELEMENTS
Resistor-transistor logic (RTL), diode-transistor logic
(DTL), some of transistor-transistor logic (TTL), metal
oxide semiconductor (MOS) logic circuits, etc., are typical
asymmetrically power dissipating elements. °AND, °OR,
'NOT or their duals can easily be made of these elements.
It would be effective to utilize properly positive and negative logics.
We will show some actual data taken from catalogs.
The DTL used in the IBM 360 has the power ratio 37/23
mW [13]. Other examples are in DTL 64/14 mW (Signetics SP337A, SP377A, SP387A), in RTL 6.5/0.5 mW
(Motorola MC928), and in TTL 67/1.5 mW (Signetics
SP314A, SP317A, SP370A, SP380A, SP381A) and 0.78/
0.24 mW [14].
In the case of a MOS integrated circuit a sufficiently
complex negative function can be realized by a single gate.
The discussions in Section IV-C are readily applicable.
VIII. CONCLUSION
We have discussed in this paper some solutions for the
power minimization problems of logic networks, which
have the potential of greatly reducing power dissipation
in logic networks.
In particular, we have established a method of synthesis of a PML using 1NAND elements; achieved minimum
power realization under all input conditions; and consequently minimized average power dissipation, independent
of the occurrence probabilities of the input conditions.
In practice, the number of gates would not increase significantiy in most cases. It is likely that this synthesis
method can be widely applied. This method is easily modified into a computer-oriented algorithm.
The method of synthesizing a PML, taking fan-in,
fan-out, the number of gates, interconnections, gate
levels, etc., into consideration, will have to rely on such
techniques as integer programming (IP) [15]. In this
case the occurrence probabilities of input conditions will
become a point of discussion.
One disadvantage of a PML would be the fluctuation
of power consumption. This, however, will scarcely come
into question when a PML is composed of 'NAND elements,
because in this case the number of high power elements
is at most m + 1 in an m-output combinatorial network.
An increase in fan-in may result in excessive complexity
in the gate circuit. It may also greatly raise power dissipation. These difficulties can be avoided by the use of
gate elements whose power dissipation does not greatly
increase with fan-in.
We have also found the minimum-gate method of synthesizing a PML whose power dissipation is minimum
with 'negative gates, and have minimized the number of
165
YAJIMA AND INAGAKI: LOGIC NETWORKS
gates. The discussion is highly parallel with that of 'NAND
gates [4].
There are also possibilities of reducing power dissipation in the case of complementary MOS (CMOS) [16],
although in this case the models are somewhat different.
Our development of the power minimization problem
passed through three stages. We thought at the starting
point that if power is supplied while logic networks are
operating and not supplied while they are not operating,
we could greatly reduce their power dissipation. This approach was based on the knowledge that logic networks
in computers do not operate very efficiently, although the
various techniques of parallel processing or multiprocessing
have been employed in computers. We have shown elsewhere [1], [2] the approximate percentage of the reduction of power dissipation in a computer when power.controlling circuits are employed. A similar method for reducing power dissipation in LSI memories has recently
been published by Greene [17].
At the second stage of our development we noticed that
appropriate logic organization using the asymmetrically
power dissipating elements will greatly reduce power dissipation without the utilization of any power controlling
circuits.
At the third stage of our development, using 1NAND
elements, we succeeded in the minimum power realization for any input conditions, where at most m + 1 gates
will dissipate higher power, thus indicating the possible
realization of "cool-headed" computers in the future.
ACKNOWLEDGMENT
The authors wish to express their thanks to their colleagues in Yajima's laboratory for their helpful suggestions
and discussions. They are also indebted to Dr. T. Ibaraki
of Kyoto University and Dr. Y. Kambayashi of the University of Illinois (now with Kyoto University) for the
generalization of theories and for presenting them circuit
examples. Dr. Kambayashi proposed in his private letter
a method of synthesizing a PML with 'NAND elements.
He utilized a lattice whose elements are the terms obtained by factoring the map disjointly. The result of Section V was obtained with this as a clue.
REFERENCES
[1]
[2]
[31
[4]
[5]
S. Yajima and K. Inagaki, "Power minimization problems of
logic networks" (in Japanese), Institute of Electronics and
Communication Engineers of Japan, EC71-70, Mar. 1972;
Trans. (D) Inst. Electron. Commun. Eng. Japan, vol. 56-D,
pp. 115-122, Feb. 1973.
S. Yajima and K. Inagaki, "Power minimization problems of
logic networks," in Proc. 1st USA-Japan Computer Conf.,
pp. 552-558, Oct. 1972.
K. Inagaki and S. Yajima, "Power minimized logic circuits
using NAND elements" (in Japanese), Institute of Electronics
and Communication Engineers of Japan, EC72-18, Sept. 1972;
Trans. (D) Inst. Electron. Commun. Eng. Japan, vol. 56-D,
July 1973.
K. Inagaki and S. Yajima, "Power minimized logic circuits
using negative gates" (in Japanese), Institute of Electronics
and Communication Engineers of Japan, EC72-50, Jan. 1973.
R. F. Spencer," MOS-complex gates in digital systems design,"
IEEE Comput. Group News, vol. 2, pp. 47-56, Sept. 1969.
[6] Y. T. Yen, "A mathematical model characterizing four-phase
MOS circuits for logical simulation," IEEE Trans. Comput.,
vol. C-17, pp. 822-826 Sept. 1968.
[7] T. Ibaraki and S. MVuroga, "Synthesis of networks with a
minimum number of negative gates," IEEE Trans. Comput.,
vol. C-20, pp. 49-58, Jan. 1971.
[8] T. Ibaraki, "Gate-interconnection minimization of switching
networks using negative gates," IEEE Trans. Comput., vol.
C-20, pp. 698-706, June 1971.
[9] K. Nakamura, N. Tokura, and T. Kasami, "Minimal negative
gate networks," IEEE Trans. Comput., vol. C-21, pp. 5-11,
Jan. 1972.
[10] G. Maley and J. Earle, The Logic Design of Transistor Digital
Computers. Englewood Cliffs, N. J.: Prentice-Hall, 1963.
[11] M. A. Harrison, Introduction to Switching and Automata Theory.
New York: McGraw-Hill, 1965.
[12] L. Hellerman, "A catalog of three-variable or-invert and
and-invert logical circuits," IEEE Trans. Electron. Comput.,
vol. EC-12, pp. 198-223, June 1963.
[13] E. M. Davis et al., "Solid logic technology: versatile, highperformance microelectronics," IBM J., pp. 102-114, Apr.
1964.
[14] M. P. Xylander, "Low-power bipolar technique begets lowpower LSI logic," Electron., vol. 45, pp. 80-82, July 31, 1972.
[15] S. Muroga and T. Ibaraki, "Design of optimal switching networks by integer programming," IEEE Trans. Comput., vol.
C-21, pp. 573-582, June 1972.
[16] F. Leuenberger and E. Vittoz, "Complementary-MOS lowpower low-voltage integrated binary counter," Proc. IEEE, vol.
57, pp. 1528-1532, Sept. 1969.
[17] F. S. Greene, "Power reduction techniques for LSI memory,"
IEEE Comput., vol. 5, pp. 31-39, Jan./Feb. 1972.
Shuzo Yajima (M'66) was born in Takarazuka, Japan, in December 1933. He received
the B.E., M.E., and Ph.D. degrees in electrical engineering from Kyoto University,
Kyoto, Japan, in 1956, 1958, and 1964, re-
spectively.
i From 1958 to 1960 he worked on the development of the first digital computer
KDC-1 of Kyoto University. In 1961 he
joined the faculty of Kyoto University as a
Research Associate in the Department of
Electronics, where he became a Lecturer in 1963. In 1967 he became
an Assistant Professor in the Department of Electrical Engineering
II, Kyoto University. Since 1971 he has been a Professor in the Department of Information Science, Kyoto University, engaging in
education and research in logic circuits, switching, and automata
theory. In 1964 he was awarded the Inada prize by the Institute of
Electronics and Communication Engineers of Japan.
Dr. Yajima is a member of the Institute of Electronics and Communication Engineers of Japan, the Information Processing Society
of Japan, and the Japan Association of Automatic Control Engineers.
Kosaku Inagaki was born in Osaka, Japan,
on March 30, 1949. He received the B.E.
degree in electronics engineering from Kyoto
University, Kyoto, Japan, in 1972. He is now
a graduate student in the Department of
Electrical Engineering II, Kyoto University.
He has been studying the power minimization problems of logic networks since his
undergraduate days. His current research
interests include logic circuits and switching,
automata, and information theory.
Mr. Inagaki is an associate of the Institute of Electronics and
Communication Engineers of Japan.