664
PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1964
independent of the length of the operands and
is equal to the time required by one digital
position. The rules of operation and block
diagram of a signed-digit adder for one pair
of digits are shown in Figure 1. Here ti is
called the transfer digit and may assume the
values 1, 0, and -1; Wi is called the interim
sum digit and may assume one from the sequence of values: (-Wmax, ... , -1, 0, 1, .... ,
w max) . In the case of minimal redundancy,
Wmax = amin - 1 is chosen; in all other cases
(a > amin), Wmax is chosen from the range
ami n - 1
~
Wmax
~
a-I
Previous publications present a detailed description of signed-digit number systems!, and
the general rules for variable-precision and
Si
5'+1
ADDITION (TWO STEPS)
ICAl
Z 1+ Yi = tt i-I +
t _1 = 0
'
t i-, = I
Wd
If
IZ,+Yils. Wmax
if
Zi +Y, ) Wmax
ti -I = -I if Z i + YI < - Wmax
I(8)
Si = Wi +
til
SUBTRACTION: chang_ lign of
Yi
if
Yi "0
Figure 1.
and add
Rules of Signed-Digit Addition
significant digit operations2 , on which this paper is based.
2. Application of Signed-Digit Arithmetic
The elimination of carry propagation removes a fundamental constraint of digital arithmetic units and necessitates a reconsideration
of all arithmetic algorithms. The most importtant new aspects of signed-digit (to be abbreviated "s-d" from now on) arithmetic are:
1. the addition time of a parallel adder consisting of any number of cascaded identical
digit-adder packages is (logically) constant;
2. the most significant digits of the product
(as well as of the quotient) are generated first
and may be processed further before the less
significant digits become available;
3. the addition (and subtraction) algorithms
apply to operands of an arbitrary multiple precision (arbitrary length with respect to the
length of the adder) : the most significant sections are added first and may be immediately
processed further;
4. the multiplication and division algorithms
are identical both for single- and multiple-precision operands;
5. in floating-point arithmetic the application
of a special digit value ~ (the space-zero) to
designate non-significant positions allows the
implementation of normalized significant digit
arithmetic3 ;
6. the non-significant digit value (spacezero) 0 may be employed to determine the completion of a multiple-precision significant digit
algorithm; in this case the lengths of the operands may be unknown at the beginning of the
algorithm.
A rather novel arithmetic processor may be
constructed if these properties of s-d arithmetic are utilized. The properties (2) and (3)
permit the elimination of temporary storage of
intermediate results in a complex algorithm;
right shifts are not employed, and the flow of
operand and result digits is only in one direction (to the left) , resembling signal flow
through gate networks. The properties (3),
( 4) and (6) cancel the distinction between the
implementation of single and multiple-precision
algorithms in an arithmetic processor and allow the completion of an algorithm to be de-
From the collection of the Computer History Museum (www.computerhistory.org)
SYSTEMATIC DESIGN OF CRYOTRON LOGIC CIRCUITS
tected by an inspection of the operands. Property (5) permits the inclusion of significant
digit arithmetic while retaining all advantages
of the number system and without changing
the algorithms. Finally, property (1) permits
the assembly of fixed-time adders of any length
from identical building blocks (without any
carry-Iookahead or similar logic structures);
this feature promises convenient assembly and
restructuring of arithmetic processors for
hardware implementation of complex algorithms in a variable structure computer4 • The
cost of the various innovations, when compared
to a parallel binary arithmetic unit, is found
in the greater complexity of the individual digit
adders and in the increased storage requirements (for the same precision of operands)
due to the redundancy of the number representation.
A further important consideration in the
definition of a practical signed-digit arithmetic
processor is its compatibility with the widely
employed conventional binary number system.
The potential application of s-d arithmetic in
the VCLA Variable Structure Computer 5 established the need for a binary-compatible signeddigit arithmetic. In such an arithmetic the
s-d arithmetic processor accepts binary as well
as s-d operands and produces s-d results.
Furthermore, a reconversion algorithm is provided which allows the reconversion of s-d
numbers to conventional binary forms either
in the signed-digit or in a conventional binary
arithmetic processor. The following sections
describe a set of algorithms for a binary-compatible s-d arithmetic and outline the implementation of an aritlh"TIetic processor which employs these algorithms. The algorithms are
applicable to any radix r=2k, with k ~ 2; the
specific description will be given in terms of the
radix r=8. An adaptation for a decimal-compatible signed-digit arithmetic is also quite
evident.
3. Structure of One Digit-Adder
It is evident that any maximal-redundancy
radix r s-d number system, with the allowed
digit values ranging from - (r-1) to r-l, includes all allowed digit values (0 to r-l) of
the conventional number system with the same
radix. The prefixing of an individual sign to
each digit then will convert a conventional
665
number to an s-d number of the same algebraic value, in which all digits carry the same
sign as the conventional number. The conversion in this case requires no arithmetic and
is executed simultaneously for all digits.
A binary number may be interpreted as a
number of radix r=2 k (k ~ 2) by grouping the
binary digits into groups of k bits each. The
values of individual digits are then in binarycoded form. Consequently, a sign-and-magnitude form of a binary number becomes a radix
2k maximal-redundancy s-d number (with
all digits sharing a common sign) by means of
an interpretation of digit grouping. Any
register which provides storage for a radix 2k
s-d number will be able to store the binary
number as an s-d number. Since both positive and negative digit values occur in one s-d
number, it is necessary to choose the representation for negative digit values. Sign-andmagnitude and complement forms both may be
employed within each digit; the complement
with respect to 2k+l is a generally convenient
choice. Table I shows the "16's complement"
coding of digit values for radix 8.
The otherwise unused bit pattern 1000 is employed to designate the non-significant spacezero 0. The choice of representation for negative digit values determined the rule for digitwise subtraction, which is implemented as the
addition of "16's complements" of the subtrahend digits to the digits of the minuend.
The addition table for first step of a radix 8
digit-adder is presented in Table II.
The second step of addition generates the
sum digit of value Sj = '-Vi + tie The spacezero 0 (pattern 1000) is detected by a special
TABLE I: CODING OF DIGIT VALVES FOR
RADIX 8
Value
Code
Value
0
+1
+2
+3
+4
+5
+6
+7
0000
0001
0010
0011
0100
0101
0110
0111
-1
-2
-3
-4
-5
-6
0
".
~T'-
From the collection of the Computer History Museum (www.computerhistory.org)
Code
1000
1111
1110
1101
1100
1011
1010
1001
666
PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1964
TABLE II: FIRST-STEP ADDITION TABLE
FOR RADIX 8 (MAX. REDUNDANCY)
Zl +Yi
Wi
t i-l
Zi +Yi
Wi
t i- l
+14
+13
+12
+11
+10
+9
+6
+5
+4
+3
+2
+1
+1
+1
+1
+1
+1
+1
-14
-13
-12
-11
-10
-9
-1
-1
-1
-1
-1
-1
TU
nv
I 1
T.L
-...,Q
+7
+6
+5
+4
+3
+2
+1
0
-1
+6
+5
+4
+3
+2
+1
0
+1
0
0
0
0
0
0
0
-7
-6
-5
-4
-3
-2
-1
-6
-5
-4
-3
-2
-1
0
+1
-6
-5
-4
-3
-2
-1
IQ
~1
-1
0
0
0
0
0
0
logic circuit at the input of the digit-adder. It
is always entered as the value zero (0000) into
the adder. This conversion allows the use of
the same digit-adder for both "conventional addition" and "significance addition" modes; in
the latter mode the output of the digit-adder is
forced to space-zero 0 (pattern 1000) if either
one or both input digits were space-zeros. In
"conventional addition" mode the 0 digits may
be employed to mark the end· of a variablelength number; in this case, the output is set
to 0 only when both input digits are spacezeros. Conventional addition without use of
the space-zero values is also possible.
An inspection of Table II shows that an
ordinary four-bit (modulo 16) binary adder
will generate three correct bits of the interim
sum Wi. The correct value of the leftmost
(sign) bit and of the outgoing transfer digit
t i- I is computed by a separate logic circuit. To
add the incoming transfer digit ti to the interim
sum Wi one of two methods may be chosen:
either a second pass to add ti is made through
the same 4-bit adder which was used to compute
Wi, or a separate ± 1 circuit (carry-propagate
and borrow-propagate arrangement over 4
bits) is employed. A detailed study and comparison of these two methods is currently in
progress. l l
4. Addition and Subtraction
A convenient range for the signed-digit processor is the fractional range 1 > X > - 1 in
which the value X of an n-digit number x composed of the digits X1 X:2 ••• Xn is:
n
X == ~ Xir- i
i == I
Overflow occurs when Ito I == 1 is generated by
the adder position i==l; therefore the range in
,x:hich overfiO\"'1 ,XliII never be indicated is
n
n
~ (r-2)r-i~ X ~ - ~ (r-2)r-i
i==l
i==l
In the "significance addition" mode the spacezero digit 0 enters the digit adder as the value
zero, but the output of the digit adder is forced
to the space-zero by the special circuit which
senses 0, and is enabled by the "significance addition" command. In this case, the addition Xi
+0 will generate It i- l l==l when IXil==r-l, and
ti-I=O otherwise, while si==0 will always hold.
The result will be rounded to the precision of
the shorter operand. The roundoff by means
of 0 digits will be without bias if every digit
value is assumed to occur with equal probability. The maximum magnitude of the discarded
part is Emax==r- i (r-1) _r-n when it consists of
the digits xi, Xi+h' .. Xn' This value is reduced
(at the cost of additional logic) to Emax==r- i (r/
2) _r- n by executing Xi + 0 as Xi+ (-I- r/2)
whenever Xi =1= 0. The sign of ±r/2 is chosen
to be the same as the sign of Xi; either sign is
acceptable for Xi == O. In either case, roundoff
has been implemented as a part of addition and
executed concurrently at the level of individual
digits. In the "conventional addition" mode, 0
is always entered as value zero, and the digit
adder output is forced to 0 only where both input digits have the value 0. The result retains
the length of the longer operand.
In a floating-point system the exponent is
represented by a signed-digit integer of desired
range which is held at the left end of the fraction. All fractions are kept in normal form and
non-significant positions are filled with 0
(space-zero) digits. There is at least one 0 at
the right end of every fraction. When leading
zeros develop in a fraction, it is normalized by
From the collection of the Computer History Museum (www.computerhistory.org)
667
SYSTEMATIC DESIGN OF CRYOTRON LOGIC CIRCUITS
Z
s-d augend
Y
s-d addend
digit sums
Zi+ Yi
interim sum digits
Wi
transfer digits
ti
digit-adder output Wi + ti
conventional sum
S
S'
significance sum
==
.6 0 7 4 7 5 ~
.2 7 1 5 ~ ~ ~
4 7 6 11 7 5 0
416 1 150
o 101100
.5 1 7 0 1 5 0
.5 1 7 0 1 5 t'J
.5 1 7 0 ~ ~ ~
Note: the value ~ enters the adder as the value
o in forming the digit sums Zi+ Yi'
Figure 2.
Addition Example (Radix 8)
left shifts and a corresponding decrease of the
exponent; significant digits are lost. Overflow
is corrected by the transposition of the radix
point of the result one position to the left and
an increase of one in the exponent; the fraction
gains one significant digit. Only one exponent
is needed with multiple-precision fractions,
since the exponent serves as the index of the
relative position of the leftmost digit Xl of the
fraction. Further details of floating-point addition have been presented in a previous paper.2
5. The Pack-Add Algorithm and Normalization
The "pack-add" algorithm is a variation of
the usual "clear-add" algorithm. It is applicable in several aspects of maximal-redundancy
s-d arithmetic. The packed form x* of the
s-d number x retains the algebraic value of x,
but has only r+ 1 possible digit~values:~·.-~{cT'"i"'-l,
... , 1, 0, -1). "Pack-add x" is implemented
as the addition followed by an immediate subtraction of ± 1 to the n-digit fraction x. The
addend ±1 is represented by the n-digit fraction c, in which all digits have the value Ci ==
± (r-1), plus an incoming transfer digit tn
== ± 1. Simultaneously the overflow transfer
digit to == ± 1 is discarded, thus subtracting
± 1 from x + c+ t n ; as a result the algebraic
values of x and x* remain equal. The signs of
Ci and tn must be the same as the sign of the
leftmost digit Xl in order to guarantee Itol == 1;
if Xl == 0, both signs of Ci and tn are allowable.
The sign of Ci which has been employed in the
algorithm is designated as the dominant sign.
When x contains one or more ~ digits at its
right end, the leftmost ~ digit (xn+! == ~) will
generate til == ± 1 as the result of the addition
of en+!, which is executed as + (r-1.)
the "significance addition" mode .
+~
in
After the execution of one pack-add algorithm, digits of the opposite (non-dominant)
sign may have only the magniture 1. Furthermore, any pair of these opposite sign digits of
unit magnitude will be separated by at least
one digit; at least one of the separating digits
will be a non-zero digit with the dominant sign.
The minimum separation increases by one digit
for every successive application of the pack-add
algorithm. These properties facilitate the· formation of multiples of s-d multiplicands and
divisors in the multiplication and division algorithms.
The application of the pack-add algorithm
also permits the elimination of pseudo-normal
s-d operands. There exists a class of maximal-redundancy s-d numbers of the same algebraic value which assume the forms )( == .16
... ~, and x==.02 ... t'J, with the worst case
being x' == .177 ... 77 t'J, and x == .000 ... 0 1 t'J,
in which the form x' is pseudo-normal. The
pseudo-normal form satisfies xl#O, but fails to
satisfy a minimum magnitude requirement for
its algebraic value; it also presents an incorrect
count of significant digits.
An exact rule for the recognition of normal
forms is required in maximal-redundancy s-d
arithmetic. An application of the pack-add
algorithm to a pseudo-normal form will cause
the appearance of leading zeros and permit
further normalization of the operand. A convenient definition of a normal form is that one
s-d operand
Z
.6074 7 5 t'J
packing addend
.7777 7 77
C
15703
16 147
digit sums
Zi + Yi
5103641
interim sum digits
Wi
1 1001 1 1
transfer digits
ti
.6 104 7 5 1
digit-adder output Wi + ti ==
.6 1 04 7 5 t'J
packed form
Z* ==
Notes: significance addition is employed and
the overflow transfer digit to is discarded to obtain Z*.
The second application of the pack-add
algorithm will yield the form Z** ==
.570475t'J without negative digit values.
Figure 3. Pack-Add Algorithm Example (Radix 8).
From the collection of the Computer History Museum (www.computerhistory.org)
668
PROCEEDINGS-F ALL JOINT COMPUTER CONFERENCE, 1964
of the following conditions should be satisfied
byx:
IXII ~ 2;
Xl . +1, and X2 ~ 0;
Xl = -1, and X2 S 0;
X2 = ~ with any value of Xl'
The magnitude range of non-zero normal forms
x is given by
1 - r-n
~
IXI
~
r2 (r-1) + r-
n
where Xn is the least significant digit of x. The
...nIYl"1"YI<:Il
.&"' .... .L.&. ... ~.1.
fA",n'\
.LV..L ~.I.~
Af
V..L
f-h'"
.f",nnf-;"."..
\,I.l..I.c.;
.L~ ",vll.l.VJ...1
n n 1.,,,,,
V a.1Uv
V
..£~
-
1\
V
.: ....
~o
uniquely represented by Xl = 0 and ~ == ~.
Evidently, other definitions of normal forms
may be convenient under different circumstances.
Still another property of the pack-add algorithm is the elimination of all opposite-sign
digit values, which is a method of reconversion
into the conventional binary form. A digit
with the opposite signs survives a pack-add operation only if there was a zerO' digit at its left;
the new form will contain an opposite-sign
unit value digit in the former position of this
zero digit. Consequently, the longest string of
zero digits ending with an opposite-sign digit
at its right determines the number of pack-add
operations needed for a reconversion; k+1 operations are needed when this longest string
contains k zero digits. The worst case will require n-1 pack-add operations for an n-digit
form which has n-2 zeros separating non-zero
digits Xl and Xn with unlike signs; however,
the average number of operations required for
complete elimination of opposite-sign digits will
be considerably lower.
6. Multiplication
An important property of signed-digit multiplication is the availability of the most significant product digit in its final form after the
first two steps of the iterative mUltiplication
algorithm. Given the radix r s-d multiplicand
X and multiplier Y (with digits Yh Y2, ... Yn),
the algorithm is :
pW = r [p(j-l) + X Yj], with j = 1, 2, ... , n;
where P<o) is an initial augend, and p(n) ==
p<o) + XY is the product2. Only left shifts are
employed in this algO'rithm. For maximal redundancy radix 8 multiplication, the multiplier
digits Yj are recorded sequentially into digits
y'j such that 4 ~ y'j ~ -4 holds. The recoding generates a digit y'o (value 0, +1, or -1) ;
therefore P<O) == rXy'o is specified. The value
of y'j is a function of the values of Yb Yj+1' and
of the sign of yj+:2 during the j-th step of multiplication.
In binary arithmetic, high speeds of multiplication can be attained by cascading carrysave adders 6 to form a multiple-operand adder
which sums several mUltiples (+ 2i) X of the
binary multiplicand X at once and produces a
partial product in stored-carry form. The final
product is obtained by entering the stored-carry
form of the product into a carry-propagate
adder. The multiple 2 iX are obtained by leftshifting the multiplicand X. Signed-digit adders may be similarily cascaded to add several
operands at once. In this case, m-1 adders
wil be required to form the s-d sum of m s-d
operands; evidently, a carry-propagate adder
is no longer necessary. The last remaining
problem is the formation of the multiples
(± 2i) X of the s-d multiplicand X. Two
cases must be distinguished here.
In the first case, X is delivered to the s-d
processor in conventional binary sign-andmagnitude form; the multiples 2 iX of the magnitude are obtained by left shifts of X before
entering it into the s-d adder. For the radix
8, the multiples 2X and 4X will be obtained by
one-bit and two-bit left shifts of X; the multiple
3X is computed by adding X to 2X in the s-d
adder and storing the result (now in s-d
form) in a separate register. With a binary
multiplicand X and the stored multiple 3X, a
single addition in a 2-input s-d adder will account for one radix 8 multiplier digit y'j. For
multiplication using m radix 8 multiplier digits
at once, m signed-digit adders must be cascaded; the partial product is generated in s-d
form.
In the second case, the multiplicand X is in
s-d form a one-bit left shift will not yield the
s-d form of 2X because adjacent radix 8 digits
may have different signs. Multiple-forming
circuits 2 may be applied to generate 2X and 4X ;
however, a more general solution is provided
by the use of one more adder to add in the
negative digits separately from the positive
digits. Since the weight of the leftmost bit in
From the collection of the Computer History Museum (www.computerhistory.org)
SYSTEMATIC DESIGN OF CRYOTRON LOGIC CIRCUITS
the radix 8 digit Xi is -8, this bit may be considered as having the weight +1 in the digit
x" i-I of a negative sign-and-magnitude octal
number X", while X without the -8 weighted
digits remains a positive sign-and-magnitude
octal number X', where X==X' .+ X" holds.
Now X' and X" may be shifted bitwise and
4X' + 4X" or 2X' + 2X" added to pO-I) by the
use of two cascaded s-d adders, or by using
the same s-d adder twice.
We observe that with the above discussed
approach, an arrangement of two cascaded s-d
adders will handle two multiplier digits at once
for a binary multiplicand X, and one digit at
once for an s-d multiplicand X. When more
than two s-d adders are cascaded, it is possible to use a cascade of m> 2 adders for m
multiplier digits at once in case of a binary X,
and for m-1 multiplier digits at once for a
signed-digit X, if the s-d multiplicand X is
converted to its packed form X * prior to the
multiplication. The application of the packadd algorithm to -I- X leaves ± 1 as the only
digit value of the opposite sign in X *; the
number of successive applications is equal to
the minimum separation (in digits) between
any two opposite sign (± 1) digits. A single
s-d adder is sufficient to add all m-l mUltiples
of the opposite sign unit digits of X*, when the
s-d multiplicand X is packed m-2 times before placed into the multiplicand register as X *.
In conclusion, it is observed that the cascading of s-d adders differs from the cascading
of carry-save adders for binary multiplication
in several significant aspects. First, the carrysave structure serves as a special=purpose adder
for multiplication only and requires a carrypropagate adder to generate the .final result.
The s-d cascade is composed of fully complete
s-d adders which may be used separately for
independent operations when fast multiplication is not required. Furthermore, the radix .8
division algorithm uses the same s-d adder arrangement as the one-multiplier-digit algorithm
for multiplication.
The roundoff of a product is implemented by
concluding the algorithm when the required
number of product digits has been generated.
Significant digit multiplication ~,8 employs the
"conventional addition" mode for each step of
the algorithm; the number of significant digits
669
in the product is determined by a sequential
scanning of both operands 2. Exponents in a
floating-point multiplication are handled in the
usual manner.
7. Division
The most convenient method of division in
signed-digit arithmetic is the algorithm described by Robertson 7, in which the representation of the quotient is redundant and the value
of the next quotient digit is selected by comparing approximate magnitudes of the divisor
and the partial remainder. One quotient digit
qj is generated during each step of the division
algorithm, which consists of an iterative sequence of left shifts and additions or subtractions:
R(j) == r [R(j-I) - X qj] , with j==1, 2, ... , n
where X is the divisor, R (0) is the dividend
(satisfying IR(O) 1 < k 1 X I, with k to be specified) , R(n) is the remainder, the RW for n>j>O
are partial remainders, and n specifies the required precision of the quotient 2.
For radix 8 signed-digit division, the allowed
values of the quotient digits qj may be chosen
to be in the range 4 ~ pj ~ -4. In this case
the Ip.ultiplication algorithm and the division
algorithm are interchangeable when R(j) is substituted for pm, and -qj replaces the recoded
mUltiplier digit y'j. The entire preceding discussion of implementing multiplication applies
to division as well and will not be repeated
here. The important difference is that the
multiplier digits y'j were available, while the
quotient digits qj must be determined before
the next partial remainder RW can be computed.
The quotient digits qj is determined by comparing the magnitude of the number R', consisting of the first three digits and the temporary overflow position i==O of the partial
remainder R (-Ij, to the magnitudes of the numbers X' 0, X'17 X' 2 X' 3 consisting of the same
digits (i==O, 1,2,3) of the multiples Xj2, 3Xj2,
5Xj2 and 7Xj2 of the normalized divisor X
respectively. The magnitude of the quotient
digit will be Iqj 1 == g, where g is the subscript
of the least test number X' g which satisfies the
test condition:
From the collection of the Computer History Museum (www.computerhistory.org)
670
PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1964
if all four test numbers fail to satisfy the above
condition, Iqj I == 4 is to be chosen. The sign
of each nonzero qj is chosen to be such that the
sign of the term X qj is the same as the sign
of the partial remainder R (j-1) .
The divisor X is required to be packed and
normalized; in this case the analysis of the required precision of comparison1 shows that the
positions i == 4, 5, ... , n may be disregarded
in the choice of quotient digits. The initial
condition which is to be satisfied by R(O) in
order to apply the division algorithm without
quotient overflow is that before the first left
shift
IR'I<IX'ol
must hold, where R" consists of the digits i==O,
1, 2, 3 of the number R(O) -Xq1' When Iq1i
~ 3 is chosen, the above condition is known to
be satisfied; the selection of IqII ==4 indicates
a possible quotient overflow. A convenient
solution to the overflow problem in floatingpoint division (employing no right shifts) is to
repeat the selection of IqII once more (before
the first left shift) when IqII -4 is indicated.
If Iqll ~3 is indicated, the correct magnitude of
ql is the-,sum of both indicated values, and the
left shift is executed. If the second selection
is again Iq11 ==4, then Iqo I == 1 is recorded (qo
is the quotient overflow digit) and the procedure is continued until an indication of Iq11 ~3
allows the first left shift. After this initial
range adjustment, one quotient digit will be
generated during each step of the division algorithm.
In the implementation of division, the multiplication hardware can be used for the required
test subtractions which determine the quotient
digits. Three digits of X/2 (designated as
X'o) are obtained by displacing all bits of the
first three digits of the packed and normalized
divisor X one binary position to the right.
Since 2X and 3X are available, the other tests
(if necessary) are performed by first obtaining
X'o ± R' (add if signs of X and R(j-l) differ,
subtract otherwise) and then separately adding to this result the required digits (positions
i==O, 1, 2, 3) of X, 2X, and 3X. This method
will yield one radix 8 quotient digit for every
addition, employing the one-digit multiplication
arrangement supplemented by the comparison
circuitry.
Significant digit division 3,8 follows the same
rules as multiplication, which was discussed in
the preceding section.
8. Reconversion to Binary Forms
Several feasible methods exist for the reconversion of s-d numbers into the conventional
form; the specific choice depends on the system
relationships of the s-d arithmetic processor.
One method is the previously discussed repeated application of the pack-add algorithm.
This method requires a variable number of
steps, and is essentially a serial radix 8 borrowpropagation method with sensing of the completion of all borrow chains.
Another method of reconversion employs a
borrow-propagation circuit which accepts the
three positively weighted (+4, +2 and +1)
bits of each radix 8 digit as bits of a binary
operand and the negatively weighted (-8) bit
as a binary borrow into the (+1) position of
the octal s-d digit which is immediately to the
left. Negative numbers will appear in "two's
complement" form. An end-around borrow
connection will give the result in binary "one's
complement" form, which is readily converted
to the sign-and-magnitude form. The "-1"
circuits which add the negative transfer digit
to the interim sum in every digit adder may be
interconnected for this purpose, or a separate
borrow circuit may be employed. Any desired
amount of borrow-lookahead may be incQ,rporated in this arrangement; borrow-completion
sensing may also be used.
Finally, the s-d number may be entered as
a pair of binary operands with opposite signs
into a conventional binary adder when it is
available in the computing system. The positive operand is composed of the positively
weighted bits of all s-d digits, while the negative operand consists of the negatively weighted
bits.
9. Conclusion
Signed-digit arithmetic is characterized by
an affinity for variable-length operations with
floating-point and significance-arithmetic options. Special carry-acceleration circuits are
completely eliminated, and the space-zero value
From the collection of the Computer History Museum (www.computerhistory.org)
SYSTEMATIC DESIGN OF CRYOTRON LOGIC CIRCUITS
implements some control functions at the level
of individual digit adders instead of at a central
control location. For instance, explicit information on the length of operands and results
is not required. The logical complexity of individual digit adders is consequently increased.
For example, a preliminary design of a radix 8
digit-adder with the separate transfer addition
circuit indicates that it requires between 2 and
21;2 times as many logic circuits as a ripplecarry radix 8 (three-bit) conventional adder.
A special control circuit is also required to detect the presence of the space-zero digit values
(~) at adder inputs. The modular nature of
digit-adders is expected to be especially suitable
for microelectronic systems. One radix 2k , or
radix 10 digit-adder offers a standard building
block of considerable complexity which is suitable for micro-electronic implementation. An
arithmetic processor with specified performance characteristics then will be constructed as
an array of the standard building blocks. Each
digit adder is an arithmetic unit of limited capabality in the specified processor. The extent of central control functions is reduced and
"one-of-a-kind" logic circuits are eliminated.
A second novel and potentially useful property of s-d arithmetic is the order in which
the digits of results are produced for the elementary set of algorithms: addition, subtraction, multiplication and division. The most
significant digits of the results always appear
first and may be processed further without
waiting for the less significant digits to be
computed. Furthermore, only left shifts are
employed in these algorithms, and the digits of
the operands and results "flow" in one direction-to the left, while the rate at which they
are produced depends on the number of digit
adders which are available. Complex algorithms may now be implemented by an array
of digit adders without the need for intermediate storage of results and in an asynchronous manner, with the space-zero values serving
to indicate completion of the various elementary algorithms. Both aspects of s-d arithmetic which were mentioned above and methods
of failure detection are now being investigated
for potential application in the restructurable
computer system. 5
671
10. Acknowloogements
The Variable Structure Computer at UCLA 5
has provided the stimulus for the development
of this paper. The author wishes to acknowledge many informative discussions with Professors G. Estrin and B. Bussell. Concurrent
investigations of other types of signed-digit
arithmetic by J. L. Drayer 9 and by R. W.
Baker 10 have contributed supporting information on the feasibility of signed-digit arithmetic
processors. A detailed study of the logic design
of the binary-compatible s-d adder has been
conducted by D. M. Kimble. l l
1. AVIZIENIS, A., "Signed-Digit Number Representations for Fast Parallel Arithmetic,"
IRE Transactions on Electronic Computers
EC-10 (1961), 389-400.
2. AVIZIENIS, A., "On a Flexible Implementation of Digital Computer Arithmetic," Information Processing 1962, C. M. Popplewell, editor, (North-Holland Publishing
Co., Amsterdam, 1963), 664-670.
3. METROPOLIS, N., and ASHEN HURST, R. L.,
"Significant Digit Computer Arithraetie,"
IRE Transactions on Electronic Computers
EC-7 (1958), 265-267.
4. ESTRIN, G., "Organization of Computer
Systems-The Fixed Plus Variable Structure Computer," Proceedings of the Western Joint Computer Conference 17 (1960),
33-40.
5. ESTRIN, G., BUSSELL, B., TURN, R., and
BIBB, J., "Parallel Processing in a Restructurable Computer System," IRE Transactions on Electronic Computers EC-12
(1963), 747-755.
6. MACSORLEY, O. L., "High-Speed Arithmetic
in Binary Computers," Proceedings of the
IRE, 49, No. 1., (January 1961), 67-91.
7. ROBERTSON, J. E., "A New Class of Digital
Division Methods," IRE Transactions on
Electronic Computers EC-7 (1958), 218222.
8. ASHENHURST, R. L., and METROPOLIS, N.,
"Unnormalized Floating Point Arith-
From the collection of the Computer History Museum (www.computerhistory.org)
672
PROCEEDINGS-FALL JOINT COMPUTER CONFERENCE, 1964
metic," Journal of the Association for
Computing Machinery 6 (1959), 415-428.
9. DRAYER, J. L., "Implementation of SignedDigit Arithmetic," M. S. Thesis, University
of California, Los Angeles, 1964.
10. BAKER, R. W., "A Study of the Organization of a Signed-Digit Arithmetic Unit,"
M. S. Thesis, University of California, Los
Angeles, 1964.
11. KIMBLE, D. M., "Implementation of BinaryCompatible Signed-Digit Arithmetic in a
Restructurable Computer System, HM. S.
Thesis, University of Calif()rnia, Los
Angeles, 1964.
From the collection of the Computer History Museum (www.computerhistory.org)
A TRANSFLUXOR ANALOG MEMORY USING
FREQUENCY MODULATION*
Walter J. Karplus and James A. Howard
Department of Engineering
University of California
Los Angeles
tant place as magnetic logic and memory devices in digital computer applications. The
extension of this technique to analog systems
has been proposed from time to time, but no
fully satisfactory transfluxor analog memory
has been described to date.
I. INTRODUCTION
The accurate storage of a continuous voltage
has always proven to be a difficult and challenging problem to the designers of electronic analog systems. Most modern analog computer installations include a number of "sample-hold"
devices, utilizing high-quality operational amplifiers in combination with special electronic
switching circuitry. In such units the voltage
is stored as charge on a capacitor, so that leakage and grid currents must be extremely carefully controlled to permit long-time storage
with high accuracy. Recently introduced hybrid
computer systems have placed an additional
requirement upon the analog memory unit:
economy. For example, in the discrete-spacediscrete-time hybrid computer system now un~
der development at UCLA, 1,000 sample-hold
circuits will be required in order to accommodate 1,000 parallel digital-analog channels.
Furthermore, hold times of several minutes are
desired. Under these conditions conventional
capacitor-type analog memories become economically unfeasible. These considerations have
stimulated a search for a rapid, accurate and
economic analog memory and have resulted in
the development of the FM-transfluxor unit described in this paper. Since their introduction
by Rajchman1 ,2 in 1955, multiaperture magnetic devices (MAD) have assumed an imp or-
* This
In essence, a transfluxor is a ferrite core
with at least two holes-the major and the
minor aperture. In memory applications, advantage is taken of the fact that an electrical
signal applied to the major aperture effects a
change in the magnetic field in the entire core.
Provided certain geometrical criteria are satisfied, it is then possible to sense the magnetic
condition of the core by means of an electrical
signal applied to the minor aperture, without
affecting the magnetic field about the major
aperture. If it is desired to store analog variables, it is necessary to provide for the uninterrupted read-out of a continuous electrical voltage. This in turn necessitates that the sensing
signal be applied continuously and that it be
suitably modulated by the setting signal about
the major aperture whenever a change in
the stored information is desired. Suggested
approaches to analog memories can be conveniently classified as amplitude-modulated,
phase-modulated, or frequency-modulated, as
determined by the manner in which the setting
signal is made to affect the sensing signal.
work was supported in part by the National Science Foundation under Grant G-24888.
673
From the collection of the Computer History Museum (www.computerhistory.org)