Q3: A 4-bits Universal Shift register is shown as below: S1 S2

Q3:
S1
0
0
1
1
S2
0
1
0
1
Behavior
Hold Current Value
Shift left
Shift Right
Parallel Load
A 4-bits Universal Shift register is shown as below:
Parallel Outputs
Parallel Inputs
Q4-a (i) Case 1: Sequence 0,1,2,3,4,7,0
Q2
0
0
0
0
1
1
1
1
Circuit:
P.S
Q1
0
0
1
1
0
0
1
1
N.S
Q1
0
1
1
0
1
X
X
0
Q0
1
0
1
0
1
X
X
0
FF Inputs
T2 T1 T0
0
0
1
0
1
1
0
0
1
1
1
1
0
1
1
X
X
X
X
X
X
1
1
1
Q0
0
1
0
1
0
1
0
1
Q2
0
0
0
1
1
X
X
0
Q2
0
1
Q1Q0
00 01 11
0
0
1
0
X
1
T2= Q1Q0
10
0
X
Q2
0
1
Q1Q0
00 01 11
0
1
1
1
X
1
T1= Q0+Q2
10
0
X
Q2
0
1
Q1Q0
00 01 11
1
1
1
1
X
1
T0= 1
10
1
X
Q4-b (i) Case
Q4-a (i) Case 2: Sequence 0,1, 3,4,7,0
P.S
N.S
Q2 Q1 Q0 Q2 Q1 Q0
0
0
0
0
0
1
0
0
1
0
1
1
0
1
0 X X X
0
1
1
1
0
0
1
0
0
1
1
1
1
0
1 X X X
1
1
0 X X X
1
1
1
0
0
0
FF Inputs
T2 T1 T0
0
0 1
0
1 0
X
X X
1
1 1
0
1 1
X
X X
X
X X
1
1 1
Q4-a (ii) Case 2: Sequence 0,1, 3,4,7,0
Q2
0
1
Q2
0
1
Q1Q0
00 01 11
0
0
1
0
X
1
T2=Q1
00
0
1
Q1Q0
01 11
1
1
X
1
10
X
X
10
X
X
T1=Q0+Q2
Q2
0
1
00
1
1
Q1Q0
01 11
0
1
X
1
T0=Q0’+Q1+Q2
Circuit:
10
X
X
Q8: Solution 1 State table P.S. input N.S. output
Q1 Q0 X Q1 Q0 Z 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 0 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 1 0 J‐K1 J1 K1 0 X 0 X 1 X 0 X X 1 X 1 X 1 X 1 J‐K0 J0 K0 0 X 1 X X 0 X 0 X 1 X 0 0 X 1 X K‐maps J1 Q1Q0\X 00 01 11 10 J1=Q0X' Z Q1Q0\X 00 01 11 10 Z=Q1Q0X 0 0 1 X X 1 0 0 X X 0 0 0 0 0 1 0 0 1 0 K1 Q1Q0\X 00 01 11 10 K1=1 0 X X 1 1 1 X X 1 1 J0 Q1Q0\X
00 01 11 10 J0=X 0 0 X X 0 1
1
X
X
1
K0 Q1Q0\X 00 01 11 10 K0=Q1X'
0 X 0 1 X 1 X 0 0 X Circuit Q8: Solution2 Q1 Z q1q0\X 00 01 11 10 0 0 0 0 0 Z=q1q0X 1 0 0 1 0 Q0 q1q0\X 00 01 11 10 0 0 1 0 0 1 0 0 0 0 q1q0\X 00 01 11 10 Q1=q1'q0X'
Q0=q1'q0+X Circuit X
Z
q1
Q1
Q0
0 0 1 1 1 0 0 1 1 1 Question 9
(a)
Y 1 = x 1' x 2 + x 2 y 1
Y 2 = x1 y 2 + x 2
Z = Y 1 ' Y 2
(b)
N.S (
P.S
y2 y1 )
Output (Z)
x1x2
x1x2
y2 y1
00
01
11
10
00
01
11
10
00
00
11
10
00
0
0
1
0
01
00
11
11
00
0
0
0
0
10
00
11
10
10
0
0
1
1
10
00
11
11
10
0
0
0
1
(c)
At row 00
y 2 y 1 = 0 0 ⇒ 1 1 w h ile x1 x 2 = 0 0 ⇒ 0 1
It is noncritical race because 0 0 ⇒ 0 1 ⇒ 1 1 or 0 0 ⇒ 1 0 ⇒ 1 1
At row 11
y 2 y1 = 1 1 ⇒ 0 0 w h i le x1 x 2 = 0 1 ⇒ 0 0
It is noncritical race because 1 1 ⇒ 0 1 ⇒ 0 0 or 1 1 ⇒ 1 0 ⇒ 0 0
Question 10:
The rows in the primitive flow table are merged by first obtaining all compatible pairs of
states from the implication table shown in Fig. 1.
b
a,c ✗
c
✗
b,d ✗
d
b,d ✗
✗
e
b,d ✗
f
✓
g
f, h ✗
h
f, h ✗
a,c✗
a
e,g ✗
b,d ✗
a,c ✗
f,h ✗
e,g ✗
f,h ✗
a,c ✗
a,c ✗
✓
b,d ✗
✓
✓
b
c
✓
✓
e,g ✗
b,d ✗
✓
✗
d,e ✗
e,g ✗
c,f ✗
f,h ✗
d
e
e,g ✗
f,h ✗
✗
✓
f
g
Fig. 1 Implication Table
The squares that contain check marks define the compatible pairs:
(a,f), (b,g), (b,h), (c,h), (d,e), (d,f), (e,f), (g,h)
The maximal compatibles are obtained from the merger diagram shown in Fig. 2, which
is: (a,f), (b,g,h), (c,h), (d,e,f)
In this question, the minimal collection of compatibles is also the maximal compatible
set.
a
h
b
c
g
d
f
e
Fig. 2 Merger Diagram
The reduced flow table is shown in Fig. 3. The one shown in part (a) of the figure retains
the original state symbols but merges the corresponding rows. In part (b) the second
alternative shows clearly a four-state flow table with only four letter symbols for the
states.
(a)
(b)
Fig 3 Reduced Flow Table
Based on Fig 3 part (b), we draw the transition diagram as shown in Fig 4. There is a
race-free assignment in the minimized flow table without the need of extra states. This is
because there are no diagonal lines in the transition diagram.
a = 00
b = 01
d = 10
c = 11
Fig. 4 Transition Diagram