CIRCULAR BUILT-IN SELF-TEST
By
Sudheer Vemula
Electrical and Computer Engineering Dept.
Auburn University
(Class Project for VLSI Testing ELEC 7250)
ABSTRACT: - A program to implement Circular BIST for any circuit described
in Auburn Simulation Language (ASL) has been developed. Circular BIST has been
implemented for the circuit S5378 and the fault simulation results have been analyzed.
The code is written in ‘C’- Language and ASL tools have been used to convert the circuit
net list from HITEC to ASL. Fault simulation is performed using Auburn University
Simulator (AUSIM).
INTRODUCTION:The basic idea of BIST is to make the circuit test itself. The difficulty to test the
VLSI chips has been increasing continuously. The number of I/O pins for most VLSI
devices has increased by an order of magnitude where as the number of transistors has
increased by four orders of magnitude. In-circuit testing of most circuits became
infeasible because of the introduction of the surface mounted components, where the
components are placed on both sides of the Printed Circuit Board (PCB). The cost of the
test equipment is increasing as they are required to handle larger no. of I/O pins, higher
operating frequencies, and are required to generate larger sets of test vectors. All the
above mentioned difficulties can be minimized by the implementation of BIST in the
circuits.
In order to implement BIST we need to include extra circuitry. The extra circuitry
consists of Test Pattern Generator (TPG), to generate the test patterns, the Output
Response Analyzer (ORA), to compact the test results and the Test controller to control
the test.
BASIC BIST ARCHITECTURES:Built-in Logic Block Observer (BILBO) was the first BIST approach that was
proposed and was widely used. Its architecture is as shown in the fig.1. This BIST
structure was implemented by converting the normal flip-flops in BILBO flip-flops. The
BILBO structure is used both as a TPG and ORA. This can be operated in four modes of
operation as given in table 1.
Fig. 1 Built-in Logic Block Observer
B2 B1 Mode of Operation
0
0
Shift (scan) mode
0
1 MISR (BIST) mode
1
0 Initialization Mode
1
1
System mode
Table 1. Modes of operation of BILBO
The application and operation of BILBO is shown in fig. 2. BILBO is a test-per-clock
BIST architecture.
Fig. 2 Simple BILBO application to a CUT
This approach has been modified into a test per clock Circular BIST approach by
connecting all the flip-flops in the form of a circular chain and operating the flip-flops in
the BIST mode. And the basic flip-flop architecture has been slightly modified from the
initial one.
Three different circular BIST approaches have been proposed. They are Circular
Self-Test path (CSTP), Simultaneous Self-Test (SST) and Circular BIST.
B0
Xi
Mode
0
Di
System
1 Di ⊕ Qi-1 BIST
(a) CSTP flip-flop and modes of operation
Scan B0 Xi
Mode
Mode
0
0
0 Initialization
0
1
Di
System
1
0 Qi-1 Shift(Scan)
(b) SST flip-flop and modes of operation
B1 B0
Xi
Mode
0
0
0
Initialization
0
1
Di
System
1
0
Qi-1
Shift(Scan)
1
1 Di ⊕ Qi-1
BIST
(c) Circular BIST flip-flop and modes of operation
Fig 3. Comparison of circular BIST flip-flops
The basic idea of all these approaches is to partition the circuit into flip-flops and
combinational logic and the flip-flops are augmented with additional logic to operate in
BIST mode to test the circuit.
The circular BIST approach forms a large Multiple Input Signature Register
(MISR) structure connecting all the flip-flops in the circuit. The output of the MISR for
the current cycle will be applied as the input for the next cycle. As we are using an MISR
the output responses are also being compacted simultaneously. The circular feed back
path is equivalent to a characteristic polynomial P(x) = xn + 1, where ‘n’ is the number of
flip-flops.
AREA OVERHEAD DUE TO FLIP-FLOPS:The area over head for CSTP flip-flop is an ex-or gate and a multiplexer. It has an
overhead of 7 gates, if we assume a 2-to-1 multiplexer is made up of 3 elementary logic
gates and an ex-or with 4 gates. The main disadvantage is that it does no have scan mode.
The area overhead for SST flip-flop is 9 gates and for Circular BIST flip-flop is 6 gates.
The circular BIST approach has the lowest area overhead and it has 4 possible modes of
operation including scan and initialization mode.
MY WORK:The Circular BIST approach has been used, for implementing the circular BIST
for s5378, as it has the lowest area and highest flexibility (not required for this project).
All the flip-flops, outputs and inputs of the circuit have been replaced by the circular
BIST flip-flop shown in fig. 3c. .
PROCEDURE TO IMPLEMENT CIRCULAR BIST:1) The file in ‘bench’ format has to be converted in to ASL file. This is done using
the tools provide by Dr. Stroud, the command is
~strouce/bin/isc2asl name.bench, name.asl file is created.
2) Circular BIST can be implemented by executing the provided program. This can
be done using the commands
cc name.c , An executable a.out is created, then the command
a.out name.asl cbistname.asl (name.asl is the input ASL file and
cbistname.asl is the output ASL file with the Circular BIST inserted).
3) After the Circular BIST has been implemented, fault coverage by implementing
the Circular BIST has to be calculated. Fault coverage can be calculated by using
fault simulation.
Procedure to perform Fault Simulation using ASL:a) The vector file (cbistname.vec) has to be created with the no. of inputs + 2. The
two additional inputs are the control lines to control the operation of the circuit.
The no. of vectors decide the no. of cycle for which the circuit has to be run in
BIST mode.
b) The control file (cbistname.cnt) has to be created. This file contains the
commands to generate fault list and perform the logic and fault simulation. (Once
the fault simulation has been done, we can find the fault profile).
EFFICIENCY OR COVERAGE :As the circuit is a sequential circuit, the test generation is difficult when compared
to the combinational circuit. So, the vectors produced by HITEC do not give good
enough fault coverage because of the difficulty in controlling the state of the flip flops.
ADVANTAGES:The testing is performed by the BIST circuitry at the system clock frequency; this
helps in the detection of delay faults also.
POSSIBLE IMPROVEMENTS:Once full circular BIST has been implemented, the program can be modified to
implement partial circular BIST. By implementing partial circular BIST, we can remove
the BIST flip-flops in the critical paths and reduce the delay overhead.
CONCLUSION:Circular BIST gives better fault coverage for this circuit than the fault coverage
with vectors produced by HITEC. The fault coverage is not too high when the circuit is
operated for 10,000 cycles in BIST mode. From the fault profile, we can notice that the
first 250 vectors (500 cycles) detect around 2900 faults where as the next 9,750 vectors
detected only 500 faults. Because we cannot apply deterministic vectors as inputs, we
cannot achieve the required fault coverage within limited no. of clock cycles. Hard to
detect faults take more amount of test time, this is one of the main problems associated
with BIST. The fault coverage can be improved and the test time can be reduced if we
use the scan mode of operation in between BIST cycles.
RESULTS:The fault coverage of HITEC can’t be compared with that produced by ASL
because they use different algorithms for collapsing the faults. The fault lists provided by
the two do not match. The fault coverage statistics of HITEC are presented just for
comparison. There are separate tests to test the scan chain, so the faults present in the
scan chain are removed when the fault simulation is performed with circular BIST
included.
Fault Coverage achieved using HITEC:Total No. of faults present: 4603
No. of faults detected: 3146
No. Undetected Faults: 1379
No. of Potentially Detected Faults: 78
No. of redundant faults: 166
No. of aborted faults: 1291
Coverage: 0.6385
No. of vectors generated by HITEC: 894
Fault Coverage achieved when Circular BIST was implemented and the circuit was
executed for 10,000 Clock cycles (Excluding faults in BIST flip-flops):No. of collapsed faults: 3905
No. of faults detected: 3409
No. of undetected faults: 496
Fault coverage: 0.87
Fault Profile:Vecnum – Vector Number, Each vector is counted twice so that it is applied for both the
low and high states of the clock
Numflts – No. of faults
Cumm – Cumulative number of faults
Fault detection
distribution
vecnum numflts cumm
6
356
356
8
163
519
10
243
762
12
121
883
14
103
986
16
90
1076
18
96
1172
20
86
1258
22
94
1352
70
7
2105
24
26
28
30
32
34
36
38
40
42
44
46
93
84
63
64
39
38
36
34
22
27
20
45
1445
1529
1592
1656
1695
1733
1769
1803
1825
1852
1872
1917
48
50
52
54
56
58
60
62
64
66
68
22
13
24
17
18
23
10
9
5
8
32
1939
1952
1976
1993
2011
2034
2044
2053
2058
2066
2098
72
74
76
78
80
82
84
86
88
90
92
94
96
98
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
134
138
140
144
146
150
152
154
156
162
164
166
170
174
180
182
182
54
23
38
13
30
9
14
3
48
5
14
9
16
12
4
5
12
5
6
5
3
22
6
2
5
2
1
2
6
5
2
3
3
9
5
1
1
2
1
1
8
2
2
52
29
29
2159
2182
2220
2233
2263
2272
2286
2289
2337
2342
2356
2365
2381
2393
2397
2402
2414
2419
2425
2430
2433
2455
2461
2463
2468
2470
2471
2473
2479
2484
2486
2489
2492
2501
2506
2507
2508
2510
2511
2512
2520
2522
2524
2576
2605
2605
184
188
190
192
198
200
202
206
230
234
236
242
244
248
250
256
258
262
284
310
316
318
328
334
336
338
346
360
370
382
392
396
398
400
410
426
428
430
438
444
452
456
468
478
496
500
51
2
1
3
7
1
4
2
15
2
4
25
2
1
2
1
1
1
1
2
2
2
1
12
3
3
29
9
1
1
8
1
27
18
1
1
17
43
1
9
3
1
1
1
1
2
2656
2658
2659
2662
2669
2670
2674
2676
2691
2693
2697
2722
2724
2725
2727
2728
2729
2730
2731
2733
2735
2737
2738
2750
2753
2756
2785
2794
2795
2796
2804
2805
2832
2850
2851
2852
2869
2912
2913
2922
2925
2926
2927
2928
2929
2931
504
506
510
522
542
562
584
586
596
614
634
652
654
662
668
670
678
696
702
704
706
708
710
712
714
720
768
800
802
822
824
826
830
832
836
852
894
912
914
920
948
950
952
992
994
996
4
2
1
3
1
1
2
1
1
4
2
3
1
1
1
5
1
3
2
6
10
7
1
3
5
1
1
1
8
8
2
3
1
3
4
2
1
4
1
2
2
1
1
2
9
3
2935
2937
2938
2941
2942
2943
2945
2946
2947
2951
2953
2956
2957
2958
2959
2964
2965
2968
2970
2976
2986
2993
2994
2997
3002
3003
3004
3005
3013
3021
3023
3026
3027
3030
3034
3036
3037
3041
3042
3044
3046
3047
3048
3050
3059
3062
1008
1016
1028
1030
1034
1048
1058
1060
1084
1096
1102
1116
1120
1122
1134
1136
1164
1168
1174
1180
1186
1188
1196
1198
1204
1234
1280
1282
1286
1306
1314
1316
1378
1380
1424
1426
1470
1508
1540
1552
1556
1592
1622
1624
1716
1744
1
2
3
1
2
1
1
1
1
5
2
1
3
2
1
2
2
1
1
1
10
14
2
1
2
1
4
4
2
2
1
1
1
5
2
5
1
1
2
2
10
2
7
3
3
1
3063
3065
3068
3069
3071
3072
3073
3074
3075
3080
3082
3083
3086
3088
3089
3091
3093
3094
3095
3096
3106
3120
3122
3123
3125
3126
3130
3134
3136
3138
3139
3140
3141
3146
3148
3153
3154
3155
3157
3159
3169
3171
3178
3181
3184
3185
1756
1764
1856
1900
1998
2072
2078
2082
2086
2090
2108
2134
2144
2154
2186
2218
2258
2260
2318
2334
2374
2376
2384
2458
2530
2560
2564
2624
2644
2686
2770
2772
2814
2822
2888
2932
3028
3040
3042
3044
3046
3210
3306
3314
3336
3338
1
1
2
1
3
1
1
3
1
4
1
1
2
4
1
2
1
2
2
2
1
1
1
3
2
1
1
1
2
1
1
1
1
5
1
1
2
7
1
3
1
2
1
1
1
2
3186
3187
3189
3190
3193
3194
3195
3198
3199
3203
3204
3205
3207
3211
3212
3214
3215
3217
3219
3221
3222
3223
3224
3227
3229
3230
3231
3232
3234
3235
3236
3237
3238
3243
3244
3245
3247
3254
3255
3258
3259
3261
3262
3263
3264
3266
3368
3402
3532
3556
3562
3594
3810
3974
4072
4140
4168
4426
4430
4450
4476
4520
4658
4662
4922
4958
4960
5038
5120
5196
5292
5490
5492
5582
5688
5700
5930
5962
6200
6252
6378
6454
6536
6908
7042
7232
7282
7304
7342
7356
7726
7820
1
2
5
4
1
2
4
2
2
2
10
1
1
1
2
1
5
4
1
4
1
1
1
2
1
1
2
2
1
3
1
2
3
1
1
1
3
1
1
1
1
1
1
1
2
1
3267
3269
3274
3278
3279
3281
3285
3287
3289
3291
3301
3302
3303
3304
3306
3307
3312
3316
3317
3321
3322
3323
3324
3326
3327
3328
3330
3332
3333
3336
3337
3339
3342
3343
3344
3345
3348
3349
3350
3351
3352
3353
3354
3355
3357
3358
7858
7892
7894
8018
8576
9216
9568
9618
9760
9958
11588
11670
12110
12316
12488
12634
12770
12892
13142
13394
13530
13756
13892
13894
14112
14132
14824
16598
16794
18598
19536
19540
1
1
2
1
2
1
1
1
1
2
1
1
1
1
1
1
2
1
4
1
1
7
1
1
1
4
2
2
1
2
1
1
3359
3360
3362
3363
3365
3366
3367
3368
3369
3371
3372
3373
3374
3375
3376
3377
3379
3380
3384
3385
3386
3393
3394
3395
3396
3400
3402
3404
3405
3407
3408
3409