1CY 7C12 3
CY7C123
256 x 4 Static RAM
Features
Functional Description
• 256 x 4 static RAM for control store in high-speed
computers
• CMOS for optimum speed/power
• High speed
— 7 ns (commercial)
The CY7C123 is a high-performance CMOS static RAM organized as 256 words by 4 bits. Easy memory expansion is provided by an active LOW chip select one (CS1) input, an active
HIGH chip select two (CS2) input, and three-state outputs.
Writing to the device is accomplished when the chip select one
(CS1) and write enable (WE) inputs are both LOW and the chip
select two input is HIGH. Data on the four data inputs (D0
through D3) is written into the memory location specified on the
address pins (A0 through A7). The outputs are preconditioned
so that the write data is present at the outputs when the write
cycle is complete. This precondition operation ensures minimum write recovery times by eliminating the “write recovery
glitch.”
— 10 ns (military)
• Low power
— 660 mW (commercial)
•
•
•
•
•
— 825 mW (military)
Separate inputs and outputs
5-volt power supply ±10% tolerance both commercial
and military
TTL-compatible inputs and outputs
24 pins
300-mil package
Reading the device is accomplished by taking the chip select
one (CS1) and output enable (OE) inputs LOW, while the write
enable (WE) and chip select two (CS2) inputs remain HIGH.
Under these conditions, the contents of the memory location
specified on the address pins will appear on the four output
pins (O0 through O3).
The output pins remain in high-impedance state when chip
select one (CS1) or output enable (OE) is HIGH, or write enable (WE) or chip select two (CS2) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram
Pin Configuration
D0 D1 D2 D3
CS2
CS1
DATA INPUT
CONTROL
DIP/SOJ
Top View
A2
A3
A4
A5
A6
A7
VSS
D0
D1
WE
OE
O0
A0
A1
A2
O1
16 x 64
ARRAY
O2
A3
A4
A5
A6
A7
O0
O1
VSS
O3
COLUMN
DECODER
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A1
A0
WE
CS1
OE
VCC
CS2
D3
D2
O3
O2
C123–2
C123–1
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Military
Commercial
Military
Cypress Semiconductor Corporation
•
7C123–7
7
7C123–9
9
120
120
7C123–10
10
3901 North First Street
150
•
7C123–12
12
12
120
150
7C123–15
15
150
San Jose
• CA 95134 •
408-943-2600
January 1989 – Revised December 1992
CY7C123
Maximum Ratings
DC Input Voltage[1] .........................................–0.5V to +7.0V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Output Current into Outputs (LOW)............................. 20 mA
Latch-Up Current .................................................... >200 mA
Storage Temperature ..................................–65°C to+150°C
Operating Range
Ambient Temperature with
Power Applied..............................................–55°C to+125°C
Supply Voltage to Ground Potential
(Pins 24 and 18 to Pins 7 and 12) [1] ............... –0.5V to+7.0V
DC Voltage Applied to Outputs
in High Z State[1] ............................................. –0.5V to+7.0V
Range
Ambient
Temperature
VCC
Commercial
0°C to + 70°C
5V ± 10%
Military[2]
–55°C to + 125°C
5V ± 10%
Electrical Characteristics Over the Operating Range[3]
7C123–7
7C123–9
Parameter
Description
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
Test Conditions
Min.
VCC = Min., IOH = –5.2 mA
VCC = Min., IOL = 8.0 mA
2.4
Max.
7C123–10
7C123–15
Min.
0.4
Voltage[1]
Max.
2.4
7C123–12
Min.
Max.
2.4
0.4
Unit
V
0.4
V
V
2.2
VCC
2.2
VCC
2.2
VCC
VIL
Input LOW
–0.8
+0.8
–0.8
+0.8
–0.8
+0.8
V
IIX
Input Load Current
VSS < VI < VCC
–10
+10
–10
+10
–10
+10
µA
IOZ
Output Current
(High Z)
VSS < VOUT < VCC,
Output Disabled
–10
+10
–10
+10
–10
+10
µA
ICC
Power Supply
Current
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
120
mA
150
mA
Commercial
120
Military
150
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
8
pF
8
pF
Logic Table[5]
Input
OE
CS1
CS2
WE
D 0 – D3
X
H
X
X
X
High Z
Not Selected
X
X
L
X
X
High Z
Not Selected
L
L
H
H
X
O0 – O3
Read Stored Data
X
L
H
L
L
High Z
Write “0”
X
L
H
L
H
High Z
Write “1”
H
L
H
H
X
High Z
Output Disabled
Notes:
1. VIL(min.) = –3.0V for pulse durations of less than 20 ns.
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. Tested initially and after any design or process changes that may affect these parameters.
5. H = High Voltage, L = Low Voltage, X = Don’t Care, and High Z = High Impedance.
2
Outputs
Mode
CY7C123
AC Test Loads and Waveforms
R1 470 Ω
R1 470 Ω
5V
OUTPUT
5V
OUTPUT
R2
224Ω
20 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
ALL INPUT PULSES
R2
224Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
3.0V
10%
90%
10%
90%
GND
≤ 3 ns
(b)
≤ 3ns
C123– 3
C123– 4
THÉVENIN EQUIVALENT
152Ω
OUTPUT
1.62V
Switching Characteristics Over the Operating Range[3]
7C123–7
Parameter
Description
Min.
Max.
7C123–9
Min.
Max.
7C123–10
7C123–12
7C123–15
Min.
Min.
Min.
Max.
Max.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
7
9
10
12
15
ns
tACS
Chip Select to Data Valid
7
8
8
8
10
ns
tDOE
OE LOW to Data Valid
7
8
8
8
10
ns
5
6
6
6.5
8
ns
tHZCS
7
Chip Select to High
Z[6,7]
Z[6]
9
5
10
6
12
6
15
6.5
ns
tHZOE
OE HIGH to High
tLZCS
Chip Select to Low Z[7]
2
2
2
2
2
8
ns
ns
tLZOE
OE LOW to Low Z
2
2
2
2
2
ns
WRITE CYCLE
tWC
Write Cycle Time
tHZWE
WE LOW to High Z[6]
7
9
tLZWE
WE HIGH to Low Z
2
2
2
2
2
ns
tPWE
WE Pulse Width
5
6.5
7
8
11
ns
5.5
10
6
12
6
15
7
ns
8
ns
tSD
Data Set-Up to Write End
5
6
7
8
11
ns
tHD
Data Hold from Write End
1
1
1
1
1
ns
tSA
Address Set-Up to Write Start
0.5
1
1
2
2
ns
tHA
Address Hold from Write End
1.5
1.5
2
2
2
ns
tSCS
CS LOW to Write End
5
6.5
7
8
11
ns
tAW
Address Set-Up to Write End
5.5
7.5
8
10
13
ns
Notes:
6. Transition is measured at steady-state HIGH level – 500 mV or steady-state LOW level +500 mV on the output from 1.5V level on the input with load shown
in part (b) of AC Test Loads.
7. At any given temperature and voltage condition, tHZCS is less than t LZCS for any given device.
3
CY7C123
Switching Waveforms
Read Cycle [8,9]
tRC
ADDRESS
tAA
CS1 – CS2
tHZCS
tACS
tLZCS
OE
tHZOE
tDOE
tLZOE
DATA OUT
DATA VALID
C123–5
Write Cycle [8,9]
tWC
ADDRESS
tAW
tHA
tSCS
CS1 – CS2
tSA
tPWE
WE
tSD
tHD
DATA IN
tHZWE
tLZWE
DATA OUT
C123–6
Notes:
8. Measurements are referenced to 1.5V unless otherwise stated.
9. Timing diagram represents one solution that results in an optimum cycle time. Timing may be changed in various applications as long as the worst case limits
are not violated.
4
CY7C123
Typical DC and AC Characteristics
1.4
90
1.2
1.2
1.0
VCC =5.0V
TA =25°C
75
ICC
ICC
1.0
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
0.8
60
0.6
45
0.8
0.6
0.4
0.4
0.0
4.0
4.5
5.0
ISB
0.2
ISB
0.2
5.5
6.0
30
VCC =5.0V
VIN =5.0V
15
0
0.0
–55
25
0
125
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.0
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.4
1.6
360
1.3
1.4
300
1.2
240
1.2
1.1
180
TA =25°C
1.0
VCC =5.0V
1.0
120
0.8
0.9
0.8
4.0
4.5
5.0
5.5
6.0
VCC =5.0V
TA =25°C
60
0.6
–55
25
125
0
0.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE(V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
3.0
4.0
5.0
NORMALIZED I CC vs. CYCLE TIME
1.1
VCC =5.0V
TA =25°C
VIN =0.5V
VCC =4.5V
TA =25°C
2.5
2.0
2.0
OUTPUT VOLTAGE (V)
TOTAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30
3.0
1.0
20
1.0
10
0.9
1.5
1.0
0.5
0.0
0.0
0
1.0
2.0
3.0
4.0
SUPPLY VOLTAGE (V)
5.0
0
200
400
600
800
CAPACITANCE (pF)
5
1000
0.8
10
20
30
CYCLE FREQUENCY (MHz)
40
CY7C123
Ordering Information
Speed
(ns)
7
Ordering Code
CY7C123–7PC
CY7C123–7VC
CY7C123–9PC
CY7C123–9VC
CY7C123–10DMB
CY7C123–12PC
CY7C123–12DMB
CY7C123–15DMB
9
10
12
15
Package
Name
P13A
V13
P13A
V13
D14
P13A
D14
D14
Package Type
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
24-Lead (300-Mil) Molded DIP
24-Lead Molded SOJ
24-Lead (300-Mil) CerDIP
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
24-Lead (300-Mil) CerDIP
Operating
Range
Commercial
Commercial
Military
Commercial
Military
Military
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
Parameter
Subgroups
VOH
1, 2, 3
VOL
1, 2, 3
tRC
7, 8, 9, 10, 11
VIH
1, 2, 3
tAA
7, 8, 9, 10, 11
VIL Max.
1, 2, 3
tACS
7, 8, 9, 10, 11
IIX
1, 2, 3
tDOE
7, 8, 9, 10, 11
IOZ
1, 2, 3
WRITE CYCLE
ICC
1, 2, 3
tWC
7, 8, 9, 10, 11
tPWE
7, 8, 9, 10, 11
tSD
7, 8, 9, 10, 11
tHD
7, 8, 9, 10, 11
tSA
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tSCS
7, 8, 9, 10, 11
tAW
7, 8, 9, 10, 11
READ CYCLE
Document #: 38–00060–F
6
CY7C123
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL–STD–1835 D– 9 Config.A
24-Lead (300-Mil) Molded DIP P13/P13A
7
CY7C123
Package Diagrams (continued)
24-Lead Molded SOJ V13
© Cypress Semiconductor Corporation, 1993. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.