CSE140 L
Instructor: Thomas Y. P. Lee
February 15, 2006
Agenda
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Lab3
‹ Counters are FSM
‹ Finite State Machine
‹ Models to represent FSM – Mealy Machine and Moore Machine
FSM Design Procedure
‹ State Diagram
‹ State Transition Table
‹ Next State Logic Functions
Example One – Vending Machine
‹ Mealy Machine Implementation
‹ Moore Machine Implementation
Quartus II Tutorial – Finite State Machine Implementation
Improved Vending Machine
z Moore Machine Implementation
‹ Mealy Machine Implementation
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Acknowledgement
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Materials in this lecture are courtesy of the following people
Randy H. Katz (University of California, Berkeley, Department of
Electrical Engineering &Computer Science)
MIT Prof. Anantha Chandrakasan and Donald E. Troxel “Introduction
to Digital System Design Lab”
Professor C.K.Cheng, CSE140L
John F. Wakerly, Digital Design, “Principles and Practices”, 3rd
edition
Counters are FSM
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Counters
z proceed through well-defined sequence of states in response to
enable
Many types of counters: binary Up/Down, BCD, Gray-code,Divide-by3,…
z 3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...
z 3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000,
111, ...
001
000
010
011
100
3-bit up-counter
111
110
101
2
Finite State Machine
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Finite State Machines (FSMs) are a useful abstraction for sequential
circuits with “states” of operation
At each clock edge, combinational logic block computes outputs and
next state as a function of inputs and present state
Two Types of FSM - Mealy and Moore
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Pipelined State Machine
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Often used in PLD-based state machines.
™ Outputs taken directly from flip-flops, valid sooner after clock edge.
™ But the “output logic” must determine output value one clock tick
sooner (“pipelined”).
Comparison of Mealy and Moore Machine
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Mealy machines tend to have less states
z different outputs on arcs (n2) rather than states (n)
Moore machines are safer to use
z outputs change at clock edge (always one cycle later)
z In Mealy machines, input change can cause output change as
soon as logic is done – a big problem when two machines are
interconnected – asynchronous feedback may occur if one isn’t
careful
Mealy machines react faster to inputs
z react in same cycle – don't need to wait for clock
z in Moore machines, more logic may be necessary to decode state
into outputs – more gate delays after clock edge
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State Machine Analysis Steps
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Assumption: Starting point is a logic diagram.
1. Determine next-state function and output function
2. Construct state (transition) table
™ For each state/input combination, determine the excitation
value.Using the characteristic equation, determine the
corresponding next-state values (trivial with DFF’s)
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3. Construct output table
™ For each state/input combination, determine the output value
(Can be combined with state table.)
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4. Draw state diagram
Example in Katz’s Book: Vending Machine
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Release one item after 15 cents are deposited
Single coin slot for dimes, nickels
No change.-Æ not realistic
The controller’s cause a single item to be released down a chute to
the customer -> how to choose different items?
Reset
N
Coin
Sensor
D
Vending
Machine
FSM
Open
Release
Mechanism
Clock
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Vending Machine (Cont.)
z
Suitable abstract representation
™ typical input sequences:
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z
z
z
Reset
3 nickels
nickel, dime
dime, nickel
two dimes
S0
N
™ draw state diagram:
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S1
inputs: N, D, reset
output: open chute
N
™ assumptions:
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D
S3
assume N and D asserted
for one cycle
each state has a self loop
for N = D = 0 (no coin)
N
S7
[open]
S2
D
N
S4
[open]
S5
[open]
D
S6
[open]
D
S8
[open]
Initial vending-machine state diagram
Minimized Vending Machine’s States
™ Minimize number of states - reuse states whenever possible
™ S4,S5….,S8 have identical behavior=> combine into a single state
present
state
0¢
Reset
0¢
N
5¢
N
D
5¢
D
10¢
10¢
N+D
15¢
[open]
15¢
inputs
D
N
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
X
X
next
state
0¢
5¢
10¢
X
5¢
10¢
15¢
X
10¢
15¢
15¢
X
15¢
output
open
0
0
0
X
0
0
0
X
0
0
0
X
1
Minimized symbolic state transition table
Minimized vending-machine state diagram
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Vending Machine Encoded State Transition Table
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Uniquely encode states
present state inputs
Q1 Q0
D
N
0 0
0
0
0
1
1
0
1
1
0 1
0
0
0
1
1
0
1
1
1 0
0
0
0
1
1
0
1
1
1 1
0
0
0
1
1
0
1
1
next state
D1 D0
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
output
open
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
Moore Implementation of Vending Machine
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Mapping to Truth Table
Q1
D1
0 1 1 1
D
X X X X
Q1
D0
0 0 1 1
Q1
Open
0 0 1 0
0 1 1 0
1 0 1 1
N
D
0 0 1 0
N
X X X X
D
N
X X X X
1 1 1 1
0 1 1 1
0 0 1 0
Q0
Q0
Q0
D1 = Q1 + D + Q0 N
D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0
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Encoding in State Machine
• State Machine Encoding Style:
ƒ Binary, One-hot, Two-hot, Gray code, Johnson Code
™ Binary encoding
Requires the least number of FFs. With n FFs, 2n states
can be encoded. Disadvantages: require more logic, slower.
™ One-hotencoding
one FF per state, with n FFs, n states can be encoded. Require the least amount of
extra logic and fastest
™ Two- hot encoding
Presents two bits active per state. With n FFs, n(n-1)/2 states can be encoded.
™ Gray code encoding
Adjacent Gray codes are different in only one bit. n bits Gray code needs n FFs and
can represent 2n states.
™ Johnson code encoding
Use the output pattern of Johnson counter to encode the states. n bits Johnson code
needs n FFs and can represent 2n states.
Different State Encodings
™ Different state encodings leads to different circuit implementation,
and thus different hardware cost and performance of state machines
™ State encoding provides another dimension of optimizations
Encoding Style
STATE
BINARY
TWOHOT
State0
000
State1
ONEHOT
(8 bits)
Johnson
Code (4 bits)
Gray
Code
(3 bits)
00011
00000001
0000
000
001
00101
00000010
0001
001
State2
010
01001
00000100
0011
011
State3
011
10001
00001000
0111
010
State4
100
00110
00010000
1111
110
State5
101
01010
00100000
1110
111
State6
110
10010
01000000
1100
101
State7
111
01100
10000000
1000
100
Number of FFs
required
3
5
8
4
3
In Lab3: We use Binary Code, One-Hot State Encoding
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Vending Machine (Cont.)
One-hot encoding
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present state
Q3 Q2 Q1 Q0
0 0 0 1
0 0
1
0 1
0
1 0
0
0
0
0
inputs
D N
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
- -
next state output
D3 D2 D1 D0 open
0 0 0 1
0
0 0 1 0
0
0 1 0 0
0
- - - 0 0 1 0
0
0 1 0 0
0
1 0 0 0
0
- - - 0 1 0 0
0
1 0 0 0
0
1 0 0 0
0
- - - 1 0 0 0
1
D0 = Q0 D’ N’
D1 = Q0 N + Q1 D’ N’
D2 = Q0 D + Q1 N + Q2 D’ N’
D3 = Q1 D + Q2 D + Q2 N + Q3
OPEN = Q3
Equivalent Mealy and Moore State Diagrams
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Moore machine
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outputs associated with state
N’ D’ + Reset
Reset
0¢
[0]
Mealy machine
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outputs associated with transitions
0¢
N’ D’
5¢
[0]
N’ D’
D/0
10¢
[0]
N’ D’
N’ D’/0
D/1
10¢
N’ D’/0
15¢
Reset’/1
N+D/1
N+D
15¢
[1]
5¢
N/0
N
D
N’ D’/0
N/0
N
D
(N’ D’ + Reset)/0
Reset/0
Reset’
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Mealy Implementation of Vending Machine
Reset/0
Reset/0
0¢
present state inputs
Q1 Q0
D
N
0 0
0
0
0
1
1
0
1
1
0 1
0
0
0
1
1
0
1
1
1 0
0
0
0
1
1
0
1
1
1 1
–
–
N’ D’/0
N/0
D/0
5¢
N’ D’/0
10¢
N’ D’/0
15¢
Reset’/1
N/0
D/1
N+D/1
Q1
Open
0 0 1 0
0 0 1 1
D
N
X X 1 X
0 1 1 1
D0
D1
OPEN
next state
D1 D0
0
0
0
1
1
0
–
–
0
1
1
0
1
1
–
–
1
0
1
1
1
1
–
–
1
1
output
open
0
0
0
–
0
0
1
–
0
1
1
–
1
= Q0’N + Q0N’ + Q1N + Q1D
= Q1 + D + Q0N
= Q1Q0 + Q1N + Q1D + Q0D
Q0
Mealy Implementation of Vending Machine (Cont.)
D0
= Q0’N + Q0N’ + Q1N + Q1D
D1
= Q1 + D + Q0N
OPEN = Q1Q0 + Q1N + Q1D + Q0D
make sure OPEN is 0 when reset
– by adding AND gate
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Vending machine: Moore to Synch. Mealy
OPEN = Q1Q0 creates a combinational delay after Q1 and Q0 change in Moore
implementation
This can be corrected by retiming, i.e., move flip-flops and logic through each other to
improve delay
OPEN.d = (Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D)
= Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D
Implementation now looks like a synchronous Mealy machine
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it is common for programmable devices to have FF at end of logic
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Vending Machine: Mealy to Synch. Mealy
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OPEN.d = Q1Q0 + Q1N + Q1D + Q0D
OPEN.d = (Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D)
= Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D
Q1
Open.d
0 0 1 0
0 0 1 1
D
Q1
Open.d
0 0 1 0
0 0 1 1
N
1 0 1 1
0 1 1 1
Q0
D
N
X X 1 X
0 1 1 1
Q0
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Hardware Description Languages (HDL) and
Finite State Machine
Input
Output
Combinational Logic
pr_state
nx_state
Sequential Logic
Clock
Reset
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FSM approach => tasks constitute a well-structured list so that All
states can be easily enumerated
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VHDL coding
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ARCHITECTURE => user defined enumerated data type, containing
a list of all possible system states
Finite State Machine – VHDL (Cont.)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------------------------------------ENTITY <entity_name> IS
PORT ( input: IN <data_type>;
reset, clock: IN STD_LOGIC;
output: OUT <data_type>);
END <entity_name>;
--------------------------------------------------------------------ARCHITECTURE <arch_name> of <entity_name> IS
TYPE state IS (state0, state1, state2, state3,…);
SIGNAL pr_state, nx_state: state:
BEGIN
------------- lower section (sequential logic)---------------PROCESS (reset, clock)
BEGIN
IF (reset = ‘1’) THEN
pr_state <= state0;
ELSEIF (clock’EVENT AND clock=‘1’) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
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Finite State Machine – VHDL (Cont.)
------------- Upper section (combinational logic) --------PROCESS (input, pr_state)
BEGIN
CASE pr_state IS
WHEN state0 =>
IF (input = …) THEN
output <= <value>;
nx_state <= state1;
ELSE…
END IF;
WHEN state1 =>
IF (input = …) THEN
output <= <value>;
nx_state <= state2;
ELSE…
END IF;
WHEN state2 =>
IF (input = …) THEN
output <= <value>;
nx_state <= state3;
ELSE…
END IF;
WHEN OTHERS =>
nx_state <= state0;
….
END CASE;
END PROCESS;
END <arch_name>;
QuartusII Design Entry- Entering VHDL/Verilog
™ Launch QuartusII
™ Create a new Project (file->New Project Wizard), the project name (same as
ENTITY)
™ Open the text editor((File -> New, or click on edit icon select VHDL/Verilog)
™ Entering VHDL/Verilog code, save in the extension .vhd or .v
™ Check for syntax errors. Select Processing-> Analyze current File or click on
analysis icon
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QuartusII - Compilation
™
™
Select the target device (Assignments -> Devices)
To compile VHDL/Verilog Code, select Processing-> Start Compilation, fix all
compilation error until successful message window appears
™
Examine the compilation reports (on the left of figure), check
(1)
(2)
(3)
(4)
(5)
Flow Summary: contain part number, the number of pins used,…etc
Resource Usage Summary (fitter->resource section-> resource usage summary)
Input/Output Pins (fitter->resource section-> Input pins, fitter-> resource section->output
pins), these two reports show the I/O pin assignments
Floorplan View (fitter->Floorplan View), shows layout of the logic cells, which logic cells
were used and how, etc.
Analysis and Synthesis Equations (Analysis and Synthesis ->Analysis and Synthesis
Equations)
QuartusII - Simulation
™
™
Open Waveform Editor, Select File-> New->Other File -> Vector Waveform File
In order to define the size of waveform,
Edit -> End Time ( select 500ns, for example)
Edit -> Grid Size ( select Period = 50ns, duty cycle = 50%)
Select View -> Fit in Window Note: change default, go to Tools->Options->Waveform
Editor->general
4.
Add the input and output signals to the waveform window. Click the right mouse button
inside the white area under Name. Select Insert Node or Bus. In the next box, select
Node Finder. Make sure that Filter is set to Pins: all. Click on Start, then on >>, and
finally OK. The waveforms window contains all all signals in VHDL/Verilog code.
5.
Set the values of the input signals. (clk, rst,d,….) To set up the clock signal, select the
entire clk line. A setup box will be displayed, choose period = 100 ns
6.
For rst, select only the first portion (from 0 to 25 ns), which will cause change from 0 to 1.
7.
Save the waveform file as *.vwf
8.
The system is now ready for simulation. Select Processing -> Start Simulation
1.
2.
3.
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QuartusII – State Machine Viewer
™
The State Machine Viewer provides a high-level graphical representation of the
states and state transitions, as well as a state transition table
™
After running Analysis & Synthesis, you can also view encoding information for
the state transitions in the State Machine Viewer.
™
To view state machine nodes, transitions, and encoding in the State Machine
Viewer:
Open Project,.On the Tools menu, click State Machine Viewer.
Or, In the RTL Viewer, in the hierarchy list, expand the design element that
contains the state machine you want to view, and then expand the State
Machines category to select the specific state machine and view it in the State
Machine Viewer.
Turn on the Highlight Fan-In and Highlight Fan-Out commands (View menu)
to highlight node fan-in and fan-out, respectively.
To view the transitions for a state machine, select the state machine in the
schematic view and then click the Transitions tab.
™
To view the encoding for a state machine:
Perform Analysis & Synthesis first, Select the state machine in the schematic
view and then click the Encoding tab.
Vending Machine – How to Improve?
ƒ Lab assistants demand a new
soda machine for school. You need to
design the FSM controller.
™ All selections are $0.30
™The machine makes changes!
(Dimes and nickels only.)
ƒ Inputs: limit 1 per clock
Q - quarter inserted
D - dime inserted
N - nickel inserted
ƒ Outputs: limit 1 per clock
DC - dispense can
DD - dispense dime
DN - dispense nickel
But, machine still has problem!
Can machine select drinks? No !
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FSM States Encoding
Moore Machine Implementation
State Transition DiagramNot minimized yet
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State Reduction (remove duplication)
Moore State Machine Implementation in Verilog
Code of Vendor Machine
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Moore State Machine Implementation in Verilog
Code of Vendor Machine (cont.)
Moore State Machine Simulation Result
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Combine Next-State and Output Logic
Mealy Machine Implementation
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Verilog Code for Mealy Machine Implementation
Verilog Code for Mealy Machine Implementation
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Simulation Result of Mealy Machine
Implementation
State Encoding in Verilog Code
Binary (Decimal) encoding
parameter IDLE = 0;
parameter GOT_5c = 1;
parameter GOT_10c = 2;
parameter GOT_15c = 3;
parameter GOT_20c = 4;
parameter GOT_25c = 5;
parameter GOT_30c = 6;
parameter GOT_35c = 7;
parameter GOT_40c = 8;
parameter GOT_45c = 9;
parameter GOT_50c = 10;
parameter RETURN_20c = 11;
parameter RETURN_15c = 12;
parameter RETURN_10c = 13;
parameter RETURN_5c = 14;
One-hot Encoding
parameter IDLE =
16’b0000000000000001;
parameter GOT_5c =16’b0000000000000010;
parameter GOT_10c=16’b0000000000000100;
parameter GOT_15c= ….;
parameter GOT_20c= …;
parameter GOT_25c= ..;
parameter GOT_30c= … ;
parameter GOT_35c= …;
parameter GOT_40c= ..;
parameter GOT_45c= …;
parameter GOT_50c= ..;
parameter RETURN_20c = ……..;
parameter RETURN_15c = ……..;
parameter RETURN_10c = ……..;
parameter RETURN_5c = ………;
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Lab 3 Assignment
ƒ Two types of Finite State Machines
™ Moore – Outputs are a function of current state only
™ Mealy – Outputs a function of both the current state and
input function
ƒ Lab 3 assignment – please fix the problem in lecture! we need
to have capability to select different drinks, and depense the
selected drink and changes
ƒ We will cover how to fix Glitching in FSM? Timing
Requirement in FSM, “String Pattern Recognizer” next week.
ƒFinal Exam – Tuesday, March 21, 2006, 9:00AM- 10:30AM,
HSS1330
ƒMarch 15- Oral exam by TA on Lab 4
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