Snapback in well resistors
Guido Notermans , Anco Heringa*, Olivier Quittard, Fabrice Blanc
ESD Group, CAD Competence Centre, Philips AG Semiconductors - Zurich
* Philips Research Eindhoven/ Leuven
3rd EOS/ESD/EMI Workshop, Toulouse, May 2006
outline
• introduction
• nwell resistor
• physical description
• p+-nwell-n+ diode
• summary
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
2
introduction
Why this investigation ?
0.35 μm 12V CMOS process
HV NMOST
bulk
source
drain
gate
p+
strange TLP results
1.E-09
1.E-07
1.E-05
nwell
HNW
C075HV ANAM AHVNMOS ISO Gate
Leakage [A]
1.E-11
n+
n+
pwell
1.E-03
1.E-01
1.E+01
1.8
p-epi
1.6
1.4
Itlp [A]
1.2
1
0.8
0.6
0.4
0.2
0
0
10
20
30
40
50
60
70
Vtlp [V]
TLP ahvnmost_iso_gate_3u_200u (10.9)
TLP hvnmost_iso_ballast1_5u_200 (9.5)
TLP ahvnmost_iso_gate_2u_200u (10.8)
Leak ahvnmost_iso_gate_3u_200u (10.9)
Leak hvnmost_iso_ballast1_5u_200 (9.5)
Leak ahvnmost_iso_gate_2u_200u (10.8)
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
3
introduction
substrate
source
gate
nwell / locos
drain
substrate
source
gate
nwell / locos
drain
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
4
outline
• introduction
• nwell resistor
• physical description
• p+-nwell-n+ diode
• summary
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
5
nwell resistor
Leakage current (nA)
-1
10
0
10
101 102 103 104 105 106 107 108
40
Leakage current
30
Second Breakdown
20
Sub-Surface Breakdown
10
0
0
2
4
6
8 10 12 14
TLM Voltage (Volt)
16
18
20
4
ggNMOST with nwell
nwell alone
N-Well Current (mA/μm)
TLM Current (mA/μm)
I-V curve
3
2
1
0
0
1
2
3
4 5 6 7 8
N-Well Voltage (Volt)
9
10 11
From: Guido Notermans et al., EOS/ESD Symposium 1997
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
6
nwell resistor
Voltage drop (V)
nwell voltage drop
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
C100 simulated
medici
C075MV oq_pc8930
C100 measurements
0
2
4
6
8
nwell length (um)
voltage drop across and
current density through
pwell agree well with
previous C100 experiments
nwell current density (mA/um)
nwell current density
3
2.5
2
C075MV gn_pc8930
C100 measurements
C100 2D-sim Medici
1.5
1
0.5
0
0
2
4
6
8
nwell length (um)
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
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nwell resistor
Second Breakdown Current (mA/μm)
Second Breakdown Current (mA/μm)
Design rule for nwells
25
20
Reference; no n-well
15
25
C = 1.1 μm; D varied; A = 1.2 μm
D = 1.4 μm; C varied; A = 1.8 μm
20
a
b
15
Reference; no n-well
10
5
0
0
1
2
3
4
5
6
7
locos-to-gate length C+D (μm)
8
10
5
0
0
1
2
3
4
5
6
contact-to-nwell length A (μm)
7
8
From: Guido Notermans et al., EOS/ESD Symposium 1997
Ballast resistor rule
on both sides
of the nwell
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
8
outline
• introduction
• nwell resistor
• physical description
• p+-nwell-n+ diode
• summary
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
9
physical picture
1D nwell simulation
using Silvaco software
nnwell = 4. 1017 cm-3
unipolar device: no holes
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
10
physical picture
Vext = 0 V
Jdiff
Vext = + VA
Jdrift
Jdiff
Jdiff
EF
Ec
Jdrift
Jdiff
VA
Ei
Ev
n+
n+
nwell
J ≈ J drift ,e = qne ⋅ μ e E
n+
n+
(Ohm)
J drift ,e = qne ⋅ v ⇒ qne v sat
dE
q
= − (n − p − N D + N A )
dx
ε
nwell
for large E
(Poisson)
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
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physical picture
carrier concentration
carrier concentration
e
net charge
e
h
E-field
Potential
h
I-V curve
Snapback
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
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physical picture
nwell top view
5
Qualitative filamentation model
electric field
impact generation
localized high E-field
more local impact generation
more local current
more localized E-field
...
filamentation formation
y
x
0
5
impact generation
y
x
0
5
at high enough current
thermal damage
current density
y
nwell is dangerous
x
0
0
100
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
13
outline
• introduction
• nwell resistor
• physical description
• p+-nwell-n+ diode
• summary
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
14
p+-nwell-n+ diode
well resistors are everywhere !
LV p-diode
HV n-diode
Anode
Cathode
Lp Ln
STI
Pplus
Pplus
Source
Thick
oxide
1.3
NWell
PWell
SiProt
Pplus Nplus
Gate
Drain
0.6
STI
LB2
Nplus
NWell
SiProt
STI
Anode
0.8um
Ln L p
Nplus
PWell
Cathode
HVNMOST
Anode
Cathode
0.8um
Pplus
NWell
Nplus
NWell
Nplus
PWell
HPWell
P-/P+ substrate
NWell
P-/P+ substrate
12μm
reverse
3.4
LS
HNWell
LG 0.7 (LB1- 0.7)
>2um
LB1
reverse
P-/P+ substrate
reverse
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
15
reverse p+-nwell-n+ diode
Reverse biased p+-nwell diode; Simulation
-2
10
n+
-7 A
10
n
+
A
nwell
nwell
p+
p+
p+-nwell breakdown
and n+-nwell breakdown
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
16
reverse p+-nwell-n+ diode
Comparison with measurements
Cathode
Anode
0.8um
STI
Nplus
NWell
n+-nwell
Cathode
0.8um
Pplus
NWell
Nplus
NWell
P-/P+ substrate
breakdown
p+-nwell breakdown
(≈11 V)
impact generation at p+-nwell
⇒ no damage
impact generation at n+-nwell
⇒ thermal damage
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
17
forward p+-nwell-n+ diode
What about forward a biased diode ?
HVNMOST
Source
Thick
oxide
1.3
SiProt
Pplus Nplus
Gate
Drain
0.6
LB2
forward
SiProt
STI
Nplus
PWell
NWell
3.4
LS
HNWell
LG 0.7 (LB1- 0.7)
>2um
LB1
P-/P+ substrate
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
18
forward p+-nwell-n+ diode
Forward biased p+-nwell diode; Simulation
Vext = 0 V
Jdiff
Vext = -VA
Jdrift
Jdiff
Jdiff
Jdrift
Jdiff
Ec
Ei
Ec
Ei
-VA
Ev
EF
Jdiff
n+
p+
nwell
J ≈ J diff ,e + J diff ,h = qDn
J diff ,e ≈ J diff ,h
dne
dn
+ qDh h
dx
dx
n+
Jdrift
nwell
Ev
EF
Jdiff
p+
No velocity saturation
No high E-field
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
19
forward p+-nwell-n+ diode
carrier concentration
E-field
Potential
No impact generation
No snapback
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
20
outline
• introduction
• nwell resistor
• physical description
• p+-nwell-n+ diode
• summary
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
21
summary
What can we do about n-wells?
• Use a higher doped well
J’sat(mA/μm) ≈ 3.75x10-18nwell(cm-3)
25
20
Reference; no n-well
15
10
5
0
0
1
2
3
4
5
6
contact-to-nwell length A (μm)
7
8
Second Breakdown Current (mA/μm)
Second Breakdown Current (mA/μm)
• Use sufficient spreading
resistance
25
C = 1.1 μm; D varied; A = 1.2 μm
D = 1.4 μm; C varied; A = 1.8 μm
20
a
b
15
Reference; no n-well
10
5
0
0
1
2
3
4
5
6
7
locos-to-gate length C+D (μm)
8
• Devise smart injector regions, to allow current conduction by diffusion
(well-known example ggNMOST)
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
22
summary
Well resistors are everywhere!
Be very careful when using well resistors
under high current conditions !
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
23
2D simulation
n+
pwell
nwell
n+
p+
HNW
p-epi
COLD 2D simulation:
(HV) NMOST IV curve
excellent agreement with
measurements
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
25
2D simulation
n+
pwell
nwell
n+
p+
10-12A
HNW
p-epi
COLD 2D simulation shows:
(HV) NMOST parasitic NPN
has kicked in, but apparently
localization in the nwell
destroys it.
Philips Semiconductors, May 18-19, 2006, 3rd EOS/ESD/EMI Workshop, Toulouse
10-2A
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