B-5-4
Extended Abstracts of the l7th Conference on Solid State Devices and Materials, Tokyo, 1985, pp. 413-416
Advanced GaAs SAINT FET Fabrication Technology and its Application to
above 9 GHz Frequency Divider
T. Enoki, K.
NTT
Yamasaki, K. 0safune, and K.
0hwada
Atsugi Electrical Communication Laboratories
3-1 ,Mori nosato Wakamiya, Atsug'i-shi
Kanagawa
Pref.
,
243-01 Japan
An advanced (fl_at-gate) SAINT FET structure without the excess gate mgtal
overlapping the dielectric film is rea'lized by newly developed pla]nalization
technologY,..and which decreases .9.ate. parasitic _capacitanie. BFL M/S (master/slave)
f requency di vi ders f abri cated wi th thi s techno'logy operated up to 9 .2 GHz at roorir
temperature. It is confirmed that thr's FET structure is advantageous in high speed
and h'igh frequency GaAs ICs.
1. Introduction
e'lectrode formati on of a
High speed GaAs LSIs, such as the 16kb
realized with SAINT rErs.(2)
Moreover the short channel effect, which is an
obstacle in gate length shortening for much faster
operat'ion , was suppressed by a buri ed P-'l ayer
described below.
After opening the gate contact region, Mo/Au
is deposited onto the whole surface. by sputtering
(Fig. 2(a)). Then, the Au surface is planalized
SRAM,(1) have been
FET (
.BP-SAINT FET ).(3) Using BP-SAINT
FET, operatioh below 10 ps/gate with E/D ring
oscillator, and LSCFL 7.5 GHz I/4 frequency
f4\
divider''' are some of the realized advantages.
However, in these SAINT FETs, the gate metal
formed by the lift-off method unfavorab'ly overlaps
the die'lectric film. This excess gate metal
increases parasitic capacitances, and degrades
high frequency performance. In order to overcome
SAINT
fI
at-gate SAINT
milling with a large ion beam incident
angle, until Au remains only in the gate dip
region (Fig. 2(b)). This p'lanalization method
accounts for the cos0 dependence of Au etching
rate on the ion beam 'incident angle (0). Then the
by ion
this disadvantage, an advanced ( flat-gate ) SAINT
FET structure without excess gate metal
overlapping the dielectric fi'lm was proposed and
real ized by newly developed planal ization
beam
(a) conventional SAINT FET
techno'logy. BtL L/2 frequency dividers fabricated
with this process operated up to 9.2 GHz at room
temperature, which 'is the highest frequency in any
semiconductor devices.
.
cat'ion Process
Schematic cross-sectional views of a flat
gate SAINT FET compared .with a conventional SAINT
FET are shown in F'ig. 1. The flat-gate SAINT
process is almost the same as the conventional
SAINT process except gate formation. A gate
2
is
FET Fabri
(b) flat-gate
flat-gate SAINT FET
L Schematic cross-sectional views of
(a) conventional SAINT FET
Fi g.
(b) f'lat-gate SAINT
FET.
ion beom
oMo/Au
Mo/Au
Sputler depo.
Si
0z
SiN
(0)
"
Ion
Beom
r tur
Milling Gu)
tbt
"
RIE
I
Fig. 3 A SEM photograph
flat-gate SAINT FET.
(Mo)
around
the gate of
a
(c)
Fig. 2
Gate formation process
of a flat-gate
SAINT FET.
Fi
Au pattern i s
repl icated in the Mo ayer by
Reacive Ion Etching (RIE). Consequent'ly, the gate
electrode is embedded only in the gate opening
region. A SEM photograph around the gate is shown
1
SAINT
are summarized 'in Table 1. Static characteristics
almost the same as those of a conventional SAINT
FET are real i zed by th'is process wi thout the
damage in ion beam mi'l1ing and RIE.
To estimate the gate capacitances of the FET,
the S-parameter of an FET with 200 ,pm-width and
0.3 pm-length gate was measured. The gate-drain
capacitance (Cod) derived from Im(-Yrr) are shown
in Fig.3. Final1y, ohmic electrodes (AuGe/Ni)
are formed (Fig. 1(b)).
l'lith this gate electrode formation, 0.5 fmgate length FETs were realized without the excess
gate metal overlap
Active 1 ayers (n- and n*-l uy.rr) were
prov'ided by selective Si+ implantation at 30 keV
wi th a dose of 8.5xt012 ctn-Z ,1 and at 200 keV
through 0.15 /.rm SiN f ilm with a dose of 4x1013
-2
The p-layer was selectively buried under
cm -.
the active layers by Be* implantation at 7O keV
with a dose of 6x1011 .r-2.
3.
g. 4 I -V characteri sti cs of a f 'l at-gate
FET. Lg=O.5 lr*, Wn=10 pm, Vn=O.0--i .4 V .
. 5 , -'i n compari son wi th that of a
conventi onal SAINT FET. Cga i s decreased by
i
n
Fi g
26 ft/200 pm-gate-width. This Cga reduction is
considered to be due to the removal of the excess
gate metal overlapping the dielectric film.
The frequency dependence of the current gain
is shown in Fig. 6. According to F'i9.6,
4L')
cut-off frequencies (ff) of a flat-gate and
conventional SAINT FET are 32 and 24 GHz,
respectively. Thi s advantage i s due to the
stics
The I-V characteristics of f'lat-gate SAINT
FET with 10 pm-width and 0.5 pm-length gate are
shown in Fig. 4. The average values for device
parameters derived from the I-V characteristics
FET characteri
(Hr.,
-
reduction of the gate parasitic capacitances.
4t4
f
Gofe mefol
Gote length
Vttr
(lml
(V I
lot
- gole
Mo/Au
Ti/Pt/Au
0.5
0.5
-t.l
-r.3
gm (ms/mm,Vg=0V)
r84
Borrier heighl
0.7
(eV
Convenlionol
t80
0.78
|
K (mA/Vzlmml
Tab'le 1
il4
92
Average values for characteristics of
SAINT FETs.
A
F'
\{
Vds =
o
tr)
Vg =
o
ts
-o'2v
c*fsiry{,
€€t
ect
E
b
.J' of
102
o
c
\,
^N
,/t.f"tod=37rF
/ ,{
t-
ilti-sore
ring oscillator
oscil'lators were fabricated by the flat-gate SAINT
process. The gate length and width are 0.5, and
20 !ffi, respect'ive1y. The di stri buti on of
propagation delay time (tO6) and power dissipation
(PUir) in a 2-inch wafer measured at room
temperature are shown in Fig. 7, compared with
that of conventional SAINT ring oscillators.
Power dissipation dependences of propagation de'lay
t'ime are s'imul ated by the use of SPICE I I with
gate parasitic capacitances (zcp). According to
thi s simul ation, Cp of fl at-gate SAINT FETs
decrease by
4.5 fF/20 pm-gate-width.
the difference of
FET
patterns and the accuracy of
the S-parameter measurements or the
this
Considering
simulations,
of reduction is reasonable, compared
with the results of RF measurements. The minimum
propagati on de'l ay time measured at room
temperature is 29.4 ps/9ate ( 25.2 mt^l/gate ).
amount
100
E
H
r.0
Frequency (G Hz )
Fig. 5 Frequency dependence of Im( -Y..,)
Cno derived from Im(-Yrr) of a conventional and
a flat-gate SAINT FET (Lg=0.3
63, 37fF, respectively.
BFL
In order to confirm the high speed operation
of the flat-gate SAINT FET,17-stage BFL ring
/
I
\r/
2'0V
4.
l,r, Wn=200 pm) are
Voo = 3.0V
Vss =-2.0 V
^o
-(t 50
rtt
\ 40
3n
CL
\,
30
E
20
CL
t
Cp =3.5f
F o ipfCe U
o Convenfionol
o flot -gole
60
10
50
t00
Pdis (mW/gote )
40
a
Fig. 7
330
Propagat'ion delay t'ime versus power
pati
di ssi
on for 17-stage BFL ri ng osci I I ators.
.\l
-zo
are simulated by the use of
with gate parasitic capacitances (zCp).
These re'lationships
SPICE
10
II
of a flat-gate SAINT FET decreased by
4.5 fF/20 pm. (Lg=0.5 p, Wn=20 ;rm)
CO
0t
rr0
0. I
,
Frequency f (GHz )
Fig. 6 Frequency dependence of the current ga'in.
Cut-off frequency of a conventional and a
f'lat-gate SAINT FET are about 24 and 32 GHz,
'l,t)
respecti
20 30 4050
t0
vely.
(tg=0 .3 ,rm, Wn=200
5.
l./2 frequency d'ivider
The f 'lat-gate SAINT process i s appl ied to
fabrication of a b'inary frequency divider with a
BFL dual clocked master/slave flip-f1op.(5) rh.
BFL
gate length and width are 0.5 and 40 !m,
respect'ive1y. The d'i stri buti on of maximum toggl e
frequencies (ftoo.ru*) for standard biases
(VOO=3.0 V, VSS:-2.0 V) in a 2-'inch wafer are
shown in F'ig.8. Average tron.ru* of conventional
that of a conventional SAINT divider. Operation
at 9.2 GHz (power dissipat'ion of 290 mt,'l) was
achieved by optimizing bias vo'ltages. The
operating waveform is shown in Fig. 9.
and f'lat-gate SAINT d'ividers are 5.? and 7.4 GHz,
respectively. Operating frequency of a flat-gate
SAINT divider rises above ? GHz, compared w'ith
6.
Concl usion
A flat-gate
structure without the
excess gate metal overlapping the d'ielectric film
ized by newly developed
plana'lization technology by the use of ion beam
'large i nci dent angl e of j on beam.
mi'l 1 i ng wi th a
Thi s FET structure enabl e to decrease gate
successful
6
Conventionol r
5
L
real
paras'itic capac'itances by about 0.13-0.23 pF/mm )
according to the result of ring oscillator and RF
measurements. The binary frequency deviders us'ing
the flat-gate SAINT FET have successfully operated
up to 9.2 GHz, which is the highest frequency in
any semiconductor devices at room temperature.
In conclusion, the flat-gate SAINT is
advantageous in high speed and high frequency GaAs
+-f lot-gote
.94
E?
-v
-
=2
I
ICs.
0
6
7
I
9
Moximurn toggle frequency
7
distribut'ion of
Acknow'ledgements
the 'ion
to T.Honda for
s and M. H'i rayama ,
antati on
M.Suzuki, and M.Muraguchi for helpful discussions.
They also wish to thank M.Fujimoto, T.Ikegami and
T.Sugeta for their encouragement.
toggle
frequencies in 2-inch wafer for standerd biases
(VnD=3.0 V, VSS=-2.0 V). Averag. ftog.ru*.of
The
.
The authors are much indebted
(GHz)
Fig.8
1y
SAINT FET
maximum
proces
imp'l
conventional and flat-gate SAINT dividers are
5.2 and 7.4 GHz, respectively.
( tg=0 . 5
Fr, Wn=40 ;rm)
References
(1) M.0hmori:1lth international
symposium on
gallium arsenide and related
Biarritz, ( 1984) .
cl ock
'input
(2) K.Yamasaki,K.Asai,T.M'izutani,
0.58 V/div.
K.Kurumada
:
compounds,
and
Electron. Lett.,18, (1982),
pp.119-121.
output
(3)
K.Yamasaki,N.Kato, and M.Hirayama:
(4)
T.Takada,M.Togashi,M. Idda,K.Yamasaki, and
K.Hoshikawa:Paper of Tech. Group on So'lid
32 mV/div.
El
ectron. Lett .,?0,( 1984),pp. 1029-1031.
State Devices,IECE Japan,TGSSDB4-116,
Fig. 9 Response waveform of the binary frequency
divider operating at 9.2 GHz (power dissipation
290 ml,l). Clock Input: 0.7 V(peak-peak),
( 1985 ) , pp. 97 -104 .
(5)
K,0safune,K.0hwada, and N.Kato:Paper of
Tech. Group on Sol i
0utput: 83 mV(Peak-Peak).
d State
Japan,TGSSDS4-118, ( 1985
416
Devi ces , IECE
),pp. 113-118.