In Semiconductor Silicon 2002, H.R. Huff, L. Fabry, and S. Kishino, Editors, PV 2002-2, p. 774, The Electrochemical
Society Proceedings Series, Pennington, NJ (2002).
AVOIDING FURNACE SLIP IN THE ERA OF
SHALLOW TRENCH ISOLATION
Anthony E. Stephens
MEMC Electronic Materials
Silicon Engineering Technology Center
P.O. Box 9600, Sherman, Texas 75091-9600, USA
Although the silicon wafer is strong at room temperature, it is weak at
the elevated temperatures necessary for the fabrication of integrated
circuits. During thermal processing, a nonuniform elevated temperature
produces a nonuniform expansion within the wafer and the resulting lattice
forces can cause local or widespread furnace slip. This disrupts the silicon
crystal structure and permanently degrades the electrical and physical
characteristics of the wafer. Matters are made worse when shallow trench
isolation structures are built into the wafer surface. During thermal
cycling, the pressure oxide exerts on the silicon side-walls can create
dislocations or cause slip-dislocations to move into the device.
The causes of furnace slip are examined, and the effects on integrated
circuit yield and reliability are reviewed. Characterization methods and
the characteristic wafer failure modes are described. The factors that
influence the wafer’s resistance to furnace slip and the appropriate
corrective actions are discussed. A case study is used to describe how
shallow trench isolation structures and processing exacerbate the problem
of furnace slip.
INTRODUCTION
Decades of fabricating integrated circuits on silicon wafers have shown that furnace
slip is always a problem. This is because the fabrication engineer is always faced with
the conflicting goals of increasing the speed of furnace temperature ramps and push-pull
steps to maximize the furnace throughput, while at the same time limiting the speed of
temperature ramps and push-pull steps to prevent wafer warpage and the creation of
yield-killing slip dislocations. Each time the wafer diameter increased, a new balance
had to be found. Then, with the introduction of oxide-filled shallow trench isolation
(STI) structures, furnace recipes which had produced slip-free wafers previously became
recipes which produced massive furnace slip. In this paper we discuss actions that are
necessary to re-establish the balance between maximizing furnace throughput and
preventing dislocation creation in order to successfully fabricate integrated circuits with
STI structures.
We discuss in turn the basics of furnace slip, integrated circuit (IC) failure modes,
wafer characterization methods, wafer failure modes, and actions directed toward
Page 774
reducing furnace slip. Then we use a case study to discuss the additional actions
necessary to successfully process wafers with STI structures.
FURNACE SLIP
At room temperature, the single-crystal silicon wafer is elastic and brittle. If a small
mechanical stress such as a bending stress is applied, the wafer is temporarily deformed.
When the small stress is removed, the wafer returns to its original shape with its crystal
structure unchanged. But if an excessively large stress is applied to a wafer at room
temperature, it will fail due to brittle fracture.
During furnace processing at temperatures above about 750C (1), the wafer is elastic
and plastic. If a small mechanical stress is applied and then removed, the wafer will
deform and then return to its original shape with the crystal structure undamaged. But if
an excessively large stress is applied at an elevated temperature, the wafer will fail due to
plastic deformation (furnace slip). The furnace slip changes the shape of the wafer and
produces slip-dislocations (2-5).
During the thermal processing steps that are necessary for fabricating IC devices, the
wafer is subjected to numerous mechanical stresses. Stresses occur during heat-up and
cool-down because dissimilar materials used for IC construction expand and contract at
different rates. If not properly constructed, the boat or fixture used to hold the wafer
during thermal cycling can exert mechanical stresses on the wafer. If, during heat-up,
during annealing, or during cool-down, one part of the wafer is at a different temperature
than another part of the wafer, then the wafer is being subjected to internal mechanical
stresses due to nonuniform silicon expansion. The furnace slip that can occur in the
wafer due to a nonuniform temperature distribution will be described in some detail
below.
A nonuniform temperature distribution may or may not produce furnace slip. Slip is
more likely if the temperature is higher, if the temperature spatial gradient is higher, if the
amount of oxygen precipitation is higher, and if there are more surface or imbedded IC
features which create and concentrate the stress. Since the silicon becomes softer or
weaker with increasing temperature, the local temperature is an important factor in
determining where in the wafer the slip takes place. Slip begins with a shearing of the
layer of single covalent bonds between silicon atoms in adjacent {111} planes. As the
{111} planes slip with respect to each other, dislocations are created. Although the
change in wafer shape relieves some of the stresses caused by the nonuniform
temperature and expansion, the wafer will be deformed and new elastic stresses will be
present when the wafer returns to room temperature.
Furnace slip reduces IC fabrication yield and in some cases creates reliability
problems. If the wafer is warped or bowed too severely, it may not be possible to pull it
down on a vacuum chuck for subsequent lithography steps. If there is only local
deformation, pulling the wafer down on a vacuum chuck may cause the distorted part of
the wafer to be shifted laterally so the patterns on that part of the wafer are misaligned
with respect to the patterns elsewhere on the wafer. The dislocations that are produced
Page 775
during furnace slip are lines of silicon atoms that have no adjacent silicon atom to bond
to. Dislocations can serve as dopant diffusion pipes, so that IC junctions are not smooth
but spiked. Dislocations getter metallic impurity atoms and become highly conductive
paths. Dislocations with gettered metal atoms are effective generation and recombination
sites. Dislocations across junctions cause reverse bias junction leakage and increased IC
power consumption. Dislocations at storage capacitors can cause loss of stored DRAM
charge and pause refresh failure.
Several methods are available for characterizing furnace slip. The plot of a wafer’s
freestanding warp can be used to detect and diagnose large-scale slip. A warp plot is a
topographic map or a projected drawing that shows the shape of the wafer when it is not
clamped or pulled down on a vacuum chuck. Examples of warp plots are shown in Figs.
1 and 2.
Fig. 1: Freestanding warp plots of a {100} wafer that suffered severe furnace slip during
insertion into a furnace tube. The height contour lines show 2 µm intervals.
Fig. 2: Freestanding warp plots of a {100} wafer that suffered severe furnace slip during
withdrawal from a furnace tube. The height contour lines show 2 µm intervals.
An interference contrast microscope can be used to view slip steps on the wafer surface
or to view the dislocation etch pits produced by a defect etch. Figure 3 shows slip steps
and dislocation etch pits on the upper {100} surface of a wafer. Figure 4 shows
dislocation etch pits on the cleaved and etched {110} surface of a wafer.
Page 776
Fig. 3: The LEFT photo shows slip steps at the edge of a P{100} wafer as revealed by an
interference contrast microscope. The RIGHT photo shows dislocation etch pits at a P{100}
wafer surface after HF strip-back and 3 min Schimmel etch (6).
Fig. 4: The photo shows rows of diamond-shaped dislocation etch pits at the cleaved {110}
surface in the center of a P/P+{100} epi wafer. The cleaved surface was etched for 3 min in
Leo’s etch (7). Many large oxygen precipitation defects are also observed in the P+.
Other slip characterization methods include Makyoh (magic mirror) topography (8),
minority carrier recombination lifetime mapping (9), and scanning Lang transmission xray topography (10-12). Figure 5 shows an x-ray topography image.
Fig. 5: X-ray topography image of one edge of an in-process P{100} wafer after HF stripback and 3 min Schimmel etch. The black spots are damage sites on the back side of the
wafer and the many dark lines are dislocations in the wafer bulk.
Page 777
When a boat of wafers is inserted into a tube furnace, furnace slip can occur as
follows. The wafers are closely spaced in the furnace boat, and their initial temperature
is low and uniform. As the wafers move into the furnace tube, radiation from the furnace
tube heats up the outer edges of the wafers. Each wafer shadows the centers of the
adjacent wafers, so the wafer centers heat up more slowly than the edges. A similar
situation exists when the temperature of the furnace tube is ramped upward. The uneven
heating causes the temperature of the outer edge of each wafer to increase faster than the
temperature of the wafer center. The silicon around the wafer edge expands and softens
as the local temperature rises, but the silicon in the center of the wafer expands less and
remains stronger because of the slower rise in temperature there. If the stresses
developed by the nonuniform expansion become large enough, then silicon-to-silicon
bonds are sheared and the stresses are partially relieved by slip between individual {111}
planes in the softened outer edge of the wafer. In the more severe cases, the silicon slips
on many {111} planes and the net result is a bending of the softened silicon near the
wafer edge to accommodate the increased wafer circumference. This plastic deformation
creates many dislocations in localized regions near the wafer edge and causes the entire
wafer to be warped.
Figure 1 shows the typical shape of a wafer that has suffered severe furnace slip
during a furnace insertion or temperature ramp-up. The shape can be described as that of
a saddle, with two opposite <100> edges turned up and the other two <100> edges turned
down. Sometimes the wafer appears to be folded along one of the two <100> directions.
The highest densities of dislocations are found at the locations where the local curvature
is highest and are found at the surface which is locally concave (13).
When a boat of wafers is withdrawn from a tube furnace or the tube temperature is
ramped downward, furnace slip can occur as follows. The wafers are closely spaced in
the furnace boat and their initial temperature is high and uniform. As the wafer
environment is cooled, each wafer radiates energy from the edge and the temperature of
the wafer edge decreases faster than the temperature of the wafer center. The silicon
around the wafer edge shrinks and gets stronger as the temperature decreases, but the
silicon in the center of the wafer shrinks more slowly and remains softer due to the
slower decrease in the temperature there. The shrinking silicon around the wafer edge
squeezes the wafer center and increases any preexisting wafer bow. If the compressive
thermal stresses are great enough, then the stresses are partially relieved as inverted
pyramids of silicon (bounded by {111} planes) slip toward the wafer surface in the center
of the wafer on the concave side (3, 14, 15). In the more severe cases, plastic
deformation in the wafer center leads to high dislocation densities and severe permanent
bow.
Figure 2 shows the typical shape of a wafer that has suffered severe center slip
during a furnace withdrawal or a temperature ramp-down. The wafer is permanently
bowed. A high density of dislocations is found in the central region of the wafer and a
low density of dislocations is found at the wafer edge. As reported by Leroy and
Plougonven (3), the dislocations in the center of the wafer are found near the concave
surface. This is illustrated in Fig. 4. The wafer in Fig. 4 was bowed so that the front
surface was concave. During cooling, the shrinking periphery increased the amount of
Page 778
bow, putting the front surface into strong compression and causing slip to take place
there.
The IC failure pattern can sometimes provide a clue that furnace slip has taken place.
Figure 6 shows a case where too-rapid heating created slip-dislocations at the wafer
edges and a case where too-rapid cooling created dislocations in the wafer center on the
concave side.
Fig. 6: IC leakage failure patterns due to furnace slip. The leakage fail pattern on the
LEFT was caused by dislocations created by rapid edge-first heating of a P{100} wafer. In
this case the wafer was not highly warped, but slip-dislocations were concentrated at the
four <100> edges. The black-dot leakage fail pattern on the RIGHT was caused by rapid
edge-first cooling of the P/P+{100} wafer shown in Fig. 4.
AVOIDING FURNACE SLIP
Furnace slip can be avoided, or at least reduced to a tolerable level, by reducing the
nonuniform expansion and contraction within the wafer and by managing the stresses
caused by nonuniform expansion and contraction. Factors which affect the silicon
wafer’s strength and the associated corrective actions are discussed in this section. Issues
related to STI structures and dissimilar materials are discussed in the next section.
Slip begins when the component of stress that is directed along a {111} plane
exceeds the critical stress that is required to shear the silicon-to-silicon bonds between
{111} planes. This critical shear stress decreases with increasing temperature, so the
wafer becomes weaker or softer as the temperature increases.
A sense of how the wafer becomes more susceptible to furnace slip as the
temperature is increased from 700C to 950C is shown in Fig. 7. In this simple
experiment (16), bare 150mm P{100} wafers were placed on a fixture which supported
the wafers around the edge. Each wafer was heated to a given temperature and then
subjected to a bowing stress for 1 min by applying a vacuum to the bottom side of the
wafer so that the air pressure was 240 torr higher on the top side of the wafer than on the
bottom. Depending on the temperature of the wafer, this caused some amount of center
slip and plastic deformation. After cooling, the amount of permanent bow was measured.
Figure 1 shows why slip is much more likely to occur during an 800C furnace insertion
or withdrawal as compared to a 750C insertion or withdrawal. When the furnace tube is
Page 779
at 800C, the insertion/withdrawal rate must be made quite low to prevent the center-toedge temperature difference in the wafer from becoming so large that slip takes place.
Permanent Bow after 1 min Stress
10
Bow (mm)
8
6
4
2
0
700
750
800
850
900
950
Temperature (C)
Fig. 7: This graph shows the loss of wafer strength as the temperature is increased (16).
The experimental conditions are described in the text.
The wafers become progressively weaker as the temperature is increased to higher
values, and the furnace temperature ramp-up and ramp-down rates must be progressively
reduced to prevent slip. Table I gives ramp rates that have given slip-free results for
200mm wafers in a variety of wafer fab processes, but without shallow trench isolation.
Table I. Acceptable Furnace Ramp Rates for an 1150C Anneal of 200mm Wafers.
Temperature
Range
750C - 1000C
1000C - 1100C
1100C - 1150C
Ramp-Up
Rate
7 C/min
3 C/min
2 C/min
Temperature
Range
1150C - 1100C
1100C - 1000C
1000C - 750C
Ramp-Down
Rate
2 C/min
3 C/min
3 C/min*
The value marked * could be 7 C/min if the furnace has fast-ramp capability. For
temperatures near 1200C, a 1 C/min ramp rate is generally necessary. The values in
Table I are for a 4.75 mm wafer-to-wafer spacing in the furnace boat. One can use a
wider wafer spacing in order to reduce the center-to-edge temperature difference and the
stress. Nilson and Griffiths have developed analytical models of furnace processing (17)
and given a relation for calculating the wafer center-to-edge temperature difference
during furnace temperature ramping (18). This relation can be used to calculate the
influence of wafer spacing and wafer dimensional factors.
Dissolved oxygen strengthens the wafer by pinning dislocations (19-22). However,
oxygen precipitation weakens the wafer by depleting the dissolved oxygen and by
punching out additional dislocations at the growing oxygen precipitates. The weakening
effect of oxygen precipitation is shown in Fig. 8 (23). In this experiment, wafers with an
initial dissolved oxygen concentration of 30 ppma (24) were annealed for various times at
1050C to induce oxygen precipitation. Dog-bone shaped tensile test samples were cut
from the wafers and subjected to tensile testing at 800C in order to measure the upper
yield stress. The upper yield stress is the stress at which dislocations begin to multiply
Page 780
rapidly due to the extension of the sample. The graph in Fig. 8 shows that the silicon
strength had been reduced to about 1/5 the original value after the dissolved oxygen
concentration had been reduced from 30 ppma to 10 ppma (20 ppma precipitation).
Loss of Wafer Strength
Upper Yield Stress at 800C
2
(1E6 N/m )
60
50
40
30
20
10
0
0
5
10
15
20
Oxygen Precipitation (ppma79)
25
Fig. 8: The loss of silicon wafer strength due to oxygen precipitation is shown by these
tensile test results (23, 24). The experimental conditions are described in the text.
For all wafers, the main strategy for avoiding furnace slip is to heat and cool the
wafers in such a way that the center-to-edge temperature difference stays small enough
that thermal stress due to nonuniform expansion is always less than the critical shear
stress at the current wafer temperature. When the amount of oxygen precipitation is large
(like that in the wafer shown in Fig. 4), then one must either make the furnace process
extra gentle or reduce the amount of oxygen precipitation to avoid furnace slip.
AVOIDING FURNACE SLIP IN WAFERS WITH SHALLOW TRENCH ISOLATION
With the integration of shallow trench isolation (STI) into new IC fabrication
processes, it became clear that the creation of dislocations during furnace processing had
once again become a major problem (25). To produce STI structures, trenches are
plasma etched into the silicon surface, the trenches are filled with CVD oxide, a
densification anneal is done to fill gaps in the oxide (and to anneal out etch damage), and
excess oxide is removed by CMP. Fig. 9 shows a typical cross section.
Fig. 9: Sketch of STI cross section. After reference (26).
Page 781
Since the thermal oxidation of silicon expands the volume by about 2.25, the
subsequent thermal oxidation of the trench side walls expands the width of the oxide
"D1" and puts the silicon into compression "C" and tension "T". The dashed lines in Fig.
9 separate the compressive and tensile regions and the black dots show the locations of
maximum compression or tension (26). Several workers have discussed the stress the
STI fill oxide exerts on the silicon. They have pointed out the benefits of minimizing the
effects of oxide wedge growth (25-27), as well as minimizing the silicon stress by using a
wider STI trench (26-27) or perhaps using a fill with voids (28).
However, the contraction of the silicon wafer during furnace cooling has the same
effect. As the wafer temperature decreases, the silicon contracts roughly 10 times as fast
as the oxide (29). So in Fig. 9, the distance "D2" shrinks much faster than the distance
"D1". At high temperatures, the oxide tends to flow and relieve the stress, but the oxide
becomes two orders of magnitude more viscous for each 100C decrease in temperature
(26). As the wafer cools toward the withdrawal temperature, the oxide becomes stiff
while the wafer is still hot enough for dislocations to be created. If the wafer bows
during cooling so that the front side is concave, the compressive stress of bowing would
add to the existing stresses. Bowing could explain the spot of high diode leakage in the
center of the wafer of reference (28).
Figure 10 shows typical STI dislocations.
Fig. 10: SEM photos of STI structures after fab processing, HF strip-back, and a brief
Schimmel etch. The LEFT photo shows a dislocation threading from the bottom corner of
one trench to the bottom corner of the adjacent trench. The RIGHT photo shows a
dislocation threading through the silicon pillar.
A series of furnace slip experiments was done over a time that included two
generations of STI-technology devices. Figure 5 shows an x-ray topography image for a
200mm wafer with STI structures which had been through an 1150C oxide densification
anneal with ramp rates similar to those shown in Table I. Dislocations were present
2
along edge slip lines at the front surface of the wafer, affecting an area of 20 cm . A
companion wafer without STI structures showed no dislocations at the front surface. The
slip evident in Fig. 5 was initiated at spots of contact damage on the wafer back side.
Some of this damage occurred due to contact with the vertical furnace boat slots during
the densification anneal and some occurred during prior processing steps. Figure 11
shows a backside damage spot after the anneal. Figure 11 shows local slip with
dislocations punched out in <110> directions along the surface. X-ray topography also
showed dislocations punched out in the <110> directions below the surface toward the
front surface of the wafer.
Page 782
Figure 12 shows dislocations associated with laser scribe marks. In this case, many
dislocations were observed in the STI region away from the scribe marks, but few were
observed immediately adjacent to the scribe marks where no STI structures were present.
Fig. 11: The photo shows punched-out
dislocations around a backside contact
damage spot after STI anneal, strip-back
and 5 min Schimmel etch.
Fig. 12. The x-ray topography image shows
dislocations associated with, but not
immediately adjacent to, the laser scribe
marks.
In these experiments, dislocations at the front surface of the wafer were found along
slip lines near the wafer edges, but not in the central region. In many cases, the
dislocation etch pits were tear-drop shaped and arranged as closely spaced pairs along a
slip line. These were evidently short, shallow dislocation loops lying between the {111}
planes where the wafer had slipped. During furnace temperature ramp-up, the edge-first
heating causes the wafer to experience a compressive hoop stress around the edge. This
compressive hoop stress may have combined with the localized stress within the STI
structures to create local dislocation loops. Alternatively, the local STI stress may have
trapped pinched-off sections of a slip-dislocation. Whatever the sequence of events,
dislocations within the device are detrimental.
Based on the series of STI furnace slip experiments, the following advice can be
offered for fabricating devices with STI:
1) The furnace ramp rates for 200mm wafers must be somewhat slower than those
shown in Table I. (The ramp rates near the maximum temperature were the most
important.)
2) The oxide densification anneal should be done at a relatively low temperature.
(Reducing the anneal temperature from 1150C to 1050C to 1000C gave less slip.)
3) The technology and tool for doing the CVD oxide deposition should be carefully
chosen based on experiment. (Slip varied widely from TEOS deposition tool to tool. A
high density plasma tool worked well.)
4) The insertion/withdrawal temperature should be low. (After other factors were
optimized, 650C gave slightly better results than 750C.)
5) Re-optimize for each new (smaller) version of the STI-containing device. (If the
STI trench becomes narrower, the oxide will be less compressible.)
Page 783
CONCLUSION
During furnace processing, a nonuniform elevated temperature produces a
nonuniform expansion within the wafer and the resulting lattice stress can cause local or
widespread furnace slip. This problem is made worse when shallow trench isolation
structures are built into the wafer surface. After oxidation and during thermal cycling,
the stress the isolation oxide exerts on the silicon, plus the stress caused by nonuniform
wafer expansion can create dislocations or cause slip-dislocations to move into the
leakage-sensitive parts of the IC device. But by moderating both the furnace stress and
the internal stress, IC devices with STI structures can be fabricated successfully.
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