0921 Digital System Experiment
Page 1 , Total 5
Members:資工二 A 942864 邱逸夫、資工二 A 942862 陳哲豪
Group No.19
DIGITAL SYSTEMS EXPERIMENT REPORT 3
Signed-Twos Complement Adder/Subtractor
1. Use two 4-bit DIP switches to set 0 or 1 as inputs of the signed-twos complement adder/subtractor.
2. Use a DIP switch to control the function of addition or subtraction. Light a yellow LED to indicate the
function of subtraction. Use red and green LEDs to show 1s in the input numbers and in the output
numbers, respectively.
Part
Qty Part
Qty Part
Qty Part
Qty
DIP switch (4-bit)
3 7404 (NOT)
2 7483 (4-bit adder)
2 7486 (XOR)
3
LED (yellow)
1 7410 (NAND)
2 7400 (NAND)
2 7483
1
LED (red)
8 7411 (AND)
2 7401 (NAND)
2 0.22Kohm R
14
LED (green)
5 7432 (OR)
2 7402 (NOR)
2 1Kohm R
9
Hints: You may convert signed-magnitude binary to two’s complement.
A3A2A1A0+B3B2B1B0=S4S3S2S1S0
No overflow will occur if the sum has five bits.
Consider the following examples and then decide S4.
Ex:
# Case
Original I/O
Fixed
#
Case
Original I/O
Fixed
1 1+2=3
7+7=14
0001+0010=0011
0111+0111=1110
00011
01110
3
-1+(-1)=-2
-8+(-8)=-16
1111+1111=1110
1000+1000=0000
11110
10000
2 2+(-1)=1
-1+2=1
0010+1111=0001
1111+0010=0001
00001
00001
4
1+(-8)=-7
-2+1=-1
0001+1000=1001
1110+0001=1111
11001
11111
Decimal Twos complement Decimal Twos complement
4-bit
5-bit
4-bit
5-bit
0
0000
00000
1
0001
00001
-1
1111
11111
2
0010
00010
-2
1110
11110
3
0011
00011
-3
1101 11101
4
0100
00100
-4
1100 11100
5
0101
00101
-5
1011 11011
6
0110
00110
-6
1010 11010
7
0111
00111
-7
1001 11001
8
01000
-8
1000 11000
9
01001
-9
10111
10
01010
-10
10110
11
01011
-11
10101
12
01100
-12
10100
13
01101
-13
10011
14
01110
-14
10010
Page 2 , Total 5
Group No.19
0921 Digital System Experiment
Members:資工二 A 942864 邱逸夫、資工二 A 942862 陳哲豪
2. Make block diagram by using below ICs:
IC
GATE IN PACKAGE
GATE USED COUNT
7483(4-bit adder)*2
4-bit adder
-
7486(XOR)*1
2-input XOR Gate*4
4
3. Other parts used list:
NAME
USED COUNT
DIP switch (4-bit)
3
1K Ohm resister
9
0.22K Ohm resister
13
LED (green)
4
LED (red)
8
LED (yellow)
1
A1
INPUT
VCC
INPUT
VCC
Date: November 06, 2006
A2
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
INPUT
VCC
A3
A4
B1
B2
B3
B4
Control
inst4
inst5
XOR
inst6
XOR
XOR
inst7
XOR
7483
7483
S1
S2
S3
S4
C4
FULL ADDER
A1
B1
A2
B2
A3
B3
A4
B4
C0
report3.bdf*
inst
C0
S1
S2
S3
S4
C4
FULL ADDER
A1
B1
A2
B2
A3
B3
A4
B4
inst1
Page 1 of 1
OUTPUT
OUTPUT
OUTPUT
OUTPUT
OUTPUT
S5
S4
S3
S2
S1
Project: report3
Revision: report3
Page 4 , Total 5
Group No.19
0921 Digital System Experiment
Members:資工二 A 942864 邱逸夫、資工二 A 942862 陳哲豪
5. Verilog HDL file.[NOTE: only show the top level design HDL file.]
module report3(
A1, A2, A3, A4, B1, B2, B3, B4, Control,
S1, S2, S3, S4, S5
);
input
input
input
input
input
input
input
input
input
output
output
output
output
output
A1;
A2;
A3;
A4;
B1;
B2;
B3;
B4;
Control;
S1;
S2;
S3;
S4;
S5;
wire
wire
wire
wire
wire
SYNTHESIZED_WIRE_9;
SYNTHESIZED_WIRE_1;
SYNTHESIZED_WIRE_2;
SYNTHESIZED_WIRE_3;
SYNTHESIZED_WIRE_5;
₩7483
b2v_inst(.B4(SYNTHESIZED_WIRE_9),
.C0(Control),.A1(A1),.A2(A2),.B1(SYNTHESIZED_WIRE_1),.B2(SYNTHESIZED_WIRE_2),.A3(A3),
.B3(SYNTHESIZED_WIRE_3),.A4(A4),.S3(S3),.S4(S4),.S2(S2),.C4(SYNTHESIZED_WIRE_5),.S1(S
1));
₩7483
b2v_inst1(.B4(SYNTHESIZED_WIRE_9),
.C0(SYNTHESIZED_WIRE_5),.A1(A4),.A2(A4),.B1(SYNTHESIZED_WIRE_9),.B2(SYNTHESIZED_WIRE_
9),.A3(A4),.B3(SYNTHESIZED_WIRE_9),.A4(A4),.S1(S5));
assign SYNTHESIZED_WIRE_1 = Control ^ B1;
assign SYNTHESIZED_WIRE_2 = Control ^ B2;
assign SYNTHESIZED_WIRE_3 = Control ^ B3;
assign SYNTHESIZED_WIRE_9 = Control ^ B4;
endmodule
0 ps
8 us
2.68 s
Date: November 06, 2006
A4
A3
A2
A1
B4
B3
B2
B1
Control
S5
S4
S3
S2
S1
5.37 s
8.05 s
10.74 s
16.11 s
db/report3.sim.vwf
13.42 s
Page 1 of 8
18.79 s
21.47 s
24.16 s
26.84 s
32.0 s
Project: report3
29.53 s
Revision: report3
32.0 s
34.68 s
Date: November 06, 2006
A4
A3
A2
A1
B4
B3
B2
B1
Control
S5
S4
S3
S2
S1
37.37 s
40.05 s
42.74 s
48.11 s
db/report3.sim.vwf
45.42 s
Page 2 of 8
50.79 s
53.47 s
56.16 s
58.84 s
64.0 s
Project: report3
61.53 s
Revision: report3
64.0 s
66.68 s
Date: November 06, 2006
A4
A3
A2
A1
B4
B3
B2
B1
Control
S5
S4
S3
S2
S1
69.37 s
72.05 s
74.74 s
80.11 s
db/report3.sim.vwf
77.42 s
Page 3 of 8
82.79 s
85.47 s
88.16 s
90.84 s
96.0 s
Project: report3
93.53 s
Revision: report3
96.0 s
Date: November 06, 2006
A4
A3
A2
A1
B4
B3
B2
B1
Control
S5
S4
S3
S2
S1
101.37 s
106.74 s
db/report3.sim.vwf
112.11 s
Page 4 of 8
117.47 s
122.84 s
Project: report3
128.0 s
Revision: report3
128.0 s
Date: November 06, 2006
A4
A3
A2
A1
B4
B3
B2
B1
Control
S5
S4
S3
S2
S1
133.37 s
138.74 s
db/report3.sim.vwf
144.11 s
Page 5 of 8
149.47 s
154.84 s
Project: report3
160.0 s
Revision: report3
160.0 s
Date: November 06, 2006
A4
A3
A2
A1
B4
B3
B2
B1
Control
S5
S4
S3
S2
S1
165.37 s
170.74 s
db/report3.sim.vwf
176.11 s
Page 6 of 8
181.47 s
186.84 s
Project: report3
192.0 s
Revision: report3
192.0 s
Date: November 06, 2006
A4
A3
A2
A1
B4
B3
B2
B1
Control
S5
S4
S3
S2
S1
197.37 s
202.74 s
db/report3.sim.vwf
208.11 s
Page 7 of 8
213.47 s
218.84 s
Project: report3
224.0 s
Revision: report3
224.0 s
Date: November 06, 2006
A4
A3
A2
A1
B4
B3
B2
B1
Control
S5
S4
S3
S2
S1
229.37 s
234.74 s
db/report3.sim.vwf
240.11 s
Page 8 of 8
245.47 s
250.84 s
Project: report3
256.0 s
Revision: report3