The 2004 IEEE Asia-Pacific Conference on
Circuits and Systems, December 6-9,2004
SYMBOL-SPACED DELAY CIRCUIT DESIGN WITH HALF-RATE
CLOCK TIMING FOR MULTI-TAPS FIR FILTER AS PRE-EMPHASIS
Mia0 Li, Tad Kwasniewski, Peter Noel
Department of Electronics, Carleton University, Ottawa, Ontario, Canada
mili@,doe.carleton.ca, [email protected], pnoel(iZ,doe.carleton.ca
a clocwdata recovery module. The backplane channel
typically consists of a transmit daughter card, a
backplane, a receive daughter card and connectors.
ABSTRACT
A FIR filter for pre-emphasis has been used to
counteract inter-symbol interference ( I S ) in high-speed
backplane data transmission. A novel circuit design for
retiming data using a half-rate clock for the taps of a FIR
filter is proposed. HSPICE simulation results for CMOS
0.18 um technology verify that the jitter of PRES15
(2"-l) data at rate of 6.25 Gbps with a pre-emphasis
value of 50% can be reduced to approximately 14 psec
and thereby alleviating the requirement on clock
frequency.
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Figure 1 Configuration of a transceiver interface
1. INTRODUCTION
The high-speed serial interface, which significantly
reduces U 0 pin count and increases the maximum
bandwidth per pin is replacing the conventional
low-speed parallel bus for use in backplane
communications. IS1 is the major factor limiting the
maximum distance and data rate of backplane data
transmission. The use of a symbol-spaced FIR filter for
pre-emphasis at the transmit side of the circuit is a
widely used technique for reducing IS1 [l, 2, 31.
Traditionally, the delayed data for multi-tap FIR filters
are obtained by employing single-edge-triggered D
flip-flops (DFF) with full-rate clocking. A novel circuit
design using double-edge-triggered flip-flops (DETFF)
with half-rate clock timing for delaying the data in a
symbol space period is proposed.
In this paper, a symbol-spaced FIR filter is
introduced in section 2. The proposed circuit for
delaying the data in a symbol-space period with half-rate
clock timing is given in section 3. HSPICE simulation
results in section 4 provide verification proof that the
circuit is functional and finally section 5 concludes the
paper.
FIR filter pre-emphasis can be implemented in
current-mode-logic (CML) structure, as shown in Figure
2(a) (5 tap example shown here). Traditionally, data is
delayed for multi-taps of a FIR filter by employing
DFFs, as shown in Figure 2(b). A DFF is made of two
CML-structured D latches, which is shown in Figure
2(c). With the fust tap set as +1, all post-taps in Figure
2(a) are negative. The +/- sign of the post-taps can be
realized by exchanging the differential inputs to the
MOS gate in Figure 2(c). This can be done using XOR
logic with a sign-controlling signal, as shown in Figure
2(4.
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2. SYMBOL-SPACED FIR FILTER
Figure 1 shows a transceiver interface, including
pre-emphasis, a channel, DC coupling, an equalizer and
0-7803-8660-4/04/$20.0002004 IEEE
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Figure 2(a) 5-tap FIR filter pre-emphasis, (b) data
retiming, (c) D latch, and (d) XOR logic.
This method of implementing a data retiming
circuit 'requires a full-rate clock for timing the
single-edge-triggered DFFs to obtain the symbol space
delayed data sequence for the FIR filter. To alleviate the
requirement on clock frequency, a novel circuit is
proposed in the following section.
3. PROPOSED RETIMING CIRCUIT
The stmcture of the proposed data retiming circuit is
shown in Figure 3(a). It employs eight
double-edge-triggered flip-flops (DETFF) to generate
five symbol-space delayed data sequences with half-rate
clock timing. Two DFFs operating 00 opposite clock
phases along with a multiplexer form a DETFF [4, 51, as
shown in Figure 3(b).
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Figure 3(a) Proposed data-retiming circuit with half-rate
clock; (b) structure of DETFF.
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The clock signals for the multiplexer inside of the
DETFF are connected positively or negatively. DATAn
with o from 0 through 4 as in Figure 3(a) represents the
symbol-space delayed data sequence in order.
Figure 4 Eye diagrams for absolute pre-emphasis values
of (a) 0.48, (b) 0.22, and (c) 0.02.
The maximum jitter is about 11 psec at the
pre-emphasis value of -0.48. With 5 post-tap values of 1,
-0.48, +0.06, -0.02 and -0.02 applied, the retimed data
with up to 4-symbol delays are shown in Figure 5(a) and
the eye diagrams are superimposed in Figure 5(b). The
jitter due to delay among the retimed data is about 8psec.
4. HSPICE SIMULATION RESULTS
The proposed data retiming circuit and a 5-tap FIR filter
pre-emphasis circuit, as an example, are generated in
HSPICE with parameters from CMOS 0.18um
technology. A 6.25 Gbps PRBS15 data sequence and a
clock at a frequency of 3.125 GHz are used, with 20% of
the clock period used as peak-to-peak riselfall time.
The eye diagrams of output data with absolute
pre-emphasis values (post-tap values) of 0.48, 0.22, and
0.02 are shown in Figure 4(a), (b) and (c) respectively.
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The pre-emphasis tap values are obtained through
FIR filter optimization, which is based on the least-mean
square (LMS) algorithm [7]. The pre-emphasis circuit
can be used to compensate for the channel loss of 34
inches of FR4 backplane.
5. CONCLUSION
In order to counteract the IS1 effect due to channel loss,
FIR filter pre-emphasis is a widely used technique. A
circuit employing double-edge-triggered flip-flops with
half-rate clock timing is proposed to obtain
symhol-space delayed data for post-taps of a FIR filter.
HSPICE simulation results using CMOS O.1Sum
technology verify that the deterministic jitter at the near
end of channel with a pre-emphasis value of 50% is only
approximately 14 psec. Although the proposed circuit
consumes more power than the traditional data retiming
circuit, it employs a half-rate instead of a full-rate clock,
thus is quite appropriate for high-speed backplane data
transmission.
6. REFERENCES
[l] C . - H. Lin, C. - H. Wang, and S. - J. Jou, “5 Ghps
serial link transmitter with pre-emphasis”, Asia and
South Pacific Design Automation Conference, 2003,
Proceedings of the ASP-DAC 2003, pp. 795-800, 21-24
Jan. 2003.
Figure 5(a) Retimed data up to 4-symbol delays; @)
superimposed eye diagrams of retimed data.
The eye diagram at the near-end of channel, which
is the output of pie-emphasis circuit, is shown in Figure
6 with a deterministic jitter of about 14psec, mainly due
to incomplete settling voltage on intemal nodes. Another
jitter contribution comes from the duty cycle distortion
of the clock. Duty cycle control circuits may he
necessary for high-speed serial communications [6].
Compared with full-rate clock retiming circuit, the
half-rate retiming circuit achieves higher speed for a
given technology.
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[2] J. Zerbe, et al, “Equalization and clock recovery for a
2.5-10Gbps 2-PAW4-PAM backplane transceiver cell”,
ISSCC Digest of Technical Papers, paper 4.6.2003.
[3] R. Farjad-Rad, C. - K. K. Yang, M.A. Horowitz, and
T. H. Lee, “A 0.4-um CMOS lO-Gb/s 4-PAM
pre-emphasis serial link transmitter”, Journal of
Solid-State Circuits, ~01.34,no.5, pp. 580-585, May
1999.
[4] A. Pottbacker, U. Langmann, and H. U. Schreiber, “
A Si bipolar phase and frequency detector IC for clock
extraction up to 8 Gbls”, Journal of Solid-State Circuits,
vo1.27,no.l2,pp. 1747-1751, Dec, 1992.
of ,:honnsi
r - X - - - - - 7 ~
[SI J. Savoj, and B. Razavi, “A lO-Gb/s CMOS clock
and data recovery circuit with a half-rate binary
phaselfrequency detector”, Journal of Solid-State
circuits, vo1.38, no. 1, pp. 13-21, fan. 2003.
[6] K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa,
M. Yotsuyanagi, “A CMOS 50% duty cycle repeater
using complementary phase blending”, in IEEE VLSI
Circuits Symp., June 2000, pp. 48-49.
Figure 6 Eye diagram at near end of channel with
pre-emphasis tap values of 1, -0.48, +0.06, -0.02, -0.02
applied.
[7] M. Li, S. Wang, Y. Tao, and T. Kwasniewski, “FIR
filter optimization as pre-emphasis of high-speed
backplane data transmission”, Electronics Letters,
vo1.40, issue 14, July 2004.
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