International Journal of Electronics
2008, 1–16, iFirst article
Coupling delay calculation using Miller factors under exponential
waveforms
Selahattin Sayil* and Uday Kiran Borra
Department of Electrical Engineering, Lamar University, Beaumont, USA
Downloaded By: [Sayil, S.] At: 23:17 3 February 2009
(Received 21 October 2008; final version received 6 November 2008)
The increase in interconnect delay due to coupling can have a dramatic effect on
the circuit performance for nanoscale technologies. Calculation of couplinginduced delay using a traditional circuit simulator is computationally inefficient,
and hence alternative prediction models are desirable. In this work, we revisit
Miller factor (MF) based methodology for realistic exponential waveforms for the
very first time. It was previously argued that for exponential inputs, the MFs
could be more than 3 for worst case and less than 71 for best-case delay
estimation. We have found the correct MFs corresponding to the worst case and
best-case scenarios under exponential inputs and formulated for the partial
overlapping case. Simulation results are shown for both worst-case and the bestcase MFs and results are compared with the coupled RC network for 50% delay.
We obtained an average error of 2.7% on worst-case and 3.3% on best-case delay
using the MF derived for exponential waveforms. This model is useful as a quick
reference in verifying a large number of nets for delay estimation.
Keywords: integrated circuits; interconnect modelling; circuit delay; Miller factor;
delay modelling
1.
Introduction
The change in wire delay due to cross-coupling noise can have deleterious effects on
the performance of today’s deep sub-micron IC technologies. The increased delays
occur when an aggressor (switching neighbour line) switches in the reverse direction
to the victim line (affected line). An aggressor can also cause decreased delays when
switching in the same direction as the victim. The increase/decrease in delay can
violate the setup or hold time requirements for logic storage circuits.
Crosstalk-induced delay estimation using traditional simulation tools such as
industry standard HSpice is computationally expensive and inapplicable to full-chip
analysis (Sapatnekar 2000). Alternative techniques are desirable to ensure signal
integrity in a limited design cycle time. To determine the impact of crosstalk on the
signal propagation delay, many papers have focussed on techniques to directly
decouple multiple lines into an equivalent isolated line by using a Miller factor (MF)
or a Switch factor (Chen, Kirkpatrick and Keutzer 2000; Kahng, Muddu and Sarto
2000; Sapatnekar 2000). Depending on the switching activities on the neighboring
*Corresponding author. Email: [email protected]
ISSN 0020-7217 print/ISSN 1362-3060 online
Ó 2008 Taylor & Francis
DOI: 10.1080/00207210802654463
http://www.informaworld.com
Downloaded By: [Sayil, S.] At: 23:17 3 February 2009
2
S. Sayil and U.K. Borra
wire, the coupling capacitance is converted into an equivalent Miller capacitance that
is connected to ground from each node, thus decoupling the victim line from the
aggressor for timing calculation purposes. The derived worst-case/best-case MFs can
be used in resolving set-up time/hold time violations of storage elements.
The decoupling MFs are very easy to use and integrate into an existing static timing
analysis. Some noise-aware static timing engines also use switching windows to
determine if noise is important. Most of these engines utilise worst-case and best-case
MFs to find an initial solution (Franzini, Forzan, Pandini, Scandolara Dal Fabbro
2000; Tehrani, Chyou and Ekambaram 2000). In timing analysis, traditionally MFs
were taken as either 0 or 2 depending on the switching activity on neighbouring lines.
For example, a ground capacitance of two times the coupling capacitor was taken if
signals switch simultaneously in opposite directions (worst-case estimation). When
signals switch in the same direction, the equivalent capacitance was assumed to be
zero, corresponding to best-case delay estimation.
However, the work by Kahng et al. (2000) and Chen et al. (2000) showed that the
actual correct lower and upper bounds on MFs were –1 and 3 corresponding to bestand worst-case delay estimation. Their work considered differing slew rates for
aggressor and victim line waveforms and utilised saturated ramp functions to
approximate real waveforms.
It has been strongly recommended that aggressor and victim waveforms should
be represented by exponential functions rather than saturated ramps (Kahng et al.
2000; Agarwal, Cao, Sato, Sylvester, and Hu 2002; Sato, Cao, Agarwal, Sylvester
and Hu 2003). In practice, a coupling capacitor experiences exponential waveforms
rather than ramp waveforms on the nodes that it is connected to. Kahng et al. (2000)
also argue that 3Cc and –Cc may not be the correct upper and lower bounds for
realistic exponential waveforms and suggest the use of even higher (i.e. 4Cc for
opposite switching). Miller capacitances for exponential type inputs.
Our aim is to explore whether an MF larger than 3 does exist for non-linear
waveforms such as exponential inputs. Therefore, in this work we derive MFs for
worst-case and best-case delay for saturated exponential input waveforms. The
previous works by Kahng et al. (2000) and Chen et al. (2000) verify only the worstcase MFs and do not show any verification on the negative MF corresponding to
best-case delay scenario. In this work, we verify both MFs and show the results in
tabular form.
Owing to difficulty in working with exponentials, we use a piece-wise linear
approximation to derive average worst-case and best-case MFs. We derive a partial
overlap formulation for opposite switching which can be utilised during delay
calculation.
The inductance effect has been important in recent high performance designs for
delay calculation. However, capacitive coupling effect remains as the dominant
factor. Therefore, in this work, we only consider the capacitive coupling effect
(Heydari and Pedram 2005).
The article is organised as follows. Section 2 explains the MF analysis. The worstcase MF for exponential input waveforms is derived in Section 3. In this section, we
also discuss the partial overlap case and obtain an equivalent capacitance formula
for the victim. In Section 4, we obtain best-case MFs, which can be used for victim
speed-up calculations. We verify both MFs using industry standard HSpice software with parameter values derived in 0.13 mm technology, and results are given
in Section 5.
International Journal of Electronics
2.
3
MF analysis
In MF analysis, the coupling capacitance between two neighbour wires is replaced by
an equivalent capacitance to ground for each line as shown in Figure 1 so that delay
calculated can easily be performed using the isolated wires. We use the simple model
shown in Figure 1 to illustrate MF calculation. In Figure 1, aggressor and victim
nodes are shown by ‘A’ and ‘V,’ respectively. Using the Kirchoff’s Current law at
victim node:
Ceq ðVÞ
dVV
dVV
dVA
¼ CC
CC
dt
dt
dt
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Ceq ðVÞ ¼ CC
dVA =dt
1
dVV =dt
ð1Þ
ð2Þ
If VA and VB switch in the same direction simultaneously with RA ¼ RV and
CA ¼ CV, then dVA/dt ¼ dVV/dt. This means the MF is equal to ‘0’ for same side
switching. For the case where VA and VV having opposite transitions with RA ¼ RV
and CA ¼ CV, we obtain dVA/dt ¼ 7dVV/dt. Then we obtain us an MF of ‘2’ for
opposite switching. The MF derived here is based on the worst-case assumption that
signals at the victim and aggressor switch simultaneously with no skew.
Later work by Kahng et al. (2000) considered differing slew rates for aggressor
and victim line waveforms. Owing to different driver strengths, we can have a fast
rising/falling aggressor while having a slow victim waveform. This allows more
charge to dump through the coupling capacitor to the victim. In this case, it is
possible to obtain MFs as high as 3 for opposite switching and as low as 71 for
same direction switching assuming saturated ramp voltages (Kahng et al. 2000).
Kahng et al. (2000) argue that MFs 3 and –1 corresponding to worst-case and
best-case delay scenarios may not be correct upper and lower bounds for exponential
type waveforms. As the coupling capacitor sees exponential waveforms rather than
ramp waveforms on its terminals, the aggressor and victim waveforms should be
represented by exponential functions rather than saturated ramp functions (Kahng
et al. 2000; Agarwal et al. 2002; Sato et al. 2003). However, correct MF values
corresponding to exponential cases were never shown to our knowledge. Therefore,
in the next section, we extend this work and calculate the MF in the case of saturated
exponential waveforms.
Figure 1.
MF calculation.
4
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3.
S. Sayil and U.K. Borra
Worst-case MF calculation
Owing to difficulty working with exponential waveforms, a piece wise linear
approximation has been used to represent rising and falling exponential waveforms.
Figure 2 shows how a rising unit exponential can be represented closely by a piecewise linear approximation (dashed line) using only five segments.
In the model, the first segment represents the waveform in between 0 5 t 0.5tr. Similarly, second segment is taken between 0.5tr 5 t tr due to rapid
changing nature of the waveform. The third segment is taken between the tr and 2tr
time points. Finally, the fourth and fifth segments approximate the waveform during
2tr 5 t 3tr. and 3tr 5 t 5tr, respectively. At t ¼ 5tr, it is assumed that the
exponential waveform saturates. VDD value is taken as 1 V for all waveforms during
all MF derivations. The average error between the exponential function and the
piecewise linear representation is calculated to be less than 2.5%.
To obtain worst-case delay estimation, we assume a strong aggressor implying a
fast switching aggressor compared to victim driver as shown in Figure 3. As shown
in the figure, aggressor waveform is taken as a rising exponential and the victim is
assumed a falling exponential waveform. To have maximum delay effect on the
victim, the aggressor should complete its transition before the victim reaches the
50% level, which is defined as victim threshold in this work.
Figure 4 shows the close-up view of the aggressor waveform in Figure 3, and
indicates the six regions generated for MF calculation. It is assumed that aggressor
starts its transition ta after victim waveform started its transitioning, and completes
its switching before the victim reaches the 50% threshold level. The rising aggressor
exponential has an associated time constant tr1 as shown.
Figure 2.
Piece-wise linear representation for rising exponential waveform.
Downloaded By: [Sayil, S.] At: 23:17 3 February 2009
International Journal of Electronics
Figure 3.
Fast switching aggressor vs. victim waveform.
Figure 4.
Regions generated for MF calculation.
5
In derivations, we assume that the victim fall time constant tr2 is at least seven
times (5tr1 ¼ 0.69tr2) larger than the aggressor rise time constant, so that the whole
aggressor transition completes before victim reaches the 50% threshold.
Figure 5 shows the slow switching victim waveform (falling exponential). Here,
tr2 is the fall time constant associated with the victim waveform. Only one segment of
piece-wise linear approximation is utilised during the MF calculation since the
aggressor is assumed to complete its transition during this very first segment.
6
S. Sayil and U.K. Borra
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Figure 5.
One segment representation shown for the victim waveform.
Based on the five-segment representation in Figure 4, there are seven distinct
regions to consider in MF calculation. We will first find equivalent capacitances for
each region, and then calculate a time average worst-case equivalent capacitance
over all regions.
The first region (R1) is defined during 0 5 t 5 ta. In this region, victim starts
falling but aggressor does not start until ta. In this case because the aggressor is at
logic 0, the equivalent coupling capacitance is:
CeqR1 ðVÞ ¼ CC
ð3Þ
The second region (R2) is between ta5 t (ta þ 5tr1), in this case we refer to
Equation (2) for equivalent capacitance which can also be rewritten as:
CeqR2 ðVÞ ¼ CC
jdVA =dtj
1þ
jdVV =dtj
ð4Þ
where
dVA/dt is the slope of corresponding aggressor segment,
dVV/dt is the victim slope calculated from the first segment (Figure 5).
Finally, for segment 1 (see Figures 2 and 4), we have:
0:393=0:5tr1
CeqR2 ðVÞ ¼ Cc 1 þ
0:5=0:693tr2
or
tr2
CeqR2 ðVÞ ¼ Cc 1 þ 1:09
tr1
ð5Þ
7
International Journal of Electronics
The third region R3 (second segment) is defined during (ta þ 0.5tr1) 5 t (ta
tr1), then:
ð0:632 0:393Þ=0:5tr1
CeqR3 ðVÞ ¼ Cc 1 þ
0:5=0:693tr2
or
tr2
CeqR3 ðVÞ ¼ Cc 1 þ 0:661
tr1
ð6Þ
During the fourth region (ta þ tr1) 5 t (ta þ 2tr1), the equivalent capacitance:
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tr2
CeqR4 ðVÞ ¼ Cc 1 þ 0:323
tr1
ð7Þ
Similarly for the fifth region (ta þ 2tr1) 5 t (ta þ 3tr1),
tr2
CeqR5 ðVÞ ¼ Cc 1 þ 0:119
tr1
ð8Þ
The sixth region (R6) is defined for (ta þ 3tr1) 5 t (ta þ 5tr1):
tr2
CeqR6 ðVÞ ¼ Cc 1 þ 0:035
tr1
ð9Þ
Finally, in the seventh region (R7), aggressor voltage is constant at 1 V while the
victim decreases towards its 50% threshold point. Because the voltage difference
across coupling capacitor Cc is less than the one in Region 1, we may expect an
equivalent capacitance which is:
CeqR7 ðVÞ CC
ð10Þ
Because we will be calculating an average MF over complete regions, having this
region will reduce the MF. However, the average worst-case MF will be maximum if
we eliminate R7 by increasing aggressor arrival time ta. In this case, the aggressor
finishes its transition right before the victim reaches its 50% voltage threshold. Based
on this assumption, time average of worst-case equivalent coupling capacitance at
victim node can be calculated:
Ceq ðVÞ ¼
tA ðCeqR1 Þ þ 0:5tr1 ðCeqR2 Þ þ 0:5tr1 ðCeqR3 Þ þ tr1 ðCeqR4 Þ
þtr1 ðCeqR5 Þ þ 2tr1 ðCeqR6 Þ
0:693tr2
ð11Þ
8
S. Sayil and U.K. Borra
where
tA ¼ 0:693tr2 5tr1
After inserting Equations (3), (5)–(9) into Equation (11), we obtain the average
worst-case Miller capacitance at victim node:
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Ceq ðVÞ ¼ 2:998 ffi 3:0Cc
ð12Þ
which suggests that the worst-case MF is 3.
This value is same as the one obtained for saturated ramp inputs by Kahng et al.
(2000). Kahng et al. suggest the use of 4CC or greater equivalent capacitance for
exponential waveforms in worst-case coupling delay estimation. However, this will
result in overly pessimistic delay calculations for coupled RC interconnects. Our
result here shows that even for exponential input waveforms, the equivalent coupling
capacitance at the victim node is not greater than 3Cc, which contradicts the
assumption by Kahng et al. (2000).
We have obtained the MF for the victim using a fast rising aggressor and slow
falling victim waveform. Similar results can also be obtained for the case with a fast
falling exponential aggressor and slow rising victim.
The above result can be further verified using a simple formulation that has been
described below. Now, referring to Figure 6, the current leaving the victim node via
coupling capacitor Cc should be equal to the current on the equivalent victim
capacitance Ceq(V) for matching purposes, i.e.:
Cc
dVV dVA
dVV
¼ Ceq ðVÞ
dt
dt
dt
ð13Þ
For obtaining worst-case MF, we assume the aggressor waveform finishes its
transition before the victim reaches its threshold, which is taken typically as the 50%
voltage value. The time that corresponds to the 50% point on victim waveform is
0.69tr2.
Figure 6.
Equivalent circuit for worst-case MF formulation.
9
International Journal of Electronics
Assuming zero initial conditions, both sides of the above equation can be
integrated over 0 t 0.69tr2 time interval. In other words, during this interval, we
can equate the charges on both Cc and Ceq(V):
0:69tr2 Z
Cc
0
dVV dVA
dt
dt
Z
0:69tr2
¼ Ceq ðVÞ
0
dVV
dt
ð14Þ
Then, we have:
Cc ½VV ð0:69tr2 Þ VV ð0Þ VA ð0:69tr2 Þ þ VA ð0Þ ¼ Ceq ðVÞ½VV ð0:69tr2 Þ VV ð0Þ
Downloaded By: [Sayil, S.] At: 23:17 3 February 2009
Cc ð0:5 1 1 þ 0Þ ¼ Ceq ðVÞð0:5 1Þ
We obtain, Ceq(V) ¼ 3Cc This is the same result that we had previously found
using Equation (12).
3.1. Partial overlap of aggressor and victim waveforms
The worst-case coupling delay effect occurs if a fast aggressor starts its rising
transition after slow victim started transitioning, and completes its switching before
victim reaches the 50% threshold level. This is assumed as the full overlap case. In
reality, signals can start and end anytime. If the whole aggressor transition does not
take place during 0 t 0.69tr2, then we have less than a full overlap or a partial
overlap.
The overlap duration can be expressed as KA 6 tr1, where KA is the overlap
constant and tr1 is the aggressor rise time constant. For full overlap KA is assumed to
be 5 and for partial overlapping it is in the range 0 5 KA 5 5.
To obtain a general formula for partial overlapping, we take piecewise segments
at regular distances in time as shown in Figure 7. Initially, 0.5 6 tr1 distance has
been selected for each segment. Figure 7 shows such a model with 10 different
segments. The slow victim waveform is modelled using only one segment
representation as in Figure 5.
For partial overlapping, KA is in the range 0 5 KA 5 5, but has to be stated in
multiples of 0.5 due to the resolution chosen in piece-wise linear model. We can
define the resolution by a constant r, which is equal to 0.5 in our case.
Based on Figure 7, we can calculate an equivalent capacitance for each region (in
case it exists):
For region 1 during 0 5 t 5 ta, we have:
CeqR1 ðVÞ ¼ CC
ð15Þ
During region 2 which is between ta 5 t (ta þ 0.5tr2), we obtain:
ðe0 e0:5 Þ=0:5tr1
CeqR2 ðVÞ ¼ Cc 1 þ
0:5=0:693tr2
ð16Þ
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10
S. Sayil and U.K. Borra
Figure 7.
Representation using 10-segments.
For region 3, during (ta þ 0.5tr1) 5 t (ta þ tr1):
ðe0:5 e1 Þ=0:5tr1
CeqR3 ðVÞ ¼ Cc 1 þ
0:5=0:693tr2
ð17Þ
Similarly, we can find the MFs for the remaining eight regions. Knowing that the
above equations have a pattern, the time-averaged equivalent coupling capacitance
for partial overlap case can be written:
"
! !#
iþ1
i
2KA
X
1
e 2 e2
Ceq ðVÞ ¼
ð0:69tr2 KA tr1 ÞCc þ 0:5CC
tr1 þ 1:39 tr2
0:69tr2
0:5
i¼1
ð18Þ
The formula above is valid for exponential waveforms at nodes A and V
(Figure 5) with victim fall time constant tr2 being at least seven times larger than the
aggressor rise time constant tr1. In this case, full aggressor transition takes before
victim reaches the 50% threshold.
In most cases, overlap KA may not be a multiple of 0.5. In this case, a smaller
resolution constant r should be chosen (i.e. r ¼ 0.1). The smaller value of r results in
increased accuracy due increased resolution. In this case,
"
ðiþ1Þr ir #
K
A =r
X
1
e
e
ð0:69tr2 KA tr1 ÞCc þ rCC
tr1 þ 1:39 Ceq ðVÞ ¼
tr2 ð19Þ
0:69tr2
r
i¼1
where 0 5 KA 5 5 and KA ¼ cr with c ¼ 1 . . . 5/r
International Journal of Electronics
11
If overlap amount KA ¼ 0, we obtain a static capacitance of Cc which is expected.
With this formula, we can also verify the full overlap case which should give the
worst-case MF. Assuming a resolution constant r ¼ 0.1, for the full overlap case with
KA ¼ 5 one can obtain an equivalent coupling capacitance of 3Cc at the victim node.
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4.
Best-case MF calculation
In this case, aggressor driver switches in the same direction as the victim driver, but
transitions much faster. Aggressor and victim voltages have been taken as falling
exponential waveforms with fall time constants tr1 and tr2, respectively. It is also
assumed that the aggressor driver is strong and it completes its transition before the
victim waveform reaches its 50% switching threshold (Vref) (tr1 5 tr2/7). According to
Figure 8, there are six distinct regions to consider during equivalent capacitance
calculation. During MF calculation, only one segment of piece-wise linear approximation is considered for the slow switching victim waveform since the aggressor is assumed
to complete its transition during this first segment for best-case delay (Figure 5).
It is also assumed that the victim and aggressor drivers start their falling
transition simultaneously with ta ¼ 0. In this case, the maximum victim signal speedup occurs (Kahng et al. 2000). Referring to Figure 8, the first segment approximates
the waveform between (0 5 t 0.5tr1). For equivalent capacitance calculations, we
refer to Equation (2) which can be rewritten as:
jdVA =dtj
CeqR1 ðVÞ ¼ CC 1 ð20Þ
jdVV =dtj
Figure 8.
Fast switching aggressor vs. slow victim waveform.
12
S. Sayil and U.K. Borra
The equivalent capacitance during first region (R1) can be written as:
tr2
CeqR1 ðVÞ ¼ Cc 1 1:09
tr1
ð21Þ
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The second region (R2) is defined during (0.5tr1 5 t 5 tr1). For region 2:
tr2
CeqR2 ðVÞ ¼ Cc 1 0:661
ð22Þ
tr1
The remaining regions are defined as follows: The third region is taken between
the tr1 and 2tr1 time points. During the fourth (R4) and fifth regions (R5), segments
approximate the waveform during 2tr1 5 t 3tr1 and 3tr1 5 t 5tr1, respectively.
At t ¼ 5tr1, it is assumed that the exponential waveform reaches zero. The equivalent
capacitances for 3rd, 4th and 5th regions can be calculated as follows:
tr2
CeqR3 ðVÞ ¼ Cc 1 0:323
ð23Þ
tr1
tr2
CeqR4 ðVÞ ¼ Cc 1 0:119
tr1
tr2
CeqR5 ðVÞ ¼ Cc 1 0:035
tr1
ð24Þ
ð25Þ
Finally, in the sixth region (R6), aggressor voltage remains constant at 0 V while
the victim waveform falls towards the 50% threshold point. We may expect an
equivalent capacitance near Cc as the voltage difference on the coupling capacitor is
smaller. Based on this assumption, time average of best-case equivalent coupling
capacitance at victim node can be calculated:
Ceq ðVÞ ¼
0:5tr1 ðCeqR1 Þ þ 0:5tr1 ðCeqR2 Þ þ tr1 ðCeqR3 Þ þ tr1 ðCeqR4 Þ
þ2tr1 ðCeqR5 Þ þ ð0:693tr2 5tr1 ÞðCeqR6 Þ
0:693tr2
ð26Þ
After substituting Equations (21)–(25) into Equation (26), we find the equivalent
coupling capacitance at victim node for best-case delay to be:
Ceq ðVÞ ¼ Cc
ð27Þ
Here, we obtain the best-case MF as 71. These results suggest that the lower and
upper bounds on MFs for realistic exponential inputs remain the same at 71 and 3
corresponding to best and worst-case delay calculations.
We can further verify Equation (27) by using a current formulation. Referring to
Figure 9, the current through coupling capacitor Cc should be same as the current
through the equivalent victim capacitance Ceq(V), namely:
dVV dVA
dVV
ð28Þ
Cc
¼ Ceq ðBÞ
dt
dt
dt
International Journal of Electronics
13
Assuming zero initial condition, we can integrate both sides of Equation (28)
over 0 t 0.69tr2 time interval:
Cc ½VV ð0:69tr2 Þ VV ð0Þ VA ð0:69tr2 Þ þ VA ð0Þ ¼ Ceq ðVÞ½VV ð0:69tr2 Þ VV ð0Þ
Cc ð0:5 1 0 þ 1Þ ¼ Ceq ðBÞð0:5 1Þ
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This would give Ceq(V) ¼ 7Cc as in Equation (27).
5. Simulation results
The MFs have been verified using industry standard HSpice software with parameter
values derived in TSMC 0.13 mm technology. We assume two parallel wires on
Metal3 which are modelled by using many segments of p networks, i.e. every 100 mm
wire is modelled using a p-network in HSpice. For a 2-mm wire, there were 20-p
segments representing the RC distributed interconnect. Coupling capacitors were
also distributed along the line as shown in Figure 10.
The sheet resistance of metal interconnect in this technology is 0.074O/square.
For a wire width 0.2 mm, the per unit length capacitance and resistance values for
each wire are 0.0226 fF/mm and 0.37O/mm, respectively. We assume aggressor and
Figure 9.
Figure 10.
Equivalent circuit for best-case MF formulation.
Two parallel coupled interconnect network.
14
S. Sayil and U.K. Borra
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victim lines are driven by identical inverters of size 31.2 mm/10.4 mm and the loads at
the end of the wires are also identically sized inverters.
We first simulated for 50% victim delay using the two-line circuit with distributed
coupling capacitances in between. Then, the coupled network was reduced to an
equivalent victim line with coupling capacitance scaled by an MF as shown in
Figure 11. We repeated the 50% victim delay simulation with the isolated victim line
and compared results with coupled victim line delay to see how closely the MFs
approximate to the coupled model.
In our experiments, we vary aggressor and victim interconnect resistances,
ground and coupling capacitances to study the effects of varying interconnect
lengths, widths and spacing. The parameter ranges are taken as follows: The
aggressor and victim wire resistances are varied in between 20 and 250O, the ground
and coupling capacitances are changed from 50 to 300 fF. In addition, we examine
differing exponential rise/fall time constants on the inputs of both lines.
Table 1 summarises the results obtained for worst-case MF. For each case,
aggressor arrival time has been adjusted for worst possible delay on the victim. For
Figure 11.
Table 1.
Case
no.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Isolated victim line.
Experimental results obtained for the worst-case MF.
Aggressor/
victim
rise/fall time
constant
Ragg
(O)
Rvic
(O)
Cagg
(fF)
Cvic
(fF)
Cc
(fF)
MF ¼ 3
MF ¼ 4
Coupled
RC network
30/300
80/600
50/450
50/400
60/500
60/500
100/750
100/750
100/750
60/700
60/700
100/800
50/600
40/400
75/600
100/800
50/400
40/550
50/400
100/800
100
100
160
80
250
160
30
70
150
60
100
20
50
100
200
100
220
20
100
100
120
100
80
70
160
240
20
60
150
80
140
25
50
120
200
100
200
20
120
200
50
60
90
60
120
100
100
140
100
150
250
100
60
100
100
100
80
70
100
80
60
60
60
80
100
120
120
120
100
200
300
100
60
150
100
100
80
80
150
220
100
140
160
150
130
200
170
220
150
170
140
200
280
300
50
200
120
180
250
300
352
627
522
477
560
638
777
827
773
771
784
837
733
609
557
851
468
620
575
994
382
669
564
515
603
693
824
873
839
817
832
891
789
642
577
909
503
663
631
1070
351
624
522
472
547
616
781
821
768
771
779
839
725
585
553
843
455
615
555
972
Delay in ps
15
International Journal of Electronics
Table 2.
Downloaded By: [Sayil, S.] At: 23:17 3 February 2009
Case
no.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Experimental results obtained for the best-case MF.
Aggressor/
victim
rise time
constant
Ragg
(O)
Rvic
(O)
Cagg
(fF)
Cvic
(fF)
Cc
(fF)
Delay with
MF of
71 (pS)
Coupled
RC network
(pS)
jerror %j
30/300
80/600
50/450
50/400
60/500
60/500
100/750
100/750
100/750
60/700
60/700
100/800
100/800
100/800
120/900
100
100
160
80
250
160
30
70
150
60
100
20
100
100
200
120
100
80
90
160
240
20
80
150
80
140
25
100
200
200
50
60
90
160
120
100
100
140
100
150
250
100
100
110
100
60
60
120
180
100
140
120
170
100
200
300
100
100
240
100
100
100
100
250
130
75
170
220
150
170
110
150
150
300
250
243
452
337
316
391
443
550
544
557
557
633
505
590
576
622
256
463
343
340
416
450
555
570
573
563
640
518
595
616
655
5.08
2.38
1.75
7.06
6.01
1.56
0.90
4.56
2.79
1.07
1.09
2.51
0.84
6.49
5.04
the 20 cases considered, the worst-case MF of 3 produced very accurate delay results
(an average error of only 2.69%) compared with coupled RC network delay.
Almost for all cases, there was no underestimation on worst-case delay when
using an MF of 3 for exponential inputs. We also include the results for the MF of 4
since it was suggested by Kahng et al. (2000). Results show that a factor greater than
3 results in overly pessimistic worst-case delay calculations for coupled RC
interconnects and should be avoided. For some cases, an equivalent coupling
capacitor of 4Cc gives an error as large as 14% compared with coupled RC network.
Table 2 shows the 15 different cases examined for best-case MF. Previously, for
ramp inputs an MF of 71 was suggested as a bound for best-delay calculation
(Chen et al. 2000; Kahng et al. 2000). However, the verification on the negative MF
has not been done. Here, we show the results for victim speed-up under exponential
inputs for the coupled RC circuit as well as for the isolated victim network. The 50%
voltage point has been taken as the reference in our delay calculation.
In our experiments, we vary aggressor and victim interconnect resistances,
ground and coupling capacitances to study the effects of varying interconnect
lengths, widths and spacing and examine differing exponential time constants on the
inputs of both lines. The results show that for the cases considered absolute error
remains less than 7% for all cases, and the average error obtained is only 3.3%.
6. Conclusion
We revisited MF based methodology for realistic exponential waveforms for the very
first time. In practice, a coupling capacitor sees exponential waveforms rather than
ramp waveforms on the nodes that it is connected to. It was previously argued that
under exponential inputs, the MFs could be more than 3 for worst-case, and less
than 71 for best-case delay estimation.
16
S. Sayil and U.K. Borra
We studied MF based methodology for worst-case and best-case delays and
found that 3 and 71 are indeed the worst-case and best-case bounds for delay
calculation even for non-linear exponential input waveforms. Our results here shows
that for worst-case delay under exponential input waveforms, the equivalent
coupling capacitance at victim node is not greater than 3Cc, which contradicts the
assumption by Kahng et al. (2000). We showed that using an MF greater than 3
would result in overly pessimistic delay calculations for coupled RC interconnects.
We have verified best-case and worst-case MFs using HSpice software with
parameter values derived in TSMC 0.13 mm technology. Simulation results for bestcase and worst-case MFs have been compared with the coupled RC network for
50% delay. We obtained an average error of 2.7% on worst-case and 3.3% on bestcase delay using the MF derived for exponential case.
Downloaded By: [Sayil, S.] At: 23:17 3 February 2009
References
Agarwal, K., Cao, Y., Sato, T., Sylvester, D., and Hu, C. (2002), ‘Efficient generation of delay
change curves for noise-aware static timing analysis’, in Proceedings of Asia and South
Pacific Design Automation Conference, pp. 77–84.
Chen, P., Kirkpatrick, D.A., and Keutzer, K. (2000), ‘Miller factor for gate-level coupling
delay calculation’, in International Conference on C.A.D. (ICCAD), pp. 68–74.
Franzini, B., Forzan, C., Pandini, D., Scandolara, P., and Dal Fabbro, A. (2000), ‘Crosstalk
aware static timing analysis: a two step approach,’ in Proceedings of ISQED, pp. 499–503.
Heydari, P., and Pedram, M. (2005), ‘Capacitive coupling noise in high-speed VLSI circuits’,
IEEE Transactions on CAD, 24, 478–488.
Kahng, A.B., Muddu, S., and Sarto, E. (2000), ‘On switch factor based analysis of coupled RC
interconnects’, in Proceedings of Design Automation Conference, pp. 79–84.
Sapatnekar, S.S. (2000), ‘Capturing the effect of crosstalk on delay’, in Proceedings of 13th
International Conference on VLSI Design, pp. 364–369.
Sato, T., Cao, Y., Agarwal, K., Sylvester, D., and Hu, C. (2003), ‘Bidirectional closed-form
transformation between on-chip coupling noise waveforms and interconnect delay change
curves’, in IEEE Transactions on CAD, 22, pp. 560–572.
Tehrani, P.F., Chyou, S.W., and Ekambaram, U. (2000), ‘Deep submicron static timing
analysis in presence of crosstalk,’ in Proceedings of ISQED, pp. 505–512.