Creep Behaviors of Flip Chip on Board With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints
Creep Behaviors of Flip Chip on Board With
96.5Sn-3.5Ag and 100In Lead-Free Solder Joints
John H. Lau and Stephen H. Pan
Agilent Technologies, Inc.
350 W. Trimble Road, MS 90LJ
San Jose, California 95131
Phone: 408-435-4836
Fax: 408-435-6983
e-mail: [email protected]
Abstract
Time-dependent nonlinear analysis of lead-free solder bumped Flip Chip on Printed Circuit Board (PCB) assemblies subjected to
thermal cycling condition is presented in this study. Two different lead-free solder alloys are considered, namely, 96.5wt%Sn-3.5wt%Ag
and 100wt%In. The 62Sn-36Pb-2Ag solder alloy is also considered to establish a baseline. All of these solder alloys are assumed to
obey the Garofalo-Arrhenius creep constitutive law. The shear stress, the shear creep strain hysteresis loops, the shear stress history,
and the shear creep strain history at corner solder joint are presented for a better understanding of the thermal-mechanical behaviors
of lead-free solder bumped Flip Chip on PCB assemblies. Also, a very simple and cost-effective procedure is presented for the creep
analysis of Flip Chip solder joints by using ANSYS.
Key words:
Creep, Lead-free Solder Alloys, Flip Chip, and Nonlinear Finite
Element Method.
1. Introduction
The low-cost tin-lead solders have been used as joining materials in the electronics industry for many years1-5. The unique
physical and mechanical properties of the tin-lead solders have
facilitated Printed Circuit Board (PCB) assembly choices that
have fueled creative advance packaging developments, such as
solder bumped Flip Chips1,2,3,4, Ball Grid Array (BGA) packages3,5,
and Chip Scale Packages (CSP)1,2,3. For these packaging technologies, the low-cost Sn-Pb solder is the electrical and mechanical
“glue” of the PCB assemblies.
Since 1992, different bills have been introduced at the U.S.
Congress to ban lead from a wide variety of uses which include
solders. The reasons are, among others, (a) lead and its compounds are ranked as one of the top 10 hazardous materials and
(b) lead is the number one environmental threat to children. Many
major electronics companies, national laboratories, universities,
research organizations, and solder vendors worldwide responded
by initialing research programs to eliminate lead from solders6-32.
In North America, for example, the world’s first lead free
circuit telephone produced by NORTEL Networks in 199729. The
Company used the eutectic 99.3Sn-0.7Cu to replace Sn-Pb solder for both surface mount and through-hole components. In
Europe, the European Union proposes to ban all lead in electronic products by the year 2004.
In Japan, some electronic manufacturers have announced voluntary plans to reduce their use of lead in solders. For examples,
Hitachi aimed to reduce their use of lead by half during 1999
compared to 1997 levels and to stop using lead solders by 2001.
(Sn-Bi-Ag type alloys are Hitachi’s favorite). NEC intends to
reduce lead use in solders by 50% by 2002 compared to the usage
in 1997. (Sn-Ag and Sn-Ag-Cu alloys are NEC’s choice). NTT
intends to only purchase equipment safe for the environment (i.e.,
no lead or cadmium) by 2001. SONY wants to reduce the usage
of lead solders but has not yet set a target date. (SONY developed
the Sn-2Ag-4Bi-0.5Cu-0.1Ge for their own products). Matsushita
The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)
© International Microelectronics And Packaging Society
11
Intl. Journal of Microcircuits and Electronic Packaging
aims to stop using lead solders by 2001. (Matsushita picks SnAg-Bi-x alloys).
It is interesting to point out that “green” products sell! For
example, Matsushita’s market share of its lead-free MiniDisc
player jumped from 4.6 to 15 percent in 6 months in Japan. With
the pressure of “green” products, one of the challenges is to find
an alternative solder alloy that is as cost effective, manufacturable, and reliable as the industry standard eutectic tin-lead or
high-lead solders. Unfortunately, there are no drop-in replacements22.
In this study, two lead-free solder alloys are considered,
96.5wt%Sn-3.5wt%Ag and 100wt%In. The melting point for
96.6Sn-3.5Ag and 100In solder alloys are 221oC and 156.6oC,
respectively, and thus, each of them has some unique applications. The 62Sn-36Pb-2Ag solder alloy is also considered to establish a baseline. From cost point of view, 100In is the most
expensive, and of course, 62Sn-36Pb-2Ag is the cheapest.
In this study, the focus is not on manufacturability but on the
solder joint reliability with these lead-free solder alloys on PCB.
Only thermal cycling loadings are considered. Emphasis is placed
on the creep behaviors of these lead-free solder joints in Flip
Chip on PCB assemblies and is not on the life prediction of these
solder joints.
with underfill encapsulant. It can be seen that the PCB is 1.575
mm thick and is made of FR-4 Epoxy glass. The copper pad
thickness is 0.018 mm. The underfill is about 0.07 mm thick and
is made of silica filler and bis-phenol-type epoxy and trade secret
resins.
5.66 mm
Y
Z
0.508 mm
0.508 mm
X
Si
FR4
0.0686 mm
(underfill)
0.508 mm
Solder joint and copper pad
1.575 mm
8 mm
Figure 2. Dimensions of Finite Element model.
0.0686 mm
Copper Pad
Thickness 0.0178 mm
2. Boundary-Value Problem
0.1016 mm
2.1. The Structure
Figure 1 schematically shows the silicon chip under consideration. The dimensions of the chip are: 8mm x 8mm x 0.51 mm.
It has peripheral pads (0.1mm x 0.1 mm) with a spacing of 0.1
mm. All the pads have solder bumps and the bump height is
about 0.1 mm.
8mm
Section of
FEM
Modeling
Y
Z
X
Figure 3. Dimensions of solder and copper pad.
2.2. Material Properties
Figure 4 shows a typical Finite Element model for creep analysis of the lead-free solder bumped Flip Chip on board assemblies. Since the focus is on the solder joint, finer meshes are used
to model it. The Finite Element code used in this study is ANSYS,
release 5.6.133. It can solve boundary-value problems with
Garofalo-Arrhenius creep constitutive equation expressed as follows5,
n
8 mm
dγ
 G 
 τ 
 Q 
= C   sinh  ω  exp −

dt
 Θ 
 G 
 kΘ 
(1)
Where ! is the creep shear strain, d!/dt is the creep shear strain
rate, t is the time, C is a material constant, G is the temperaturedependent shear modulus, " is the absolute temperature (oK), #
defines the stress level at which the power law stress dependence
breaks down, $ is the shear stress, n is the stress exponent, Q is
Pad 0.1 mm
Spacing ≈ 0.1 mm
the activation energy for a specific diffusion mechanism (for example, dislocation diffusion, solute diffusion, lattice self-diffuFigure 1. Schematic of a 8x8 mm2 chip.
sion, and grain boundary diffusion), and k is the Boltzmann’s
Figures 2 and 3 show the solder bumped Flip Chip on PCB
constant (8.617 x 10-5 eV/oK). For 62Sn36Pb2Ag, 96.5Sn3.5Ag,
The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)
12
© International Microelectronics And Packaging Society
Creep Behaviors of Flip Chip on Board With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints
and 100In solder alloys, the material constants of Equation 1
have been experimentally determined by Darveaux and Banerji6
with a single hyperbolic sine function given by the following
relationship5, 6 ,
1.E+00
62Sn36Pb2Ag_27C
96.5Sn3.5Ag_27C
100In_27C
62Sn36Pb2Ag_100C
1.E-01
1.E-02
96.5Sn3.5Ag_100C
100In 100C
1.E-03
1.E-04
n

dγ
 τ 
 Q
= Asinh   exp −

dt
 kT 
 B 

1.E-05
(2)
1.E-06
1.E-07
1.E-08
Table 1 shows the values of constant n, Q, A, and B. Equations
(2) for these three solder alloys at 27oC and 100oC are plotted in
Figure 5. It can be seen that: (1) for all the solder alloys, the
higher the stress the higher the steady state creep strain rate; (2)
for all the solder alloys, the higher the temperature the higher the
steady state creep strain rate; (3) for all temperatures, the steady
state creep strain rate of the 100In is much larger than that of the
62Sn36Pb2Ag and 96.6Sn3.5Ag; (4) for all stress levels, the
steady state creep strain rate of the 100In is much larger than
that of the 62Sn36Pb2Ag and 96.6Sn3.5Ag; (5) for all operating
temperatures and for most of the operating stresses, the steady
state creep strain rate of 62Sn36Pb2Ag is larger than that of
96.5Sn3.5Ag, especially for higher temperatures and lower
stresses; and (6) for very high stresses, which seldom occur, the
steady state creep strain rate of 62Sn36Pb2Ag becomes smaller
than that of 96.5Sn3.5Ag.
Y
Z
X
1.E-09
1.E-10
1.E+01
1.E+02
1.E+03
1.E+04
Shear Stress (psi)
Figure 5. Steady state creep in shear (Equation (2)).
If the solder materials obey the von Mises criterion1, then
Equation (2) can be written as follows,
dε
 C 
C
= C1 [sinh (C2σ )] 3 exp − 4 
dt
 T 
(3)
where C1, C2, C3, and C4 are given in Table 2 for the three solder
alloys under consideration. It should be noted that Equation (3)
is exactly the same form of input for implicit creep model (TBOPT
= 8) of ANSYS, Release 5.6.133. In Equations (2) and (3), % is the
uniaxial stress, d!/dt is the uniaxial creep strain rate. The unit
for % and $ is in lb/in2 (psi).
Table 2. ANSYS input for implicit creep analysis (Creep
Model 8).
dε
 C 
C
= C1 [sinh(C 2σ )] 3 exp − 4 
dt
 T 
Solder joint
Solder Alloys
C1
(1/sec)
C2
(1/psi)
C3
C4
(°°K)
62Sn36Pb2Ag
462(508-T)/T
1/(5478-10.79T)
3.3
6360
96.5Sn3.5Ag
18(553-T)/T
1/(6386-11.55T)
5.5
5802
100In
40647(593-T)/T
1/(274-0.47T)
5
8356
Figure 4. Finite Element model.
Table 1. Fitted equations from shear creep test results.
n

dγ
 τ 
 Q 
= Asinh   exp −

dt
 B 
 kT 

Solder Alloys
n
Q (eV)
A
(1/sec)
B
(psi)
62Sn36Pb2Ag
3.3
0.548
801(508-T)/T
3163-6.23T
96.5Sn3.5Ag
5.5
0.5
31(553-T)/T
3687-6.67T
100In
5
0.72
70400(593-T)/T
158-0.27T
Note: T is absolute temperature in °K.
(For ANSYS Release 5.6.1 inputs, C2 and C3 should be interchanged.)
The material properties of the silicon chip, FR-4 PCB, copper, and underfill are shown in Table 3. Figures 6 (CTE = coefficient of thermal expansion) and 7 (E = Young’s modulus) show
the temperature dependence of the underfill.
Note: T is absolute temperature in °K.
The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)
© International Microelectronics And Packaging Society
13
Intl. Journal of Microcircuits and Electronic Packaging
Table 3. Material properties of Flip Chip assemblies.
Material
properties
Poisson’s
ratio
(ν
ν)
0.35
0.4
100In
Underfill
Young’s
modulus
(MPa)
34,441-152T
52,708 -67.14T
-0.0587T2
2,200
9,292 -35.4T
Si
FR4
Copper
131,000
22,000
76,000
0.3
0.28
0.35
62Sn36Pb2Ag
96.5Sn3.5Ag
0.4
0.35
the PCB; and (2) the behavior of solder below -20oC is not very
well understood. Five full cycles are executed.
CTE (α
α)
ppm/°°C
120
24.5
21.85
+0.02039T
32.1
31.0395
+0.0923T
2.8
18
17
100
80
60
40
20
0
-20
-40
0
2000
4000
6000
8000
10000
12000
14000
16000
18000
20000
Time(s)
(sec)
Note: Temperature, T, in °C.
Figure 8. Temperature boundary condition.
43
41
39
3. Creep Responses of Lead-Free
Solders
37
35
33
31
29
3.1. Hysteresis Loops
27
25
-20
0
20
40
60
80
100
120
Temperature (C)
Figure 6. Coefficient of thermal expansion (CTE) for
underfill.
11000
10000
9000
8000
7000
6000
5000
For creep analysis, it is important to study the responses for
multiple cycles until the hysteresis loops become stabilized. Figures 9, 10, and 11, respectively, show the shear stress and shear
creep strain hysteresis loops (for a definition of these terms, please
see Reference34) for multiple cycles at the center of solder joints
made by 62Sn36Pb2Ag, 96.5Sn3.5Ag, and 100In solder alloys.
It can be seen that: (1) the creep shear strain is quite stabilized
after the first cycle; (2) the creep shear strain range of the 100In
(1.1%) is larger than that of the 62Sn36Pb2Ag (0.5%) and
96.5Sn3.5Ag (0.46%); and (3) the shear stress range of the
96.5Sn3.5Ag (16 MPa) is larger than that of the 62Sn36Pb2Ag
(13.2 MPa) and 100In (1.15 MPa). This is expected, since 100In
is the most soft material. Also, 62Sn36Pb2Ag is softer than
96.5Sn3.5Ag.
4000
-20
0
20
40
60
80
Temperature (C)
100
120
12
10
62Sn36Pb2Ag
8
Figure 7. Young’s modulus (E) for underfill.
6
4
2
2.3. Loading Conditions
0
-2
-4
The temperature loading imposed on the solder bumped Flip
-6
Chip on board assemblies is shown in Figure 8. It can be seen
-0.009
-0.008
-0.007
-0.006
-0.005
-0.004
-0.003
-0.002
-0.001
0
that for each cycle (60 minutes), the temperature is between –20
Shear Creep Strain
o
and +110 C, with 15 minutes ramp, 20 minutes hold at hot, and
10 minutes hold at cold. There are two reasons for choosing this
Figure 9. Hysteresis loop for 62Sn36Pb2Ag.
temperature profile: (1) the glass transition temperature of the
FR-4 PCB is 120oC, and one do not want to introduce additional
failure mechanisms of the solder joint due to the degradation of
The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)
14
© International Microelectronics And Packaging Society
Creep Behaviors of Flip Chip on Board With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints
12
12
10
10
96.5Sn3.5Ag
8
8
6
6
4
4
2
2
0
-2
0
-4
-2
-6
-4
-8
-0.008
-6
-0.007
-0.006
-0.005
-0.004
-0.003
-0.002
-0.001
Shear Creep Strain
0.000
0.001
96.5Sn3.5A g
-8
0
5000
10000
15000
20000
T im e (s)
(sec)
Figure 10. Hysteresis loop for 96.5Sn3.5Ag.
Figure 13. Shear stress history for 96.5Sn3.5Ag.
1
0.8
1
100In
0.6
0.8
0.4
0.6
0.2
0.4
0
0.2
-0.2
0
-0.4
-0.2
-0.6
-0.01
-0.4
-0.008
-0.006
-0.004
-0.002
0
0.002
0.004
100In
-0.6
Shear Creep Strain
0
5000
10000
Time (s)
(sec)
15000
20000
Figure 11. Hysteresis loop for 100In.
Figure 14. Shear stress history for 100In.
3.2. Time-Dependent Shear stress
12
9 6 .5 S n 3 .5 A g
62Sn 36P b2A g
1 0 0 In
10
The shear-stress history at the center of solder joints made by
the 62Sn36Pb2Ag, 96.5Sn3.5Ag, and 100In solder alloys is
shown in Figures 12, 13, and 14, respectively. It can be seen that,
at this location, the shear-stress history of all these solder alloys
follows the imposed thermal cycling condition. Figure 15 shows
the comparison of these three solder alloys. It can be seen that:
(1) the shear stress of 100In is much smaller than that of
62Sn36Pb2Ag and 96.5Sn3.5Ag; and (2) the shear stress of
96.5Sn3.5Ag is slight higher than that of 62Sn36Pb2Ag.
8
6
4
2
0
-2
-4
-6
-8
0
5000
10000
15000
20000
T im e (s)
(sec )
12
10
8
6
Figure 15. Shear stress history comparison.
4
2
0
3.3. Time-Dependent Shear Creep Strain
The shear-creep-strain history at the center of solder joints
made
by the 62Sn36Pb2Ag, 96.5Sn3.5Ag, and 100In solder al62Sn36Pb2Ag
-6
loys is shown in Figures 16, 17, and 18, respectively. It can be
0
5000
10000
15000
20000
seen that, at this location, just like the shear-stress history, the
Time (sec)
shear-creep-strain history of all these solder alloys follows the
imposed thermal cycling condition. Figure 19 shows the shearFigure 12. Shear stress history for 62Sn36Pb2Ag.
The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)
-2
-4
© International Microelectronics And Packaging Society
15
Intl. Journal of Microcircuits and Electronic Packaging
creep-strain history comparison of these three solder alloys. It
can be seen that: (1) the shear-creep-strain of 100In is much
larger than that of 62Sn36Pb2Ag and 96.5Sn3.5Ag; and (2) the
shear-creep-strain of 96.5Sn3.5Ag is slight smaller than that of
62Sn36Pb2Ag.
4.E-03
96.5Sn3.5Ag
62Sn36Pb2A g
2.E-03
100In
0.E+00
-2.E -03
-4.E -03
0 .0 E + 0 0
-1 .0 E -0 3
62 Sn36Pb 2A g
-6.E -03
-2 .0 E -0 3
-3 .0 E -0 3
-8.E -03
-4 .0 E -0 3
-1.E -02
-5 .0 E -0 3
0
-6 .0 E -0 3
-7 .0 E -0 3
5000
10000
Tim e (s)
(sec)
15000
20000
-8 .0 E -0 3
-9 .0 E -0 3
0
5000
10000
T im e (s)
( s e c)
15000
20000
Figure 16. Shear creep strain history for 62Sn36Pb2Ag.
1.0E -03
0.0E + 00
Figure 19. Creep shear strain history comparison.
4. Summary, Discussions, and Future
Directions
96.5S n 3.5 A g
-1.0E -0 3
Nonlinear time-history analyses of Flip Chip on board with
96.5Sn3.5Ag, 100In, and 62Sn36Pb2Ag solder joints have been
presented. The implicit creep model (TBOPT=8) of ANSYS,
Release 5.6.1 has been used for the very first time for solder applications. Some important results are summarized as follows.
-2.0E -0 3
-3.0E -0 3
-4.0E -0 3
-5.0E -0 3
-6.0E -0 3
-7.0E -0 3
-8.0E -0 3
0
5000
10000
15000
20000
T im e (s)
(sec)
Figure 17. Shear creep strain history for 96.5Sn3.5Ag.
4.0E -0 3
2.0E -0 3
0.0E +0 0
-2 .0 E -0 3
-4 .0 E -0 3
-6 .0 E -0 3
-8 .0 E -0 3
1 0 0 In
-1 .0 E -0 2
0
5000
10000
15000
T im e (s)
(sec)
Figure 18. Shear creep strain history for 100In.
20000
(1)The implicit model of ANSYS for solders obeying GarofaloArrhenius creep constitutive equation works very well and
converges very fast. It should be noted that there is an error in
the present release (The constants C2 and C3 should be interchanged), and it will be corrected in the next release of ANSYS.
(2)The creep shear strain range of 100In is larger than that of
62Sn36Pb2Ag and 96.5Sn3.5Ag. Also the creep shear strain
range of 96.5Sn3.5Ag is larger than that of 62Sn36Pb2Ag
and 100In.
(3)The shear stress history of 100In is much smaller than that of
62Sn36Pb2Ag and 96.5Sn3.5Ag, and the shear stress of
96.5Sn3.5Ag is slightly higher than that of 62Sn36Pb2Ag.
(4)The shear-creep-strain of 100In is much larger than that of
62Sn36Pb2Ag and 96.5Sn3.5Ag, and the shear-creep-strain
of 96.5Sn3.5Ag is slightly smaller than that of 62Sn36Pb2Ag.
(5)The 100In is suitable for joining brittle materials, such as
GaAs, Si, and glass, and for lower temperature applications.
On the other hand, 96.5Sn3.5Ag is for tough materials, such
as ceramics and for higher temperature applications such as
under the hood of automobile.
(6)In order to use the lead-free solders, both 100In and
96.5Sn3.5Ag, in high volume production, more works such
as wettability and compatibility with PCB finishings need to
be done.
(7)It should be pointed out in Reference30 if lead free solders
containing silver are improperly disposed and contacted
The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)
16
© International Microelectronics And Packaging Society
Creep Behaviors of Flip Chip on Board With 96.5Sn-3.5Ag and 100In Lead-Free Solder Joints
groundwater, the solders could render that groundwater unsafe to drink per the United States Environmental Protection
Agency (USEPA) standards. In that case, the lead free solders
containing silver could create hazardous environments or increase cost in waste treatments.
Acknowledgments
The authors would like to thank ANSYS (especially Dr. Metin
Ozen of MCR) for their useful help.
References
13. P. T. Vianco, K. L. Erickson, and P. L. Hopkins, “Solid State
Intermetallic Compound Growth Between Copper and High
Temperature”, Tin-Rich Solder – Part 1: Experimental Analysis, Sandia National Labs (Contract Number DE-AC0494AL85000) Report, 1994.
14. S. K. Kang and A. K. Sarkhel, “Lead (Pb) – Free Solders for
Electronic Packaging”, Journal of Electronic Materials, Vol.
23, No. 8, pp. 701-708, August 1994.
15. D. A. Shangguan, A. Achari, and W. Green, “Application of
Lead-Free Eutectic Sn-Ag Solder in No-Clean Thick Film
Electronic Modules”, IEEE Transactions on Components,
Packaging and Manufacturing Technology – Part B, Vol. 17,
No. 4, pp. 603-611, 1994.
16. W. Yang, L. E. Felton, and R. W. Messler, “The Effect of
Soldering Process Variables on the Microstructure and Mechanical Properties of Eutectic Sn-Ag/Cu Solder Joints”, Journal of Electronic Materials, Vol. 24, No. 10, pp. 1465-1472,
1995.
17. J. S. Hwang, “Modern Solder Technology for Competitive
Electronics Manufacturing”, McGraw-Hill, New York, New
York, 1996.
18. P. Vianco, J. Rejent, I. Artaki, U. Ray, D. Finley, and A.
Jackson, “Compatibility of Lead-Free Solders with Lead Containing Surface Finishes as a Reliability Issue in Electronic
Assemblies”, Proceedings of the IEEE Electronic Components
and Technology Conference, ECTC ‘96, Orlando, Florida,
pp. 1172-1183, May 1996.
19. Z. Mei and H. Holder, “A Thermal Fatigue Failure Mechanism of 58Bi-42Sn Solder Joints”, ASME Transactions, Journal of Electronic Packaging, Vol. 118, pp. 62-66, June 1996.
20. W. Ren, M. Lu, S. Liu, and D. Shangguan, “Thermal Mechanical Property Testing of New Lead-Free Solder Joints”,
Soldering and Surface Mount Technology, Vol. 9, No. 3, pp.
37-40, October 1997.
21. D. A. Shangguan, and G. Gao, “Lead-Free and No-Clean
Soldering for Automotive Electronics”, Soldering and Surface Mount Technology, Vol. 9 No. 2, pp. 5-8, July 1997.
22. NCMS, “Lead-Free Solder”, Project Final Report, NCMS
Report 040IRE96, August 1997.
23. Z. Mei, F. Hua, J. Glazer, and C. Key, “Low Temperature
Soldering”, Proceedings of IEMTS, pp. 463-476, October
1997.
24. A. Iida, Y. Kizaki, Y. Fukuda, and M. Mori, “The Development of Repairable Au-Al Solid Phase Diffusion Flip-Chip
Bonding”, Proceedings of the IEEE Electronic Components
and Technology Conference, ECTC ‘97, San Jose, California, pp. 101-107, May 1997.
25. F. Hua, Z. Mei, and J. Glazer, “Eutectic Sn-Bi as an Alternative to Pb-Free Solder”, Proceedings of Electronic Components & Technology Conference, ECTC ‘98, Seattle, Washington, pp. 277-283, May 1998.
26. A. Grusd, “Lead Free Solders in Electronics”, Proceedings
of Surface Mount International Conference, San Jose, California, pp. 648-661, August 1998.
27. P. Biocca, “Global Update on Lead-Free Solders”, Proceed-
1. J. H. Lau, “Low Cost Flip Chip Technologies for DCA, WLCSP,
and PBGA Assemblies”, McGraw-Hill, New York, New York,
2000.
2. J. H. Lau and W-S R. Lee, “Chip Scale Package: Design,
Materials, Process, Reliability, and Applications”, McGrawHill, New York, New York, 1999.
3. J. H. Lau and Y-H. Pao, “Solder Joint Reliability of BGA,
CSP, Flip Chip, and Fine Pitch SMT Assemblies”, McGrawHill, New York, New York, 1997.
4. J. H. Lau, “Flip Chip Technologies”, McGraw-Hill, New York,
New York, 1996.
5. J. H. Lau, “Ball Grid Technology”, McGraw-Hill, New York,
New York, 1995.
6. R. Darveaus and K. Banerji, “Constitutive Relations for TinBased Solder Joints”, Proceedings of the IEEE Electronic
Components and Technology Conference, ECTC’ 92, San
Diego, California, pp. 538-551, May 1992.
7. J. H. Lau, “Creep of 96.5Sn-3.5Ag Solder Interconnects”,
Soldering & Surface Mount Technology, Vol. 15, pp. 45-49,
September 1993.
8. E. I. Stromswold, “Characterization of Eutectic Tin-Silver
Solder Joints”, Ph.D. Dissertation, The University of Rochester, 1993.
9. P. T. Vianco, “Issues in the Replacement of Lead-Bearing
Solders”, Journal of Metals, Vol. 45, No. 7, pp. 36-40, July
1993.
10. M. McCormack and S. Jin, “Progress in the Design of New
Lead-Free Solders Alloys”, Journal of Metals, Vol. 45, No. 7,
pp. 14-19, July 1993.
11. L. E. Felton, C. H. Taeder, and D. B. Knorr, “The Properties
of Tin-Bismuth Alloys”, Journal of Metals, Vol. 45, No. 7,
pp. 20-25, July 1993.
12. J. Glazer, “Microstructure and Mechanical Properties of PbFree Solder Alloy for Low-Cost Electronic Assembly: A Review”, Journal of Electronic Materials, Vol. 23, No. 8, pp.
693-700, 1994.
The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)
© International Microelectronics And Packaging Society
17
Intl. Journal of Microcircuits and Electronic Packaging
ings of Surface Mount International Conference, San Jose,
California, pp. 705-709, August 1998.
28. S. Wege, G. Habenicht, and R. Bergmann, “Manufacture and
Reliability of Alternate Solder Alloys”, Proceedings of Surface Mount International Conference, San Jose, California,
pp. 699-704, August 1998.
29. B. Trumble, “Get the Lead Out”, IEEE Spectrum, pp. 55-60,
May 1998.
30. E. Smith III and L. Swanger, “Lead Free Solders – A Push in
the Wrong Directions?”, Proceedings of the IPC Technical
Conference, pp. F-10-1 – F-10-6, March 1999.
31. S. Kang, J. Horkans, P. Andricacos, R. Carruthers, J. Cotte,
M. Datta, P. Gruber, J. Harper, K. Kwietniak, C. Sambucetti,
L. Shi, G. Brouillette, and D. Danovitch, “Pb-Free Solder
Alloys for Flip Chip Applications”, Proceedings of Electronic
Components and Technology Conference, ECTC ‘99, pp. 283288, June 1999.
32. J. H. Lau and C. Chang, “TMA, DMA, DSC, and TGA of
Lead Free Solders”, Soldering & Surface Mount Technology,
Vol. 11, No. 2, pp. 17-24, 1999.
33. ANSYS User’s Manual, Release 5.6.1, 2000.
34. J. H. Lau, “Thermal Stress and Strain in Microelectronics
Packaging”, Van Nostrand Reinhold, New York, New York,
1993.
About the authors
John H. Lau received his Ph.D. Degree in Theoretical and
Applied Mechanics from the University of Illinois in 1977, a
M.A.Sc. Degree in Structural Engineering from the University
of British Columbia in 1973, a second M.S. Degree in Engineering Physics from the University of Wisconsin in 1974, and a
third M.S. Degree in Management Science from Fairleigh
Dickinson University in 1981. He also received a B.E. Degree in
Civil Engineering from National Taiwan University in 1970. He
is a principal scientist at Agilent Technologies, Inc. and his current interests cover a broad range of optoelectronic packaging
and manufacturing technology. Prior to joining Agilent, he
worked for Express Packaging Systems, Hewlett-Packard Company, Sandia National Laboratory, Bechtel Power Corporation,
and Exxon Production and Research Company. With more than
30 years of R&D and manufacturing experience in the optoelectronics, electronics, petroleum, nuclear, and defense industries,
he has given over 200 workshops, authored and co-authored over
175 peer reviewed technical publications, and is the author and
editor of 13 books: Solder Joint Reliability; Handbook of Tape
Automated Bonding; Thermal Stress and Strain in Microelectronics Packaging; The Mechanics of Solder Alloy Interconnects;
Handbook of Fine Pitch Surface Mount Technology; Chip On
Board Technologies for Multichip Modules; Ball Grid Array
Technology; Flip Chip Technologies; Solder Joint Reliability of
BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies; Elec-
tronics Packaging: Design, Materials, Process, and Reliability;
Chip Scale Package (CSP): Design, Materials, Process, Reliability, and Applications; Low Cost Flip Chip Technologies for DCA,
WLCSP, and PBGA Assemblies., and Microvia: Key to LowCost and High-Density Interconnects. The first 6 were published
by Van Nostrand Reinhold and the last 7 by McGraw-Hill.
John served as one of the Associate Editors of the IEEE Transactions on Components, Packaging, and Manufacturing Technology and ASME Transactions, Journal of Electronic Packaging. He also served as general chairman, program chairman, and
session chairman, and invited speaker of several IEEE, ASME,
ASM, MRS, IMAPS, SEMI, NEPCON, and SMI International
Conferences. He received a few awards from ASME and IEEE
for best papers and outstanding technical achievements, and is
an ASME Fellow (2000) and an IEEE Fellow (1994). He is
listed in American Men and Women of Science and Who’s Who
in America.
Dr. Pan is currently a consultant and software developer at
Optimal Corperation. He is solving large scale non-linear problems for major electronic product manufacturers using finite element techniques. He is also maintaining and upgrading commercial software tools for electronic packaging. He earned a B.S.
in Mechanical Engineering, NCKU (1974), a M.S. in Mechanical Engineering, University of Cincinnati (1978), and a Ph.D. in
Mechanical Engineering, Stanford University (1987). While at
Express Packaging Systems (EPS)/Foxconn, Dr. Pan was the
manager in charge of simulation and reliability analysis of integrated circuit packaging systems, including DCA (Direct Chip
Attachments), WLCSP(Wafer Level Chip Scale Packaging), and
PBGA(Plastic Ball Grid Array) assemblies. His research area
covers finite element simulations of thermal fatigue failure mechanism for solder balls between Flip Chips and substrates. Dr. Pan
has been involved in large-scale computer simulation of engineering problems since 1980. He has experiences in linear/nonlinear, elastic/plastic/creep, and static/dynamic problems. He is
an experienced user of finite element programs, such as ANSYS
and ABAQUS. While at Structural Integrity Associates (SIA),
Dr. Pan performed finite element computer simulation of mission and time critical engineering problems for troubleshooting
and root cause analysis, such as ASME Class I structural stress
analysis, metal fatigue evaluation, fracture mechanics analysis,
elastic-plastic analysis, drop/impact analysis, fluid-structure interaction problems, flow induced vibrations, and piping/structure vibrations.
The International Journal of Microcircuits and Electronic Packaging, Volume 24, Number 1, First Quarter, 2001 (ISSN 1063-1674)
18
© International Microelectronics And Packaging Society