S
L2 cache statistics outputs
S
IOMMU statistics outputs
TICK/INTWDOG[4:1]
MP Interrupt
Controller
S
LEON4
STAT. UNIT
Red dashed connections are statistics outputs from processors and DSU
Black dashed arrows are connection between interrupt controller and processor
SYS_RESETN
Interconnect between processor cores to DSU
Raw reset
Reset
Generator
TSTOP
Debug
Support
Unit
Synchronized
system reset
BREAK
DSU_EN
DSU_ACT
SPW_CLK
On-chip SpaceWire clock
SpW PLL
HW MUL/DIV
CPU 0
CPU 1
CPU 2
CPU 3
Register file
Register file
Register file
Register file
LEON4FT
7-stage
Integer pipeline
Statistics
Interrupt port
Trace buffer
Statistics
Debug port
Interrupt port
FP controller
FP controller
LEON4FT
7-stage
Integer pipeline
HW MUL/DIV
HW MUL/DIV
Debug port
Statistics
Trace buffer
Interrupt port
LEON4FT
7-stage
Integer pipeline
Trace buffer
Interrupt port
Debug port
Statistics
FP controller
FP controller
S
X
HW MUL/DIV
LEON4FT
7-stage
Integer pipeline
AHB/APB Debug Bridge
(APB bus controller)
Debug port
Trace buffer
S
PROC_ERRORN
I-Cache
System clock for on-chip buses
and peripherals
SYS_CLK
PLL
ITLB
SRMMU
AHB I/F
I-Cache
Pipelined
Execution
unit
X
ITLB
I-Cache
SRMMU
AHB I/F
Iteration
unit
D-Cache
DTLB
ITLB
Snoop I/F
M
D-Cache
I-Cache
SRMMU
AHB I/F
X
Arbitration logic
DTLB
Pipelined
Execution
unit
Snoop I/F
X
M
GRFPU IEEE-754 FP Unit
Generated system clock and system reset are routed through
the clock gating unit for the cores that can be gated off. Clock
and reset routing/gating is not shown in this diagram.
MEM_IFSEL
Arbitration logic
DTLB
Snoop I/F
M
Main memory interface clock
MEM_IFFREQ
D-Cache
ITLB
SRMMU
AHB I/F
Iteration
unit
PCI controller
connection
D-Cache
DTLB
Snoop I/F
X
M
M
Debug AHB bus
AHB arbiter/controller
DDR2 SDRAM
Memory
Controller
96-bit (64 data + 32 check)
DDR2-800 and PC100
SDRAM interface on
shared pins.
MUX
Shared EDAC
SDRAM
Memory
Controller
M
Memory AHB bus
AHB Arbiter/Controller
M
L2 cache statistics outputs
Level 2
Cache
Controller
with EDAC
Dashed AHB lines are snoop/trace inputs. Full lines are AHB connections
Processor AHB bus
AHB arbiter/controller
S
USB debug I/F
Connects to ULPI
compliant transceiver
S
M
X
SIE
S
AHB Trace
Buffer
S
JTAG DCL
M
JTAG debug I/F
TCK, TMS, TDI, TDO, TRST
X
AHB/AHB Bridge
Correctable error
Memory scrubber
MST #2
X
TICK/INTWDOG[4:1]
TSTOP
TSTOP
TSTOP
REG
AHB Status reg.
(AHBSTAT0)
TSTOP
TSTOP
GP Timer Unit
GP Timer Unit
GP Timer Unit
GP Timer Unit
GP Timer Unit
Timer 1
Timer 1
Timer 1
Timer 1
Timer 1
S
S
Timer 2
Timer 2
Timer 2
Timer 2
Timer 2
Timer 3
Timer 3
Timer 3
Timer 3
Timer 3
Timer 4
Timer 4
Timer 4
Timer 4
Timer 4
S
S
S
S
Clock gate
unit
AHB Status reg.
(AHBSTAT1)
S
S
MST #1
S
SLV
External signal DSU_EN controls
clock gating of all cores attached
to Debug AHB bus (marked with
green)
S
All on-chip buses run at the same frequency
determined by MEM_IFSEL and MEM_IFFREQ.
The baseline frequenecy is 400 MHz for both
on-chip buses and primary DDR2 SDRAM
memory interface,
M
DSU_EN
IOMMU statistics outputs
IOMMU
AHB/AHB Bridge
Timer 5 / WDOG
M
M
TICK[4]/EXTSTART
WDOGN
GRSPW2
RMAP target
USB DCL
S
BREAK
SpaceWire RMAP target
LVTTL RXD, RXS, TXD, TXS
S
GRFPU IEEE-754 FP Unit
Master I/O AHB bus
AHB Arbiter/Controller
M = AHB master interface
S = AHB or APB slave interface
X = AHB snoop or trace connection
X
S
AHB/APB Bridge 1
(APB bus controller)
AHB/APB Bridge 0
(APB bus controller)
PROM/IO
Memory
Controller
with EDAC
8/16-bit PROM/IO I/F
with BCH EDAC and
separate data buses
Slave I/O AHB bus
AHB Arbiter/Controller
S
S
Correctable error
S
S
S
General Purpose
I/O Port
Internally re-synchronized reset values of
GPIO lines are used as bootstrap signals.
Bootstrap connections are not shown in the
diagram. Please refer to the preliminary
datasheet for additional information on bootstrap signals.
Processor AHB bus
Processor AHB bus snoop/trace connection
Memory AHB bus
Memory AHB bus snoop connection
Debug AHB bus
Debug APB bus
M
S
S
S
Bootstrap
signals
16 GPIO lines
Master I/O AHB bus
Master I/O AHB bus trace connection
Slave I/O AHB bus
Slave I/O AHB bus snoop connection
Slave I/O APB bus 0
Slave I/O APB bus 1
UART 0
UART interface 0
S
S
UART 1
UART interface 0
SPI controller
SPI master/slave interface
Correctable error signals
Debug bus between processor and DSU
Interrupt bus between interrupt controller and processor
Signal propagating statistics to LEON4 Statistics Unit
Misc. on-chip interconnect
Off-chip signal(s)
S
PCI Arbiter
8 pairs of PCI REQ/GNT signals
Debug APB bus
connection
M
S
S
AMBA #1
S
Cfg, port
PCI Controller
M
32-bit 32/66MHz PCI interface
S
S
M
AMBA #2
S
M
AMBA #3
SpaceWire router
M
S
M
S
AMBA #4
GR1553B
Controller
SpaceWire PHYs
8 external SpaceWire ports. Connects
to external transceivers.
MIL-STD-1553B interface
M
M
M
M
HSSL
Controller
HSSL
Controller
HSSL
Controller
HSSL
Controller
SerDes
SerDes
SerDes
SerDes
High-Speed Serial Links. Physical layer TBD
MST
M
EDCL
GRETH_GBIT
10/100/1000 Mbit
Ethernet MAC
MII/GMII interface to
external transceiver.
RGMII/SGMII I/F TBD
M
S
MST
M
EDCL
GRETH_GBIT
10/100/1000 Mbit
Ethernet MAC
MII/GMII interface to
external transceiver.
RGMII/SGMII I/F TBD
Title: NGMP Detailed Block Diagram. Version Draft 1.6.0
Date: 2011-09-12 Document number: NGMP-BLOCK-0001-D160
ESA contract: 22279/09/NL/JK Deliverable: N/A
Comments: This is a draft block diagram of the NGMP architecture
defined under ESA contract 22279/09/NL/JK.
Questions/comments: [email protected]