International Conference KNOWLEDGE-BASED ORGANIZATION
Vol. XXII
No 3
2016
Δ-𝚺𝚺 MODULATORS IN FREQUENCY SYNTHSIZERS
Emil TEODORU
“Nicolae Bălcescu” Land Forces Academy, Sibiu, Romania
[email protected]
Abstract: Frequency synthesizers are indispensable systems in the wireless communications area. In
fractional-N frequency synthesizers ΔΣ modulators allows performances like larger bandwidth, faster
lock times, reduced output phase-noise, with the price of some circuitry complexity. These
specifications and others are based on the modulation accuracy. The main problem in ΔΣ fractional-N
synthesizers is the specific quantization noise of the ΔΣ modulator and the solutions try to suppress it.
MASH (Multi-stAge noise SHapping) digital ΔΣ modulator are also performance stages used in
fractional-N frequency synthesizers. This paper will present solutions for ΔΣ modulators and their
implementation.
Keywords: frequency synthesizers, 𝚺𝚺𝚫𝚫 modulator, MASH, quantization error, phasenoise.
spectral purity of the output signal and the
bandwidth persist in such structures.
The fractional-N frequency synthesis
offers solutions to these antagonistic aspects
by using a non-integer resolution of the
synthesizer (N+k/M)fref with k, M integer. In
this case the reference frequency fref can be
higher than the output step between two
adjacent frequencies.
By using the fractional solution, the
output phase noise decreases, a great fref
permits larger bandwidth and fast lock times
of the loop.
1. Introduction
In indirect integer-N frequency
synthesizers (fig.1) some limitations
concerning spectral purity at higher
resolutions are present. To achieve small
frequency steps, large value dividing factor
N are needed.
Figure 1: Basic structure of a integer-N
indirect frequency synthesizer.
fref
charge
pump
+
By consequence the reference
source noise increases to the output because
is direct proportional by the value of N.
Another problem is that the small
reference frequency fref means a small
system bandwidth, so an important
specification of the synthesizer, the great
bandwidth, is not achievable. A permanent
conflict between the good resolution, the
fout
VCO
divider
N/(N+1)

k
loop
filter
fref
carry
accumulator
Figure 2: Basic structure of a indirect
fractional-N frequency synthesizer.
DOI: 10.1515/kbo-2016-0099
© 2015. This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.
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The way to realize the fractional
modulus of the divider is the key to avoid
some unwanted spurs in the output signal of
the loop.
In the basic structure (fig.2) the
fractional value results by switching a dual
modulus divider between the two divider
factors N and N+1 in so a manner that k
times in M reference cycles the divider is
N+1 and M-k times N. The average value is
Na=(N+k/M), M is the size of the counter in
the accumulator and k is the value that is
added to this counter each reference cycle.
After M reference cycles, the carry
will set the counter modulus to N+1 for a
reference cycle.
2.1. Methods to compensate the
fractional error
The presence of this noise is the
single problem in fractional-N frequency
synthesis in addition to the reference noise.
The compensation of this noise is
necessary to make the fractional synthesis
useful. Many methods were developed [3]:
- phase compensation
- phase interpolation
- phase insertion
- Δ-Σ modulation
- DAC estimation
- random jittering.
2.2. The Δ-Σ modulator method
The basic structure of a Δ-Σ
modulation
fractional-N
frequency
synthesizer is in fig.3. The divider is
multimodulus and the random alternation
between his factors breaks the periodicity of
the fractional error. In the same time the
quantization error of the basic structure is also
reduced.
The value of the divider modulus is
determined by the sequence x[n] and finally
results as a weighted mean of the divider
integer modules by their probabilities of
apparition:
N, F = N1 P1 + N2 P2 + ⋯ + Nj Pj (2)
A 1st order Δ-Σ modulator can
combine 2 divider factors, a second order one
4 factors, a third order 8.
2. The fractional error
When
the
content
of
the
accumulator is not 0, a phase error between
the reference fref and fVCO/Na – a
quantization error - is present. This error
increases till the accumulator is full and the
overflow reduces the phase error by 2π. A
new counting cycle is initiated and the error
will increase again. The content of the
accumulator represents the actual phase
error at the end of each reference cycle [1]:
Phase err.(rad) = acc. value∙2π/M (1)
On other point of view, the sequential
change of N, the abrupt change of the phase
and the periodicity of this mechanism
generate a spurious signal located at integer
multiples of fref/M from the carrier, named
the fractional spur.
To reduce these spurs a lower
bandwidth is necessary, but this way a very
important goal of the fractional synthesis is
negated – the larger bandwidth.
The good solution is to introduce a
randomization in the selection of the divider
modulus. It is necessary to generate a
sequence that approximate a sampled
sequence of independent random variables of
1 and 0 with the probabilities (M-k)/M and
k/M for N, respectively for N+1. The noise is
no more periodic and became white. This
noise appears in the bandwidth of the
synthesizer as effect of integration by the
loop transfer function.
fref
Ch.pump+LPF
PFD
VCO
fout
÷N+y[n]
ΔΣ dig mod
x[n]
k
y[n]
Figure 3: ΔΣ fractional-N synthesizer.
The Δ-Σ modulator accomplishes an
attenuation of the noise in a specific band of
frequencies. The energy of the fractional error
is no more concentrated at multiply of fref/M
and is spread from low to high frequencies
with the quantizer law of the Δ-Σ modulator.
The characteristic of the noise results
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depending of the Δ-Σ modulator order. Such
systems are called noise shapers.
filtration of the high frequency noise.
e[n]
x[n
−
+
𝑧𝑧 −1
1 − 𝑧𝑧 −1
+
y[n]
Figure 4: linear model of the 1st order
ΔΣ modulator
Based on the linear model of an 1st
order Δ-Σ modulator (fig.4) the noise transfer
function NTF is [5]:
NTF = 1−z-1
(3)
j𝜔𝜔
j(2𝜋𝜋f f )
and with z = e =e / s it can be shown that
this is a high-pass characteristic. Much of this
noise will be filtrated by the LPF effect of the
loop.
With an oversampling ratio as [7]:
𝑓𝑓
𝑄𝑄 = 2𝑓𝑓𝑠𝑠
(4)
Figure 5: MASH 1-1 structure.
the signal-to-noise ratio SNR for a sinusoidal
input is [7]:
𝑃𝑃
𝑆𝑆𝑆𝑆𝑆𝑆𝑚𝑚𝑚𝑚𝑚𝑚 = 𝑃𝑃𝑠𝑠 =
𝑛𝑛
54∙�22𝑛𝑛 �∙(𝑂𝑂𝑂𝑂𝑂𝑂 )3
∆2 ∙𝜋𝜋 2
(5)
It results that each doubling of the
OSR produces a 8 times (9 dB) improvement
in SNR. The noise shaping become more
important for superior orders of the Δ-Σ
modulator.
Figure 6: Characteristic of the MASH 1-1.
This structure has a characteristic like
in fig. 6.
3. MASH Δ-Σ modulators
Usually Δ-Σ modulators are divided
in:
- single stage
- cascaded (MASH).
The MASH (Multi-stAge noise
SHapping) structure contains more low-order
cascaded Δ-Σ modulators. An (1-1) MASH
structure refers to two 1st order cascaded Δ-Σ
modulators. A Simulink model of a 1-1
structure is shown in fig. 5
The NTF of this structure is [7]:
𝑁𝑁𝑁𝑁𝑁𝑁(𝑧𝑧) = −(1 − 𝑧𝑧 −1 )2
(6)
The output signal is now a 4-level
signal. Only 2nd and 3rd order Δ-Σ modulators
are in practice used in fractional-N
synthesizers. 4th or higher order modulators
are difficult to implement because the limited
order of the loop filter do not allow a good
4. Conclusions
The main problems in integer-N
frequency synthesis were presented. The
permanent conflict between large bandwidth,
agile setting and poor noise in the output
signal can be solved in the fractional-N
frequency synthesis.
The basic structure of the fractional-N
synthesizer permits better results when Δ-Σ
modulators are used to produce the divide
factor.
The order of the Δ-Σ modulator is
responsible for the type of the noise
characteristic.
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References
[1] Egan, W.F., Frequency synthesis by phase lock, John Wiley & Sons, New York, 2000,
pp.376.
[2] Ian Galton, Delta-Sigma Fractional-N Phase-Locked Loops, in Phase-Locking in HighPerformance Systems: From Devices to Architectures, B. Razavi, Ed. New York: Wiley,
2003, pp.23-33.
[3] T. A. Riley, M. Copeland, T. Kwasniewski, Delta-sigma modulation in fractional-N
frequency synthesis, Source IEEE Journal of Solid-State Circuits, vol. 28, May 1999, pp.
553-559.
[4] Miller, B., Conley, R., A multiple modulator fractional divider, IEEE Transactions on
Instrumentation and Measurement, June 1991, vol.40, pp. 578-583.
[5] Johns, D.A., Martin, K., Analog Integrated Circuit Design, John Wiley, 1997.
[6] Shu,K., Sanchez-Sinencio, E., CMOS PLL Synthesizers: Analysis and Design, Springer
Science + Business Media, Inc., Boston, 2005, pp.69-101.
[7] Bertran Bakkaloglu, Sayfe Kiaei, Bikram Chaudhuri, Delta-Sigma (Δ-Σ) frequency
synthesizers for wireless applications, Computers Standard & Interfaces, volume 29,
Issue 1, January 2007, pp. 19-30.
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