DATASHEET
Photon Detection
CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
Key Features
 Extended spectral range,
200 to 1000 nm
 80 MHz pixel data rate
Line rates to 37 kHz
 Center-split, dual channel
readout
 > 2,500:1 dynamic range
 5 Volt clocking
 14 μm square pixels with
100% fill factor
 Ultra-low image lag
 Electronic exposure and
 Anti-blooming control
Based on the industry standard Reticon® arrays, Excelitas has combined the
best features of high sensitivity photodiode array detection and high-speed
charge coupled scanning to offer an uncompromising solution to the
increasing demands of advanced imaging applications.
These high performance imagers feature low noise, high sensitivity,
impressive charge storage capacity, high speed, and lag-free dynamic imaging
in a convenient dual-output architecture. The 14 μm square contiguous pixels
in these imagers reproduce images with minimum information loss and
artifact generation, while their unique photodiode structure provides
excellent blue response extending below 400nm and into the ultraviolet. The
two-phase CCD readout register requires only 5 Volts for clocking yet achieves
excellent charge transfer efficiency. Additional electrodes provide
independent control of exposure and anti-blooming. Finally, the highsensitivity readout amplifier provides a large output signal to relax noise
requirements on the camera electronics that follow.
Applications
 High-speed document reading
 Web inspection
 Mail sorting
 Production measurement
and gauging
 Position sensing
 Spectroscopy
 Optical coherence tomography
imaging
Available in standard array lengths of 2048, and 4096 elements with either
glass or UV-enhanced fused silica windows, these versatile imagers are widely
used in high speed document reading, web inspection, mail sorting,
production measurement and gauging, position sensing, spectroscopy, and
other industrial and scientific applications requiring peak imager performance.
P-series imagers combine high- performance photodiodes with high speed
CCD readout registers and a high-sensitivity readout amplifier. Refer to Figure
4 for functional details.
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CCD Line Scan Array-Rev.1.1-2015.07.10
CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
Light Detection Area
This unique design also avoids
polysilicon layers in the light detection
area that reduces the quantum
efficiency of most CCD imagers. The Pseries imagers are supplied with glass
windows for general visible use, or
fused silica windows for use in the UV
below 350 nm. On a custom basis, Pseries imagers can be supplied without
an affixed window. See Figures 1, 2 and
3 for Quantum Efficiency/Responsivity
and window transmission curves
respectively.
Figure 1 Spectral Sensitivity Curve
45
40
Responsivity [V/mJ/cm2]
The light detection area in P-series
imagers is a linear array of contiguous
pinned photodiodes on 14 μm centers.
These photodiodes are constructed
using Excelitas’ advanced photodiode
design that extends short-wavelength
sensitivity into the deep UV below 200
nm, while preserving 100% fill factor
and delivering extremely low image lag.
35
30
25
20
15
10
5
0
250
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550
650
750
850
950
1050
850
950
1050
Spectral Sensitivity Curve
100
90
80
Quantum Efficiency []%
Photodiodes covered with light shields
included at both ends of the imager
provide a dark level reference for
clamping. These are separated from the
active photodiodes by two unshielded
transition pixels that assure uniform
response out to the last active
photodiode. Due to the potential for
light leakage, the two dark pixels
nearest the transition pixels should not
be used as a dark reference.
450
Wavlength [nm]
Figure
For lowest lag, all P-series imagers
feature pinned photodiodes. Pinning,
which requires a special semiconductor
process step, provides a uniform
internal voltage reference for the
charge stored in every photodiode. This
stable reference assures that every
photodiode is fully discharged after
every scan.
350
70
60
50
40
30
20
10
0
250
350
450
550
650
750
Wavelength [nm]
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CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
100
90
Transmission []%
80
70
60
50
40
Fused Silica
30
Glass
20
10
0
250
350
450
550
650
750
850
950
1050
Wavelength [nm]
Imager Functional Diagram
Horizontal Shift Registers
Charge packets collected in the photodiodes as light is received are converted to a serialized output stream through
a buried channel, two phase CCD shift register that provides high charge transfer efficiency at shift frequencies up to
40 MHz. The Excelitas 5 Volt CCD process used in this design enables low-power, high-speed operation with
inexpensive, readily available driver devices. The transfer gate (ØTG) controls the movement of charge packets from
the photodiodes to the CCD shift register. During charge integration, the voltage controlling the ØTG is held in its low
state to isolate the photodiodes from the shift register. When transfer of charge to the shift register is desired, Ø TG is
switched to its high state to create a transfer channel between the photodiodes and the shift register.
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CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
After readout of a particular image line (n), the
shift register is empty of charge and ready to
accept new charge packets from the photodiode
representing image line n+1. To begin the transfer
sequence, the horizontal clock pulses (ØH1 and ØH2)
are stopped with ØH1 held in its high state, and ØH2
in its low state. ØTG is then switched high to start
the transfer of charge to the shift register. Once
the ØTG reaches its high state, the photo gate
voltage (ØPG) is set to high to complete the
transfer. It is recommended that the photo gate
voltage be held in the high state for at least 0.1 μs
to ensure complete transfer. After this interval, the
photo gate voltage is returned to its low state, and
when this is completed, the transfer gate is also
returned to its low state. The details of the
transfer timing are shown in Figure 5 with ranges
in Table 1.
After transfer, the charge is transported along the
shift register by the alternate action of two
horizontal phase voltages ØH1 and ØH2. While the
two-phase CCD shift register architecture allows
relaxed timing tolerances over those required in
three or four-phase, optimum charge transfer
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efficiency (CTE) and lowest power dissipation is
obtained when the overlap of the two-phase CCD
clocks occurs around the 50% transition level.
Additionally, the phase difference between
signals ØH1 and ØH2 should be maintained near
180° and the duty cycle should be set near to 50%
to prevent loss of full well charge storage
capacity and charge transfer efficiency. Readout
timing details are shown in Figure 6 with ranges
in Table 2.
Timing Requirements
In high-speed applications, fast waveform
transitions allow maximum settling time of the
output signal. However, it is generally advisable
to use the slowest rise and fall times consistent
with required video performance because fast
edges tend to introduce more transition noise
into the video waveform. When the highest
speeds are required, careful smoothing of the
waveform transitions may improve the balance
between speed and video quality.
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CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
Waveforms
Table 1 – Transfer Timing Requirements
Item
Symbol Minimum Typical Unit
Delay of ØTG falling edge
t1
5
20
ns
Delay of ØTG rising edge from end of ØH1
t2
0
10
ns
Delay of ØAB rising edge from ØPG falling edge
t3
5
5
ns
ØTG pulse width
t1
200
500
ns
ØPG pulse width
t5
180
400
ns
Rise/Fall time
t6
10
20
ns
Integration time
t7
0
ns
1
ØAB pulse width
t8
750
ns
Delay of ØH1 falling edge from ØTG falling edge
t9
25
ns
Table 2 – Readout Timing Requirements2
Item
Symbol Minimum Typical Unit
ØH1 and ØH2 clock period
t10
25
ns
ØH1 and ØH2 Rise/Fall time
t11
5
ns
ØRG Rise/Fall Time
t12
2
ns
ØRG clock – high duration
t13
2
ns
Delay of ØH1 high-to-low transition from ØRG low
t14
0
ns
1
2
750 ns is the typical time to fully drain the photodiode
The cross over point for ØH1 and ØH2 clock transitions should occur within the 10-90% level of the clock amplitude.
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CCD Line Scan Array-Rev.1.1-2015.07.10
CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
Output Amplifier
Charge emerging from the last stage of the
shift register is converted to a voltage
signal by a charge integrator and video
amplifier. The integrator, a capacitor
created by a floating diffusion, is initially
set to a DC reference voltage (VRD) by
setting the reset transistor voltage (ØRG) to
its high state. To read out the charge, ØRG
is pulsed low turning the reset transistor
off and isolating the integrator from VRD.
The next time ØH1 goes low, the charge
packet is transferred to the integrator,
where it generates a voltage proportional
to the packet size. The reset transistor
voltage, ØRG, must reach its low state prior
to the high-to-low transition of ØH1. An
apparent clipping of the video signal will
result if this condition is not satisfied.
Figure 6 details the clock waveform
requirements and overlap tolerances. The
video amplifier buffers the signal from the
integrator for output from the imager.
Care must be taken to keep the load on
this amplifier within its ability to drive
highly reactive or low impedance loads.
The half power bandwidth into an external
load of 10 pF is 150 MHz. It is
recommended that the output video
signal be buffered with a wide bandwidth
follower or other appropriate amplifier to
provide a large Zin to the output amplifier.
Keep the external amplifier close to the
output pins to minimize stray inductive
and capacitive coupling of the output
signal that can harm signal quality.
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Table 3 – Imager Performance (Typical)
Parameter
Pixel count
Pixel Size
Exposure Control
Horizontal Clocking
Number of outputs
Dynamic Range
Readout noise
Amplifier
Reset Transistor
Total noise without CDS
Saturation exposure (750 nm)
Noise equivalent exposure
Amplifier sensitivity
Saturation output voltage
Saturation charge capacity
Charge transfer efficiency
Peak responsivity (w/o window)
PRNU
Dead pixels
Lag
Spectral response range
Pixel date rate
2048 elements (HL2048P)
4096 elements (HL4096P)
14µm x 14µm
Yes
2Ø (5 V amplitude)
2
>2,500:1
20 electrons
45 electrons
50 electrons
27 nJ/cm2
8.1 pJ/cm2
6.0 µV/electron
1,100 mV
167,000 electrons
>0.99995
41 V/µJ/cm2
±5%
0
<0.1%
200 nm to 1 000nm
80 MHz
Exposure Control and Anti-blooming
An exposure control feature in the P-series imagers
supports variable charge accumulation time in the
photodiode. When the anti-blooming gate voltage
(ØAB) is set to its high state, charge is drained from the
pixel storage gate to the drain. During normal charge
collection in the photodiode, ØAB is set to its low state.
Due to the timing requirements of the exposure
control mode, charge is always accumulated at the
end of the period just before the charge is transferred
to the readout register. Figure 5 includes the timing
requirements for exposure control with the antiblooming gate. The exposure control timing shown will
act on the charge packets that emerge as video data
on the next readout cycle.
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CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
Table 4 – Operating Voltages
Signal
ØH1 ØH2
Function
High
Low
High
Low
High
Low
High
Low
Horizontal clocks
ØTG
Transfer gate
ØPG
Photo gate
ØAB
Anti-blooming gate
VOG
Output gate
ØRG
Reset fate
VDD
VRD
VSS/LS
IDD
State
High
Low
Amplifier voltage supple
Amplifier reset drain
Amplifier return/light shield
Amplifier current
Imager Performance
In P-series imagers each element performs its own
function independently while integrating smoothly
with the other elements in the array. The
photodiodes efficiently transform light to charge,
the readout registers accurately transport the
charge to the amplifier, and the amplifier delivers a
clean, robust signal for use in image processing
electronics. While the actual performance of these
imagers depends strongly on the details of the
electronics and timing the camera provides, their
straight-forward implementation requirements
facilitate optimum designs.
Voltage (V)
Typical Maximum
5
0.03
ØPG High
8
-4
0
8
8
-4
-3
3
4
8
-4
-4
2.5
3
3.5
8
84
10
0
0.3
12
125
15
4,5
9
9
12
0
20 mA
Minimum
4.75
imager from electrostatic discharge (ESD) and
excessive voltages and temperatures. Do not
violate the limits on output register speed or
reduce timing margins below the minimums.
Imager Configuration
All P-series imagers are constructed using ceramic
packages and optically- flat windows. Imager die
are secured to precision lead frames by thermal
silver-filled epoxy. Packages are baked before
sealing to eliminate moisture, and tested for seal
integrity.
Operating Conditions
Ordering Information
For optimum performance and longest life,
carefully follow the operational requirements of
these imagers. Provide stable voltage sources free
of noise and variation, and clean waveforms with
controlled edges. Protect the
The HL2048 and HL4096 P-Series imagers are
available with either glass or quartz windows. On
special orders, Excelitas can supply anti-reflective
coated windows or windowless packages. Imagers
are individually packaged in electrostatic- resistant
boxes and identified by lot number for tracking.
3
Lower than typical ØAB High voltage may result in higher PRNU due to semiconductor processing variation
Higher than typical VRD voltage setting requires higher ØRG high voltage
5
Higher than typical VDD voltage could increase amplifier gain with corresponding higher than typical V RD voltage
4
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CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
Figure 7 – Pinout Configuration
Table 7 – Package Dimensions and Tolerances
A
B
Device Inches
mm
Inches
mm
HL2048P 1.131 280728 1.500 ± 0.15 38.1 ± 0.381
HL4096P 2.259 57.379 2.690 ± 0.15 68.3 ± 0.381
Table 8 – Stock Part Numbers
Active Pixels
Window
Glass
Fused Silica
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2048
HL2048PAG-021
HL2048PAQ-021
Note
While the HL P-Series imagers have
been designed to resist electrostatic
discharge (ESD), they can be damaged
from such discharges. Always observe
proper ESD precautions when
handling and storing this imager.
4096
HL4096PAG-021
HL4096PAQ-021
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CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
Figure 8 – Drawing 2K Array and 4K Array
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CCD Line Scan Array-Rev.1.1-2015.07.10
CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
Figure 9 – Recommended 40 MHz ØH1/ØH2 and ØRG Circuits
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Page 10 of 11
CCD Line Scan Array-Rev.1.1-2015.07.10
CCD Line Scan Array
P-Series High Speed Linear Photodiode Array Imagers
RoHS Compliance
The P-Series High Speed Linear Photodiode Array Imagers are designed and built to be fully compliant with the
European Union Directive 2011/65/EU – Restriction of the use of certain Hazardous Substances (RoHS) in Electrical
and Electronic equipment.
Warranty
A standard 12-month warranty following shipment applies. Any warranty is null and void if the photodiode window
has been opened.
About Excelitas Technologies
Excelitas Technologies is a global technology leader focused on delivering innovative, customized solutions to
meet the lighting, detection and other high-performance technology needs of OEM customers.
Excelitas has a long and rich history of serving our OEM customer base with optoelectronic sensors and modules
for more than 45 years beginning with PerkinElmer, EG&G, and RCA. The constant throughout has been our
innovation and commitment to delivering the highest quality solutions to our customers worldwide.
From analytical instrumentation to clinical diagnostics, medical, industrial, safety and security, and aerospace and
defense applications, Excelitas Technologies is committed to enabling our customers' success in their specialty
end-markets. Excelitas Technologies has approximately 5,000 employees in North America, Europe and Asia,
serving customers across the world.
Excelitas Technologies
22001 Dumberry Road
Vaudreuil-Dorion, Quebec
Canada J7V 8P7
Telephone: (+1) 450 424 3300
Toll-free: (+1) 800 775 6786
Fax: (+1) 450 424 3345
[email protected]
Excelitas Technologies
GmbH & Co. KG
Wenzel-Jaksch-Str. 31
D-65199 Wiesbaden
Germany
Telephone: (+49) 611 492 430
Fax: (+49) 611 492 165
[email protected]
Excelitas Technologies Singapore, Pte. Ltd.
8 Tractor Road
Singapore 627969
Telephone: (+65) 6775 2022 (Main number)
Telephone: (+65) 6770 4366 (Customer Service)
Fax: (+65) 6778-1752
[email protected]
For a complete listing of our global offices, visit www.excelitas.com/locations
© 2015 Excelitas Technologies Corp. All rights reserved. The Excelitas logo and design are registered trademarks of Excelitas Technologies Corp. All other trademarks not owned by Excelitas Technologies or its subsidiaries that are
depicted herein are the property of their respective owners. Excelitas reserves the right to change this document at any time without notice and disclaims liability for editorial, pictorial or typographical errors.
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CCD Line Scan Array-Rev.1.1-2015.07.10