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Nanoscale Etching in Inductively Coupled Plasmas
Colin Welch, BSc, MSc
Oxford Instruments Plasma Technology
1 Introduction
Nanotechnology may be defined as the ability to precisely manipulate matter on nanoscale dimensions (usually agreed
to be within the range 1nm to 100nm). This ability is enabling extension of the performance of conventional devices
(such as the CMOS transistor), and the development of completely new devices and technology. The application of
nanotechnology has been increasing exponentially over the last few years it is no exaggeration to say that very few
areas of human technology are exempt from its potential benefits. Such areas of technology [1] include:
1) Medical (e.g. nano lab-on-chip for diagnostics, drug delivery, nano-tissue engineering)
2) Chemical (e.g. highly efficient nanocatalysts and nanofiltration)
3) Energy (e.g. nanotech in energy efficiency, and insulation, fuel cells, rechargeable batteries and photovoltaics)
4) Nanotech enhanced material for heavy industry (such as aerospace and construction).
5) Information and communication (memories, novel semiconductor and optoelectronic devices, displays and quantum
computing)
6) Consumer (e.g. food, cosmetics, household, textiles, optics)
This paper on nanoscale etching is most relevant to technology area 5 but also finds uses in other areas especially 3
and 1.
Etching is the selective removal of solid material through a mask to produce two or three dimensional structures in the
fabrication of devices. The classic example is in etching steps required for monolithic integrated circuit fabrication
(such as Complementary-Metal-Oxide Silicon (CMOS) transistor chips) with feature sizes on the micron scale and now
much less. Etching for such microelectronics evolved from wet chemistry in the 1960s and 70s (usable down to about
5µm dimensions) to dry etching with parallel plate plasma systems (Reactive Ion Etching, RIE) usable down to maybe
0.1µm in favourable cases and finally in the last 10-15 years to dry etching with high density plasma (HDP) systems,
especially inductively coupled plasma (ICP) taking us into nanoscale dimensions below 100nm. Indeed CMOS
technology has long since progressed into the nanoscale. Figure 1 taken from the International Technology Roadmap
for Semiconductors (ITRS) 2010 update indicates this occurred in about 2003 when considering half pitch polysilicon
gate widths for flash or DRAM technology [2].
Etching to form nano-objects is an example of a "top-down" approach, whereby smaller entities are constructed from
larger entities without atomic-level control. Aside from CMOS nanoelectronics other examples of the use of etching in
nanotechnology are the formation of quantum dots and nanoconstrictions [3] and in black silicon formation for
photovoltaic and photodetector devices, and advanced chargeable battery fabrication [4]
The opposite to “top down” is of course the “bottom-up” approach, whereby initially nanoscale components are
arranged into more complex arrays. An example is the growth on nanowire and nanotubes from tiny seed layers. [5].
Sometimes, top down and bottom up may be combined: in reference [6] a regular array of colloidal gold particles is
formed on a protein surface and then etching is attempted with the gold as a mask.
This article will focus on the top down technique of ICP etching and will use in particular techniques and results for
nano-imprint technology and photonic crystal fabrication, as well as illustrating the nanoscale etching capability for a
wide range of materials and devices. The results are all achieved in Oxford Instruments ICP tools, demonstrating a
strong capability in nanoscale etching.
This publication is the copyright of Oxford Instruments Plasma Technology Limited and which (unless agreed by the company in writing) may
not be used, applied or reproduced for any purpose, or form part of any order or contract or be regarded as a representation relating to the
products or services concerned.
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Nanotech
(<100nm)
Era begins
(2003)
Figure 1 From the ITRS 2010 Update, plotting product half-pitch gate length against year of production [2]
2 The ICP tool
The system used for these processes is the Oxford Instruments Plasmalab System 100 ICP etcher. A schematic of an etch
chamber is given in Figure 2 and a photograph of a full System 100 ICP180 is shown in Figure 3.
Figure 2 Schematic of the Plasmalab System100 ICP180 tool
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Figure 3 Plasmalab System 100 ICP180
RF power (13.56MHz) is applied to both the ICP source (up to 3000Watts) and substrate electrode (up to 600Watts) to
generate the etch plasma. An electrostatic shield around the ICP tube is used to ensure that the ICP power is purely
inductively coupled (i.e. ‘true-ICP’), hence eliminating sputtering of tube material and minimising unnecessary highenergy ion damage to devices. Ion energy at the substrate is monitored by measurement of the DC bias generated on
the lower electrode, and is controlled mainly by the RF power supplied to this electrode.
Wafers are loaded into the chamber via a load lock to maintain good stability of chamber vacuum and hence
repeatability of etching results.
The wafers are clamped either mechanically or electrostatically to the temperature-controlled lower electrode. Helium
pressure is applied to the back of the wafers to provide good thermal conductance between the chuck and the wafer.
Smaller samples or pieces may be attached to a carrier wafer with thermally conductive compound.
Oxford Instruments ICP systems have control of substrate temperature to accuracy of ±1°C over a temperature range of
-5°C to +400°C, through the use of electrical heater elements and a coolant circulating circuit. This can be extended to
–150ºC to +400ºC with the addition of a supply of liquid nitrogen. In general substrate temperature has a marked
effect on the etch result, as it controls the volatility of the etch species and hence influences the chemical component
of the process, affecting not only etch rate, selectivity and profile, but also surface roughness. The system can be
operated over a pressure range from 0.1mT to 100mT with close control by automatic pressure control.
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3. Difficulties and Limits of Nanoscale Etching
Etching on the nanoscale is a fundamentally difficult for two basic reasons: 1) more difficult transport of neutrals
species in and out of the smaller features and 2) increased effects of charging by ions and electrons as sidewalls get
closer together. The situation is compounded by the fact that in the design of smaller devices, usually the lateral
shrink is greater than the vertical shrink so the aspect ratio h/d rises as illustrated in Figure 4.
h
d
d
Figure 4 Design rules dictate increasing Aspect Ratio (AR) as critical dimension d shrinks for nanoscale devices
Focussing on the first basic reason, neutral etching species and etch products move isotropically by diffusion
(unaffected by the perpendicular sheath field). As AR increases, the number of collisions with the sidewalls
increases. Each collision slows the progress of etching species towards the surface to be attacked and slows the
escape of product species. Furthermore incoming species are shadowed by the top corners of the trench. See
Figure 5.
Figure 5 Multiple sidewall collisions of a gas species (with low sticking coefficient) in a HAR feature
These effects increase the difficulty of etching high AR features especially when neutral species are involved in the
rate limiting step of the etching reaction. A crucial parameter determining the progress of neutrals in and out of
a trench is the sticking coefficient. A low sticking coefficient is desirable to transfer species up and down the
etched feature without loss, but the sticking of other species on the sidewall may be necessary to prevent
isotropic etching. This is the idea of sidewall passivation and often involves a polymer with a high sticking
coefficient. Ideally the sticking coefficients of etching and passivating species would be carefully controlled. Figure
6 gives real examples where the sticking coefficients and passivation are not optimally managed.
Figure 6a Excess sticking or wrong species: too much sidewall passivation. Features closing up
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Figure 6b Insufficient passivation: bowed profile and underetching
The second basic reason for the increasing challenge of nanoscale etching is the increased effects of charging by ions
and electrons as sidewalls get closer together. Charged species experience a lateral force (charge q multiplied by the
electric field E) which is inversely proportional to the square of the distance y from the sidewalls:
qE ∝ 1/y2
The constant of proportionality is greater for conductive or polar material making up the sidewall (because charge can
move to enhance the effect). The result is that ions moving nearly vertically are deflected towards the sidewalls, and
at higher aspect ratio there are a higher percentage of ions experiencing significant deflection. See Figure 7.
Figure 7 Deflection of charged species: Ions are nearly vertical on approach but experience a lateral force
Positive ions
Almost
vertical
Electrons
Isotropic
Electrons
repelled
from small
features
Ions deflected
to sidewalls
I+
a. Electron charges build up at the mouths of features
b. Either balancing currents flow or charges builds up more.
Figure 8 Directional effects of charge
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Conversely electrons with their much greater mobility in the plasma move isotropically, both in the bulk plasma and
close to surfaces, and they tend to build up at the mouths of openings in the surface. See Figure 8a. This negative
charge repels further electrons and deflects positive ions at the top of the feature as well. If the substrate is
conductive, then balancing currents can flow to alleviate such charge build up. However, if the substrate is insulating
or electrically isolated like silicon- on-insulator (SOI) then charge build up will be worse. See Figure 8b.
Figure 9 gives examples where positive ion deflection is causing “notches” at the top or bottom of the feature, or
removing the passivation in the middle causing bowing. The additional fault of trenching at the base (deeper etching
against the sidewall) is also associated with ion deflection.
Figure 9a Notch at top of feature
Figure 9b Notch at base of feature (SOI interface)
Figure 9c Ion deflection causing bowing in the middle
Figure 9c Ion deflection also causing trenching at base
Of course, the profile faults shown in the examples of Figure 6 and 9 are seldom due to just one effect. Rather they
are a combination, and an interaction of the two effects discussed in this section.
The two fundamental difficulties of nanoscale etching described above have focussed solely on profile. As well as
greater difficulty in controlling the profile, nanoscale etching usually exhibits steadily lower rates, the deeper one
etches – another effect of slower species transport in HAR features. This is not usually an issue per se, especially in
fabrication of very high value devices but, because the mask is at the top of the feature, it is in a low AR situation and
so etches at the constant low AR rate whilst the solid in the HAR feature etches ever slower. Thus the selectivity over
the mask is reduced for nanoscale features which can create limitations. Furthermore in devices where the feature
width is variable, the smaller features will be etching less deep than the wide features. This is well known by the term
aspect ratio dependent etching (ARDE) and can be a severe problem for some devices, necessitating re-design. A
consequence of ARDE is etching depths that are non-linear with etch time. Finally, process window for nanoscale
etching is usually reduced, and of course, metrology and analysis become ever more difficult as feature sizes shrink.
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Alleviating this seemingly gloomy situation for the future of nanoscale etching is the fact that ICP technology is well
able to cope with the higher end of the nanoscale: less than 100nm and down to about 40nm is relatively easy with
current ICP technology. It is the ability of ICP to operate at low pressure yet with high density and low (controllable)
DC bias that helps greatly compared to simple RIE. Low pressure improves anisotropy by minimising scattering of
species by gas phase collisions. Producing good masking is more of a limit at present. There is a trend towards hard
masking for two reasons: these are usually very thin and so offer reduced aspect ratio compared to that which thicker
resist masks give even before etching begins and, secondly the selectivity over the hard mask is usually very good
compared to resist. Probably ICP technology will be sufficient to reach 20nm half pitch features and it will enable
cutting edge device fabrication for many years to come without huge modification. However, going below 20nm and
on to sub 10nm will be ever more challenging. An estimate of the ultimate limit of small trench etching has been
given as about 5nm. This is based on the thickness of sidewall passivation films (2 or 3 nm per side) needed to prevent
sideways etching [7].
4 Nanoscale Etching by ICP
In this section many examples of successful nanoscale etching by ICP systems from Oxford Instruments will be
presented and discussed.
4.1
Nano-imprint Lithography
Nano Imprint Lithography (NIL) is a versatile, cost effective, flexible and high throughput (parallel) method for
fabrication of down to 10nm (and shrinking) structures even over large areas (wafers) [8]. It has applications in
semiconductor memory, micro and nano fluidics, optical devices e.g. LEDs and lasers, life science, e.g. lab-on-a-chip
systems, bio-sensors, radio frequency components, renewable energy and new nanotech devices. The basic process
flow of NIL is shown in Figure 10.
Figure 10 is a simple schematic of the NIL process.
(a)
(b)
A. A stamp is fabricated by electron beam lithography (EBL) and dry etching
B. The stamp is pressed into a soft thermoplastic, thermosetting or UV-curable polymer on a substrate combined with
heating or UV radiation
C.
The polymer is cured and the stamp released from substrate
D. Residual imprint polymer under stamp protrusions removed by ‘descum’ process
E.
Imprinted pattern transferred into substrate by dry etching.
Figure 10 Schematic of the NIL process
Dry etching by RIE and especially ICP is very important in three of the basic steps of fabrication by NIL:
A. Nanoscale etching of the stamp (mould): Si, SiO2 (quartz), Ni, Cr, PDMS etc.
D. Descum of residual layer
E. Nanoscale etching of the substrate
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4.1.1
Stamp etch
Requirements for a good stamp etch are vertical or very near vertical profiles (but no negative slope at all to avoid
damaging the NIL polymer as the stamp is pulled out), Smooth sidewalls, uniform depths and critical dimensions (CD).
It is also desirable to avoid trenching.
Figure 11 shows a chromium (Cr) masked quartz stamp etched in the System 100 ICP180 chamber using a C4F8-based
plasma chemistry. 30nm features are etched to a depth of 200nm at a rate of 85nm/min ±<1% across a 2inch wafer.
The selectivity over Cr was >170: 1. The profile is 89-90°, smooth and trench-free at the base.
Figure 11 High quality nanoscale quartz etching for NIL stamp
The quartz profile was optimised by means of the set electrode temperature as shown in Figure 12, while trenching
was eliminated by using low enough DC bias – see Figure 13.
Trenching in Silica vs DC bias
Trench% of silica depth
Silica Sidewall Angle vs Temperature
Profile [degrees]
94
92
90
88
86
84
25
35
45
55
65
12
10
8
6
4
2
0
0
50
100
150 200 250
Temperature [°C]
DC bias [-V]
Figure 12 Simple profile control by temperature
Figure 13 Trench control by DC bias reduction
Cr is often used as a hard mask for the quartz stamp etch. Figure 14 shows a nanoscale Cr etch with features down to
70nm.
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HSQ mask
15nm Cr layer on quartz
Process gases
Cr etch rate
Uniformity
Profile
Delta CD
CD control
Selectivity
Cl2, O2 (+He)
>15 nm/min.
<±4% (200mm wafer)
>85°
<0.05µm
<±1%
>0.5:1 Cr: resist
Figure 14 Nanoscale (70nm) Cr mask etch before quartz etch (picture courtesy of AMO GmbH)
4.1.2
Descum NIL residual
The second area requiring an etch process is the Descum of the NIL residual. Some “scum” is inevitable after the stamp
presses into the NIL polymer and releases. Low scum is preferable of course (a ratio of HR/Hl 0.1 is considered very good
e.g. 20nm of scum for a 200nm polymer film. See Figure 15).
HR
NIL
polymer
HL
Substrate
Figure 15 Residual NIL polymer after stamping step
Requirements for a good descum are to remove the scum whilst minimising changes in profile and CD. It is inherently
challenging as there is no ‘mask’ to protect the top of the pattern. Although most processes are O2-based, new plasma
chemistries will be needed as more NIL polymers are developed.
ICP provides the best performance for descum: low pressure processing minimises isotropic etching and loss of profile
and CD control. Low temperature processing also helps – down to -50° C or less (available in Oxford Instruments ICP
systems). Low bias processing by ICP also minimises faceting at the top of the lines. Figure 16 is an example of a
descum process of BCB polymer leaving 10nm intact using an O2-SF6 ICP process.
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10nm
50nm
20nm
40nm
30nm
Figure 16 Nanoscale BCB lines descummed by ICP
4.1.3
NIL Nanoscale Etching
Having prepared the imprinted polymer it is very often used as an etch mask (although it may also be used as a lift-off
mask or even as the final device e.g. polymer based microfluidics or optical devices). The requirements to the final
substrate etch depend on the application and so are much more diverse than the stamp etch and descum. This is
general nanoscale etching and example will be given in section 4.3.
4.2
Photonic Crystal Hole Etching
A photonic crystal is a periodic arrangement of holes in 1-d, 2-d or 3-d that creates a photonic band gap structure- see
for example Figure 17. In a photonic crystal ‘forbidden’ wavelengths for light propagation arise much like forbidden
electron energies within a semiconductor crystal. However the hole size must be comparable with the light
wavelength λ. The photonic crystal effect was first demonstrated in 1987 for microwaves propagated in 1mm
diameter holes [9]. For visible/infra-red light at communications frequencies holes must be much smaller: submicron
holes only feasible in recent years, and into ultra-violet the holes would become nanoscale. Altering local hole
periodicity leads to a range of high performance devices (passive low loss filters, efficient microcavities, narrow line
width laser structures). There is a huge range of structures; and this is an exciting research area worldwide [10, 11]
Figure 17 A photonic crystal device: in-plane resonant cavity with 6-hole mirrors and its transmission plot (dashed line = simulation)
The requirements of photonic crystal hole etching are generally to achieve smooth vertical walls and sometimes high
aspect ratio. It is noteworthy that the etching of nanoscale holes is more challenging than trenches because the
feature is confined in 2 dimensions instead of 1 and the difficulties discussed in Section 3 are compounded (the effects
of sidewall collisions leading to sticking (deposition) or etching of the sidewall are greater, and the effects of charging
of the sidewall greater). Some examples of two dimensional photonic crystal hole etches follow in Figures 18 to 21.
These processes of course may be used for other nanotechnology applications such as those requiring ‘nanopores’ [4]
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Figure 18 Photonic crystal holes etched in InP using OI System 100 ICP180.
Reproduced with kind permission of P Strasser, et al. ETH Zurich)
The best process used a (polymer free) Cl2/N2/Ar chemistry. Cl2 is the etch gas, N2
provides sidewall passivation and Ar is used as a diluent. The OI wide
temperature electrode is utilised with a set temperature above 200°C (sample
pieces are glued to a carrier plate and backside helium cooling is used)
An etched depth of 2.9µm for 180nm diameter hole size was achieved: an
aspect ratio of 16:1. The etch rate was 1.75µm/min
Figure
19
High
aspect
ratio
in Silicon by Cryogenic ICP etching
Photonic
Crystal
holes
The OI wide temperature electrode is utilised with a set
temperature below -100°C.
180nm diameter holes are etched to 1.65µm depth using SF6-O2
chemistry in the System 100 ICP180
Mask
ZEP520E
Depth
300nm
Etch rate
220nm/min
Selectivity
>1.5:1
Profile
>88°
ARDE
no lag between 100
and 500nm holes
Figure 20 Photonic crystal holes etched in SiO2 by ICP with C4F8-He chemistry
Mask
ZEP520E
Depth
300nm
Width
200nm
Etch rate
80nm/min
Selectivity
>0.5:1
Profile
>80°
Figure 20 Photonic crystal holes etched in Ta2O5 by ICP with C4F8-O2 chemistry
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4.3
Selection of other nanoscale ICP etching processes
In Figure 21 to 23, examples are given of three ICP silicon etch processes with complementary attributes for nanoscale
etching [12]. The first is a room temperature process using a C4F8-SF6 gas mixture (Figure 21). The second is the
cryogenic process using a SF6-O2 gas mixture (Figure 22). The third process is an HBr-O2 process that can offer very high
selectivity over SiO2 achievable by controlled O2 substitution (Figure 23). This is a notch free process for shallow SOI,
fine gates, waveguides. Control of silicon etched profiles by means of the ICP process parameters is shown.
Profile [degree]
95
93
91
89
87
85
60
65
70
75
C4F8 % in SF6
Figure 21 16nm Si lines etched by C4F8-SF6 ICP process ((Courtesy of AMO, Aachen) Profile control by C4F8% (right)
94
P ro file [d egree]
92
90
88
86
84
-105
-110
-115
-120
Temperature [°C]
Figure 22 1µm deep Si lines with 10:1 aspect ratio etched by ICP cryo process. Profile control by temperature (right)
P rofile [degrees]
HBr-SOI Profile vs Temperature
92
91
90
89
88
87
86
85
84
83
82
0 10 20 30 40 50 60 70
Temperature [degC]
Figure 23 34nm polySi gate etch, HSQ masked, stopping on 3nm SiO2 (Courtesy of AMO). Profile control by temperature (right)
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850nm deep x 100nm wide lines in thermal SiO2
Very smooth sidewalls and no trenching
Ni masked C4F8-He ICP380
Figure 24 Nanoscale SiO2 etching in the System 100 ICP380
Calixarene-type e-beam
resist: TEBN-1.
Down to 30nm lines and
10nm gaps with
Redeposition-free
Pt features
Sub-10nm gaps
in Pt resolved
Figure 25 Nanoscale ICP etching of Pt on silicon
Figure 26 gives 3 examples of nanoscale tungsten etching [13, 14] performed in OIPT ICP systems.
Figure 26a Nanoscale W etching
Nanoscale (50nm lines) ICP etching of W
on HfO2. HSQ masking
Figure 26b Nanoscale W etching. See also [11]
Nanoscale ICP etching of W on silicon.
SF6-O2 plasma. -40°C electrode.
30nm half pitch, 3:1 AR
W etch rate 60nm/min. Selectivity over Cr mask >20:1
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Figure 26c High aspect ratio anisotropic nanoscale W etching.
SF6 process chemistry utilising the low temperature capability of the System 100 ICP65. 20nm evaporated Cr mask.
W etch rate 100nm/min. FIB-made cross-section of tungsten gratings. 40 and 35 nm half-pitch, 300 nm high, i.e. AR 8.5
Courtesy of Anders Holmberg, Biomedical and X-Ray Physics, Royal Institute of Technology, Stockholm, Sweden
O2 process chemistry (at -100°C) utilising the low
temperature capability of the System 100 ICP65 for
high aspect ratio anisotropic nanoscale polyimide
etching
50-nm half-pitch polyimide-gratings, 500 nm high
(AR 10:1).10nm evaporated titanium hard mask.
Polyimide etch rate 100nm/min
Courtesy of Anders Holmberg, Biomedical and XRay Physics, Royal Institute of Technology,
Stockholm, Sweden
Figure 27 Nanoscale ICP etching of polyimide on silicon
Cl2 process chemistry used in the System 100 ICP65
(RIE mode) for high aspect ratio anisotropic
nanoscale Ge etching
10nm evaporated titanium hard mask.
Ge etch rate 100nm/min.
25-nm half-pitch Ge-grating, 310nm deep (AR 12:1).
Courtesy of Anders Holmberg, Biomedical and XRay Physics, Royal Institute of Technology,
Stockholm, Sweden. See also [15]
Figure 29 High aspect ratio anisotropic nanoscale germanium etching
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5. Summary
A review of ICP etching for nanotechnology has been given. The increasing difficulty of nanoscale etching has been
explained and it has been stated that current ICP technology is good for several years more to below 20nm half pitch.
To get smaller and to what may be the ultimate limit for etching of around 5nm will require advances in the
technology to achieve better control of neutrals and charged species. New hardware developments may involve
controllable frequency and pulsed plasmas, better substrate temperature control and advanced software control – for
instance feedback loops using optical emission spectroscopy and other diagnostic techniques, parameter ramping.
Many examples of high quality nanoscale etches by Oxford Instruments ICP systems have been given and we are
continually adding to our ‘portfolio’ of materials etched and applications in the increasingly important area of
nanotechnology.
References
[1] See: http://en.wikipedia.org/wiki/List_of_nanotechnology_applications
[2] See: http://www.itrs.net/reports.html
[3] M. Sutikno, U. Hashim, Z. Azhar and Z. Jamal. “A systematic dry etching process for profile control of quantum dots and
nanoconstrictions”, Microelectronics Journal, Vol.38, Issues 8-9, Aug-Sept.2007, pp823-827
[4]See: http://www.eurekalert.org/pub_releases/2010-10/ru-ss101310.php
[5] Beri Mbenkum, Andreas Schneider, Gisela Schütz, Cigang Xu, Gunther Richter, Peter van Aken, Günter Majer and Joachim Spatz.
“Low-Temperature Growth of Silicon Nanotubes and Nanowires on Amorphous Substrates”, ACS Nano, 4 (4), (2010), pp1805–1812
[6] S. Mark, M. Bergkvist, P. Bhatnagar, C. Welch, A. Goodyear, X. Yang, E. Angert and C. Batt. “Thin film processing using S-layer
proteins: Biotemplated assembly of colloidal gold etch masks for fabrication of silicon nanopillar arrays”. Colloids and Surfaces B:
Biointerfaces. 57, (2007), pp161-173
[7] Ying Zhang, “Plasma Etching of Nanometer Scale Features”. Invited talk at Micro-and Nano Engineering, Ghent, Sept 2009. See
also www.electrochem.org/meetings/scheduler/abstracts/215/0768.pdf
[8] H.Schift, “NIL Nanoimprint lithography: An old story in modern times? A review”, J. Vac. Sci. Technol. B 26, 458 (2008);
doi:10.1116/1.2890972 (23 pages)
[9] E.Yablonovitch, “Inhibited spontaneous emission in solid-state physics and electronics”’, Phys.Rev.Lett., 58 (1987), 2059
[10]
Wei
Jiang,
“Photonic
Crystal:
Physics,
Devices,
http://asdn.net/ngc2007/raw_abstracts/attached_abstracts/060930152021/abstract.pdf
and
Applications”.
See:
[11] Peng Yinsheng et al, “Optimization of inductively coupled plasma etching for low nanometre scale air-hole arrays in twodimensional GaAs-based photonic crystals”. J. Semicond., (2010), 31, p012003,
doi: 10.1088/16744926/31/1/012003
[12] C. Welch, A. Goodyear, T.Wahlbrink, M.Lemme and T. Mollenhauer. “Silicon Etch Process Options for Micro- and Nanotechnology
using Inductively Coupled Plasmas”, Microelectronic Engineering Volume 83, Issues 4-9, April-September 2006, pp1170-1173.
[13] A.Goodyear, D. Olynick, S.Mackenzie and E.Anderson. “High resolution ICP etching of 30nm lines and spaces in Tungsten and
Silicon”, JVST B 18 (6), Nov/Dec 2000, pp3471-3475
[14] S.Gilmartin, K.Arshak, D.Bain, W.Lane, B.McCarthy, D.Collins, S.Newcomb and A. Arshak. “Development of a tungsten plasma
etch process for IR nanobolometer fabrication”, Microelectronic Engineering Volume 87, Issues 5-8, May-August 2010, pp1634-1639.
[15] M.Lindblom, J.Reinspach, O.von Hofsten, M.Bertilson, H.Hertz and A.Holmberg, “High-aspect-ratio germanium zone plates
fabricated by reactive ion etching in chlorine”, J. Vac. Sci. Technol. B 27, (2009), L1-L3
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