Reliability of Wafer Level Chip Scale Package (WLCSP) with 96.5Sn-3.5Ag
Lead-Free Solder Joints on Build-up Microvia Printed Circuit Board
John H. Lau
Agilent Technologies
350 W. Trimble Road
San Jose, CA 95 131
S-W. Ricky Lee
Department of Mechanical Engineering
Hong Kong University Science & Technology
Clear Water Bay, Kowloon, Hong Kong
Abstract
In this study, time-temperature-dependent nonlinear
analyses of lead-free solder bumped wafer level chip scale
package (WLCSP) on microvia build-up printed circuit
board (PCB) assemblies subjected to thermal cycling
conditions are presented. The lead-free solder considered
is 96.5wt%Sn-3.5wt%Ag. The 62wt%Sn-36wt%Pb2wt%Ag solder is also considered to establish a baseline.
These two solder alloys are assumed to obey the GarofaloArrhenius steady-state creep constitutive law. The shear
stress and shear creep strain hysteresis loops, shear stress
history, shear creep strain history, and creep strain density
range at the corner solder joint are presented for a better
understanding of the thermal-mechanical behaviors of the
lead-free solder bumped WLCSP on microvia build-up
PCB assemblies.
Introduction
Low-cost tin-lead solders have been used as joining
materials in the electronics industry for many years. The
unique physical and mechanical properties of the low-cost
tin-lead solders have facilitated printed circuit board
(PCB) assembly choices that have fueled creative
advanced packaging developments, such as solder bumped
flip chips [ 1-61, ball grid array (BGA) packages [ 1-61, and
chip scale packages (CSP) [l-41. For these packaging
technologies, the tin-lead solders are the electrical and
mechanical “glue” of the PCB assemblies.
Since 1992, different bills have been introduced at the
U.S. Congress to ban lead from a wide variety of
applications, which include solders. The reasons are,
among others, (a) lead and its compounds are ranked as
one of the top 10 hazardous materials and (b) lead is the
number one environmental threat to children. Many major
electronics companies, national laboratories, universities,
research organizations, and solder vendors worldwide
responded by initialing research programs to eliminate
lead from solders [7-451.
In North America, for example, the world’s first lead
free PCB telephone produced by NORTEL Networks in
1997 [30]. They used the eutectic 99.3Sn-0.7Cu to replace
Sn-Pb solder for both surface mount and through-hole
components. In European, the European Union proposed
0-7803-6654-9/00/$10.00 0 2000
IEEE
to ban all lead in electronic products by the year 2004.
Recently, they would like to postpone it to 2008.
In Japan, some electronic manufacturers have
announced voluntary plans to reduce their use of lead in
solders. For examples, Hitachi reduced their use of lead in
1999 by half of that used in 1997 and want to stop using
lead solders by 2001. (Sn-Bi-Ag type alloys are some of
Hitachi’s favorites). NEC intends to reduce lead use in
solders by 50% by 2002 compared to the usage in 1997.
(Sn-Ag, Sn-Zn, and Sn-Ag-Cu alloys are some of NEC’s
choices). NTT intend to only purchase equipment safe for
the environment (i.e., no lead or cadmium) by 2001.
SONY reduced the usage of lead solders in 1999 by half of
that used in 1996 and want to stop using lead solders
(except high-density packaging) by 2001. (SONY
developed, for example, the Sn-2Ag-4Bi-O.SCu-O.lGe for
their own products). Toshiba intend to remove lead from
all mobile phones by 2002. Fujitsu plan to stop using lead
for their LSI products by October 2000, for half of their
PCB used in their products by December 2001, and for all
their products by December 2002. (Fujitsu explored, for
example, Sn-Bi-Ag alloys). Matsushita aim to stop using
lead solders by 2001. (Matsushita pick, for example, SnAg-Bi-x alloys).
It is interesting to point out that “green” products sell!
For example, Matsushita’s market share of its lead-free
MiniDisc player jumped from 4.6 to 15 percent in 6
months (1999) in Japan. Toshiba’s bromine-free PCBs
help them to sale their Libretto and Dynabook notebook
computers in Europe and earned them some romantic
names such as Blue Angel (in Germany), White Swan (in
Finland), and TCOGY (in Sweden).
With the pressure of “green” products, one of the
challenges is to find an alternative solder alloy that is as
cost effective, manufacturable, available, and reliable as
the industry standard eutectic tin-lead or high-lead solders.
Unfortunately, there are no drop-in replacements [23] yet.
In this study, the 96.5wt%Sn-3.5wt%Ag lead-free
solder is considered. The melting point for 96.5Sn-3.5Ag
is 221’C. The 62Sn-36Pb-2Ag solder alloy is also
considered to establish a baseline. From cost point of
view, 96.5Sn-3.5Ag is more expensive than 62Sn-36Pb2Ag.
55
2000 Int’l Symp on Electronic Materials & Packaging
...........
T ...........
...........
.....
9 mm
1
0 0.3 mm
0.75 mm
(a) Dimensions of a WLCSP
(b) Cross-section of a Solder Bump with Redistribution
Figure 1: Schematic Diagrams for a Wafer Level Chip Scale Package (WLCSP)
0.008 mm
4.,oS0yf
c,ic,
Si
Solder
c l , f c l +' Joints
Micro-vias
FR-4
f
.
0.15 mm
1.575 mm
(1.0
(0.5 mm)
0.3048mm
Figure 2: Schematic Diagram of a WLCSP Build-up PCB Assembly
Figure 3: Dimensions of Solder Joint
.............
J
1 c-01
I Edlt
1.E'tl.l
I EQI
Stieor Stress (prit
Figure 5 : Creep Constitutive Relation of Solder
w
Unit : mm
-411
0. I
11
201l11
4111111
61l01l
11111111
1(KIIIII
12IIIHl
14l11111 1601HI lIIII(Hl
2WWl
Time (sec)
Figure 4: 2-D Finite Element Mesh for WLCSP Assembly
Figure 6: Temperature Profile of Thermal Cycling
56
2000 Int'l Symp on Electronic Materials & Packaging
One of the most cost-effective packaging technologies
Table 1: Fitted equations from shear creep test results
is direct chip attach (DCA) [l]. However, because of,
amount others, the high-cost of the corresponding fine line
dt
and spacing microvia build-up PCB [46] and the
I
I
troublesome of the underfill operation [47], most in the I
Solder Alloys
n
Q (eV)
A (llsec)
B (psi)
industry are still working on these issues. In the meantime,
62Sn-2Ag-36Pb 3.3 0.548
801(508-T)IT
3163-6.237
a class of new technology called wafer level chip scale
package (WLCSP) has surfaced. The unique feature of
5.5 0.5
31(553-T)IT
3687-6.67T
most WLCSPs is the use of a metal layer to redistribute 96.5Sn-3.5Ag
the very fine-pitch peripheral-arrayed pads on the chip
5
0.72
70400(593-T)m 158-0.27T
lOOIn
(Figure 1) to much larger-pitch area-arrayed pads with
Note:
T
is
absolute
temperature
in OK.
much larger solder joints on the PCB [l, 2, 45, 48, 491.
With WLCSPs, the demands on the PCB are relaxed and
the underfill may not be necessary. Also, with WLCSP, Material Properties
Figure 4 shows a typical finite element model for
the electrical performance could be enhanced by: (1)
distributing most of the power and ground toward the creep analysis of the lead-free solder bumped WLCSP on
center of the die in an area-array format to minimize microvia build-up PCB assemblies. Due to symmetry, only
voltage drop, and (2) adding more power and ground one-half of the structure is modeled and it is a 2-D
solder bumps surround the sensitive U 0 signal solder analysis. Since the focus is on the corner solder joint and
bumps to minimize the simultaneous switching noise and the microvia, finer meshes are used to model them. The
finite element code used in this study is ANSYS, release
the ground bounce.
For solder bumped flip chip on low-cost substrate 5.6.1 [50]. It can solve boundary-value problems with
applications, even with the wafer-level pad re-distribution Garofalo-Arrhenius steady-state creep constitutive
(from peripheral-array to area-array) to relax the pressure equation expressed by [6]:
on PCB, however, in most of the cases, one to two, or
even three to four build-up layers with microvias are
needed to fan-out the circuitry [46]. In this study, the
effects of microvia build-up circuits on the 96.6Sn-3.5Ag
where y is the steady-state creep shear strain, dy/dt is the
solder joint reliability of the WLCSP are presented.
steady-state creep shear strain rate, t is the time, C is a
Since there is no underfill for most of the WLCSP
material constant, G is the temperature-dependent shear
assemblies and the thermal expansion mismatch between
modulus, 0 is the absolute temperature ( O K ) , o defines the
the silicon chip and the FR-4 epoxy glass PCB is very
large, thus solder joint reliability of the WLCSP stress level at which the power law stress dependence
assemblies becomes a critical issue [48, 491. In this study, breaks down, z is the shear stress, n is the stress exponent,
the focus is on the solder joint reliability with the lead-free Q is the activation energy for a specific diffusion
solder alloy in the WLCSP on the microvia build-up PCB mechanism (for example, dislocation diffusion, solute
assemblies. Only thermal cycling loadings are considered. diffusion, lattice self-diffusion, and grain boundary
Emphasis is placed on the creep behaviors of the lead-free diffusion), and k is the Boltzmann's constant (8.617 x lo5
solder joints in the WLCSP on the microvia build-up PCB eVPK). For 62Sn-2Ag-36Pb, 96.5Sn-3.SAg, and lOOIn
assemblies and is not on the life prediction of these solder solder alloys, the material constants of Eq. (1) have been
experimentally determined by Darveaux and Banerji [6,7]
joints.
'
with a single hyperbolic sine function given by [6, 71
9
dt = A[ sinh( i)r
exp( - E)
WLCSP on PCB Assembly
The Structures
Figure 1 schematically shows the silicon chip under
consideration. The dimensions of the chip are: 9 x 9 x 0.5 1
mm. It has 121 peripheral pads (0.06 x 0.06 mm) with a
spacing of 0.1 mm. After wafer-level redistribution [ l , 21,
the pads (0.3 mm in diameter) are in an area-arrayed
format with 0.75 mm pitch.
Figure 2 shows the microvia build-up PCB assembly
of the lead-free solder bumped WLCSP. It can be seen that
the PCB is 1.575 mm thick and is made of FR-4 Epoxy
glass. The copper pad thickness is 0.018 mm as shown in
Figure 3. The diameters of the microvia are varying from
0.1 mm to 0.15 mm (Figure 4). The thickness of the
electroplated copper microvia is 0.025 mm. The thickness
of the build-up resin is about 0.125 mm. The solder joint
height is 0.1524 mm and is made of lead-free (96.6Sn3.5Ag) or eutectic (62Sn-2Ag -36Pb) solder alloys.
Table 1 shows the values of constant n, Q, A , and B.
Equations (2) for these three solder alloys at 27°C and
100°C are plotted in Figure 5. It can be seen that: (1) for
all the solder alloys and for all the temperatures, the higher
the stress the higher the steady state creep strain rate; (2)
for all the solder alloys and for all the shear stress, the
higher the temperature the higher the steady state creep
strain rate; (3) for all temperatures and for all the shear
stress levels, the steady state creep strain rate of the lOOIn
is much larger than that of the 62Sn-2Ag-36Pb and
96.6Sn-3.5Ag; (4) for all stress levels, the steady state
creep strain rate of the lOOIn is much larger than that of
the 62Sn-2Ag-36Pb and 96.6Sn-3.5Ag; and (5) for all
operating temperatures and for most operating stresses, the
steady state creep strain rate of 62Sn-2Ag-36Pb
57
2000 Int'l Symp on Electronic Materials & Packaging
Table 2: ANSYS input for implicit creep analysis
microvia build-up PCB assembly at the instants of 588,
4188, 7788, 11388, and 14988 seconds (Figure 6,
temperature 110°C). Also, the maximum deflections
(square root of the sum of square of the displacement
components in the x-direction and y-direction) at these
instants are shown in the second column of Table 4. It can
be seen and expected that, due to the thermal expansion
mismatch among the silicon (2.8 ppm/"C) chip, the buildup resin (50 ppm/"C), and the FR-4 epoxy glass (18
p p d C ) PCB, the solder joints are subjected to very large
shear deformation (especially the corner solder joint).
It is interesting to note that at 588 seconds, the
maximum displacement of the assembly is 0.019 mm. This
value is 46% smaller than that (the fourth column of Table
4) [45] of the same 96.5Sn-3.5Ag solder bumped WLCSP
PCB assembly without the build-up layer. This is because:
(1) the global thermal expansion mismatch between the
silicon chip and the build-up PCB forces the whole
assembly to deform into a concave shape; (2) the local
thermal expansion mismatch between the build-up resin
and the FR-4 PCB forces the build-up PCB to deform into
a convex shape (opposite to the global deformation); and
(3) the local thermal expansion mismatch between the
silicon chip and the build-up resin which introduces
considerable amount of shear creep deformation in the
solder joints.
At 4188,7788, 11388, and 14988 seconds, the global
deformation of the assembly becomes less concave and the
local deformation of the build-up PCB becomes more
convex. These deformed shapes are very different from
those of the WLCSP on the conventional PCB assembly,
which always deform in the concave shapes. This is
because of less bonding between the chip and the build-up
PCB and more creep strains in the solder joints.
The deformed shapes of the 62Sn-2Ag-36Pb solder
bumped WLCSP on the same build-up microvia PCB have
been obtained in [49] and the corresponding maximum
displacements are shown in the third column of Table 4. It
can be seen that there is not much difference between the
assemblies with 96.5Sn-3 SAg and 62Sn-2Ag-36Pb.
de
-
-= C,[sinh(C,a)P exp
dt
Solder Alloys
C, (llsec)
62Sn36Pb2Ag
96.5Sn3.5Ag
l0Oh
CZ(Ilpsi)
C3
C4(0K)
462(508-T)/T
ll(5478-10.79T)
3.3
6360
18(553-T)/T
ll(6386-11.55T)
5.5
5802
40647(593-T)/T
ll(274-0.47T)
5
8356
Note: T is absolute temperature in OK.
(For ANSYS Release 5.6.1 inputs, C2 and C3 should be
inter-changed.)
is larger than that of 96.5Sn-3.5Ag, especially for higher
temperatures and lower stresses. If the solder obeys the
von Mises criterion [ 11, then Eq. (2) can be written as
dE
dt = Cl [~inh(C~a)]'~
exp( (3)
F)
where C1, Cz, C3, and C4 are given in Table 2 for the three
solder alloys under consideration. It should be noted that
Eq. (3) is exactly the same form of input for implicit creep
model (TBOPT = 8) of ANSYS, Release 5.6.1 [50].In
Eqs. (2) and (3), Q is the uniaxial stress, dddt is the
uniaxial steady-state creep strain rate. The unit for Q and z
is in lb/in2(psi). The material properties of the silicon chip,
FR-4 PCB, and copper are shown in Table 3.
Boundary Conditions
The temperature loading imposed on the solder
bumped WLCSP on microvia build-up PCB assemblies is
shown in Figure 6. It can be seen that for each cycle (60
minutes) the temperature is between -20 and +1 10°C, with
15 minutes ramp, 20 minutes hold at hot, and 10 minutes
hold at cold. There are two reasons for choosing this
temperature profile: (1) the glass transition temperature of
the FR-4 PCB is 120°C and we don't want to introduce
additional failure mechanisms of the solder joint due to the
degradation of the PCB; (2) the behavior of solder below 20°C is not well understood. Five full cycles are executed.
Table 4: Comparison of Maximum Displacement (mm)
Table 3: Material properties of flip chip assemblies
Responses in the Microvias
The von Mises stress contours in the microvia of the
WLCSP assembly at 588 seconds (110°C of the first
thermal cycle) and at 14988 seconds (110°C of the fifth
thermal cycle) are shown in Figures 8a and 8b,
respectively. It can be seen that the stresses in the microvia
donot change much from thermal cycle to cycle. Also, it
should be noted that the maximum von Mises stress (108
MPa) in the microvia is less than the ultimate strength
(-200 m a ) of the electroplated copper.
Note: T is temperature ("C). The electroplated copper
is assumed to be elastic-plastic
Deformed Shapes of the WLCSP Assembly
Figures 7a through 7e show the deformed shapes
(5OX) of the 96.5Sn-3.5Ag solder bumped wLcsp On
58
2000 Int'l Symp on Electronic Materials & Packaging
A = 62.0380
D = 79.0590
(a) Time = 588 sec.
(a) Time = 588 sec.
(b) Time = 4188 sec.
(b) Time = 14988 sec.
Figure 8: von Mises Stress Contours in Microvia
A = 0.002597
B = 0.003698
C = 0.004799
D = 0.005900
E = 0.007001
(c) Time = 7788 sec.
(a) Time = 588 sec.
(d) Time = 11388 sec.
I
1
A = 0.002612
B = 0.003741
C = 0.004871
D = 0.006001
E = 0.007131
(e) Time = 14988 sec.
(b) Time = 14988 sec.
Figure 7: Deformation of WLCSP-PCB Assembly
with Build-up Layer and Microvias (all at 110°C)
Figure 9: Effective Plastic Strain Contours in Microvia
59
2000 Int’l Symp on Electronic Materials & Packaging
Item
Shear Stress
Range (MPa)
Creep Shear
Strain Range
Creep Strain
Energy Density
Range (MPa)
.
96.5Sn-3.5Ag
on p-via
Build-up PCB
62Sn-ZAg-36Pb
on p-via
Build-up PCB
96.5.911-3.5Ag
on Conventional
PCB
35'400
33.37
28.00
0.016
0.015
0.010
0.36
0.32
0.26
Responses in the Corner Solder Joint
Hysteresis Loops
Figure 10 shows the shear stress and shear creep
strain hysteresis loops for multiple cycles at the center of
the corner solder joint made of the 96.5Sn-3.5Ag solder. It
can be seen that the hysteresis loops converge after the
third thermal cycle. The loop size of the present case is
larger than that [45] of the case without build-up layer.
This is because the thermal expansion mismatch among
the chip, the build-up resin, and the PCB is larger than that
between the chip and the PCB.
Time-Dependent Shear Stress
The shear-stress history at the center of the corner
96.5Sn-3.5Ag solder joint on the microvia build-up-PCB is
shown in Figure 11. It can be seen that the shear stress
range at the fifth thermal cycle is 35.4 m a . This is much
larger than that (28 Mpa) at the center of the corner
96.5Sn-3.5Ag solder joint on the conventional PCB [45].
Again, this is because of the larger thermal expansion
mismatch among the chip, the build-up resin, and the PCB.
The shear-stress history at the center of the corner 62Sn2Ag-36Pb solder joint on the microvia build-up PCB has
been determined in [49] and the shear stress range at the
fifth thermal cycle is 33.37 MPa (Table 5 ) , which is
smaller than that with the 96.5Sn-3SAg lead free solder
Time-Dependent Shear Creep Strain
The shear creep strain history at the center of the
corner 96.5Sn-3.5Ag solder joint on the microvia build-up
PCB is shown in Figure 12. It can be seen that the shear
creep strain range at the fifth thermal cycle is 0.016. This
is much larger than that (0.01) at the center of the corner
96.5Sn-3.5Ag solder joint on the conventional PCB [45].
Thus, the effect of the build-up layer is to increase the
stresses and creep strains in the solder joints. The shear
creep strain history at the center of the corner 62Sn-2Ag36Pb solder joint on the microvia build-up PCB has been
determined in [49] and the shear creep strain range at the
fifth thermal cycle is 0.015 (Table 5), which is slightly
smaller than that with the 96.5Sn-3.5Ag solder.
Creep Strain Energy Density Range
The creep strain energy density range at the center of
the corner 96.5Sn-3.5Ag solder joint on the microvia
build-up PCB can be determined from the area of the fifth
shear stress and shear creep strain hysteresis loop, which is
0.36 MPa. This is much larger than that (0.26 MPa) at the
center of the corner 96.5Sn-3.5Ag solder joint on the
conventional PCB [45]. Thus, the effect of the build-up
layer is to increase the creep strain energy density range of
the solder joints.
The creep strain energy density range at the center of
the corner 62Sn-2Ag-36Pb solder joint on the microvia
build-up PCB has been determined in [49] and the creep
strain energy density range at the fifth thermal cycle is
0.32 MPa (Table 5 ) , which is slightly smaller than that
with the 96.5Sn-3.5Ag lead-free solder.
Summary and Discussion
Time-temperature-dependent nonlinear analyses of
solder bumped WLCSP on PCB assemblies with 96.5Sn3.5Ag and 62Sn-2Ag-36Pb solder joints have been
presented. Also, the effects of microvia build-up PCB on
the WLCSP solder joint reliability have also been
provided. The implicit creep model '(TBOPT=8) of
ANSYS, Release 5.6.1 has been used for this study. Some
important results are summarized as followings.
The implicit model of ANSYS for solders obeying
Garofalo-Arrhenius steady-state creep constitutive
equation works very well and converges very fast.
The input data (Cl, C2, C3, and C4 for creep analysis
of ANSYS) for a few solder alloys are provided. It
should be noted that there is an error in the present
release (The constants C2 and C3 should be interchanged), and it will be corrected in the next release
of ANSYS.
The effects of the additional microvia build-up layer
in the 963311-3.5Ag lead-free solder bumped WLCSP
PCB assemblies are to reduce the global deflection of
the assemblies and to increase the local displacement
of the solder joints.
The effects of the additional microvia build-up layer
in the 96.5Sn-3.5Ag lead-free solder bumped WLCSP
PCB assemblies are to increase the shear stress range,
shear creep strain range, and creep strain energy
density range in the solder joints, especially the
corner one.
The effect of the additional microvia build-up layer in
the 96.5Sn-3.5Ag lead-free solder bumped WLCSP
PCB assemblies is to reduce the thermal fatigue life
of the solder joints, especially the corner one.
The shear stress range, shear creep strain range, and
creep strain energy density range in the 96.5Sn-3.5Ag
lead-free solder joints of the microvia build-up PCB
assemblies are slightly larger than those in the 62Sn2Ag-36Pb solder joints on the microvia build-up PCB
assemblies. Thus, the thermal fatigue life of the 62Sn2Ag-36Pb solder joints is slightly better than that of
the 96.5Sn-3.5Ag solder joints.
The maximum stress in the microvia for the current
imposed thermal loading condition is less than the
ultimate strength of the electroplated copper. Also,
the maximum strain in the microvia is very small.
60
2000 Int'l Symp on Electronic Materials & Packaging
35
,
I
A = 9.0800
E = 15.073
B = 10.578
C = 12.076
D = 13.575
F = 16.571
G = 18.070
H = 19.568
(a) Time = 588 sec.
-0.06
-0.05
-0.04
-0.03
-0.02
0.00
-0.01
A = 10.213
B = 11.409
C = 12.606
D = 13.803
Shear Creep Strain
Figure 10: Creep Hysteresis Loops at the Center
of the Corner Solder Joint
35
E = 15.000
F = 16.197
G = 17.394
H = 18.591
I
!
30
n 25
a" 20
F
15
g 10
E
(b) Time = 14988 sec.
Figure 13: von Mises Stress Contours in
the Corner Solder Joint
5
$ 0
c
c/j -5
-10
0
5000
10000
15000
A = 0.007529
B = 0.016516
C = 0.025503
D = 0.034490
20000
E = 0.043478
F = 0.052465
G = 0.061452
H = 0.070439
Time (sec)
Figure 11: Shear Stress Time History at the
Center of the Corner Solder Joint
1
(a) Time = 588 sec.
A = 0,014368
B = 0.037006
C = 0.059645
D = 0.082283
-0.06
1
0
5000
10000
15000
E = 0.104921
F = 0.127559
G = 0.150197
H = 0.172836
J
20000
Time (sec)
(b) Time = 14988 sec.
Figure 12: Shear Creep Strain Time History at the
Center of the Corner Solder Joint
Figure 14: Effective Plastic Strain Contours in
the Corner Solder Joint
61
2000 Int'l Symp on Electronic Materials & Packaging
Acknowledgements
The authors would like to thank ANSYS (especially
Dr. Metin Ozen of MCR) for their useful help.
17.
References
1. Lau, J. H., Low Cost Flip Chip Technologies for DCA,
WLCSP, and PBGA Assemblies, McGraw-Hill, New
York, NY, 2000.
2. Lau, J. H., and W-S R. Lee, Chip Scale Package:
Design, Materials, Process, Reliability, and
Applications, McGraw-Hill, NY, NY, 1999.
3. Lau, J. H., C. P. Wong, J. L. Prince, and W.
Nakayama, Electronic Packaging: Design, Materials,
Process, and Reliability, McGraw-Hill, New York,
NY, 1998.
4. Lau, J. H., and Y-H. Pao, Solder Joint Reliability of
BGA, CSP, Flip Chip, and Fine Pitch SMT
Assemblies, McGraw-Hill, New York, NY, 1997.
5. Lau, J. H., Flip Chip Technologies, McGraw-Hill,
New York, NY, 1996.
6. Lau, J. H., Ball Grid Technology, McGraw-Hill, New
York, NY, 1995.
7. Darveaus, R., and K. Banerji, “Constitutive Relations
for Tin-Based Solder Joints”, Proceedings of IEEE
Electronic Components & Technology Conference,
May 1992, pp. 538-551.
8. Lau, J. H., “Creep of 96.5Sn-3.5Ag Solder
Interconnects”, Soldering & Surface Mount
Technology, Vol. 15, September 1993, pp. 45-49.
9. Stromswold, E. I., Characterization of Eutectic TinSilver Solder Joints, Ph.D. Dissertation, The
University of Rochester, 1993.
10. Vianco, P. T., and D. R., ‘‘Issues in the Replacement
of Lead-Bearing Solders”, Journal of Metals, Vol. 45,
NO. 7, July 1993, pp. 36-40.
11. McCormack, M., and S. Jin, “Progress in the Design
of New Lead-Free Solders Alloys”, Journal of Metals,
Vol. 45,No. 7, July 1993, pp. 14-19.
12. Felton, L. E., C. H. Taeder, and D. B. Knorr, “The
Properties of Tin-Bismuth Alloys”, Journal of Metals,
Vol. 45, NO. 7, July 1993, pp. 20-25.
13. Glazer, J., “Microstructure and Mechanical Properties
of Pb-Free Solder Alloy for Low-Cost Electronic
Assembly: A Review”, Journal of Electronic
Materials, Vol. 23, No. 8, 1994, pp. 693-700.
14. Vianco, P. T., K. L. Erickson, and P. L. Hopkins,
Solid State Intermetallic Compound Growth Between
Copper and High Temperature, Tin-Rich Solder Part I : Experimental Analysis, Sandia National Labs
(Contract Number DE-AC04-94AL85000) Report,
1994.
15. Kang, S. K., and A. K. Sarkhel, “Lead (Pb) - Free
Solders for Electronic Packaging”, Journal of
Electronic Materials, Vol. 23, NO. 8, August 1994,
pp. 701-708.
16. Shangguan, D., A. Achari, and W. Green,
“Application of Lead-Free Eutectic Sn-Ag Solder in
No-Clean Thick Film Electronic Modules”, IEEE
Transactions on Components, Packaging and
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
3 1.
32.
62
Manufacturing Technology - Part B, Vol. 17, No. 4,
1994, pp. 603-61 1.
Yang, W., L. E. Felton, and R. W., Messler, “The
Effect of Soldering Process Variables on the
Microstructure and Mechanical ProDerties of Eutectic
Sn-Ag/Cu Solder Joints”, Journk of Electronic
Materials, Vol. 24, No. 10, 1995, pp. 1465-1472.
Hwang, J. S., Modern Solder Technology for
Competitive Electronics Manufacturing, McGrawHill, New York, NY, 1996.
Vianco, P., J. Rejent, I. Artaki, U. Ray, D. Finley, and
A. Jackson, “Compatibility of Lead-Free Solders with
Lead Containing Surface Finishes as a Reliability
Issue in Electronic Assemblies”, Proceedings of the
IEEE Electronic Components & Technology
Conference, May 1996, pp. 1172-1183.
Mei, Z., and H. Holder, “A Thermal Fatigue Failure
Mechanism of 58Bi-42Sn Solder Joints”, ASME
Transactions, Journal of Electronic Packaging, Vol.
118, June 1996, pp. 62-66.
Ren, W., M. Lu, S . Liu, and D. Shangguan, “Thermal
Mechanical Property Testing of New Lead-Free
Solder Joints”, Soldering & Surface Mount
Technology, Vol. 9 No. 3, October 1997, pp. 37-40.
Shangguan, D. A., and G. Gao, “Lead-Free and NoClean Soldering for Automotive Electronics”,
Soldering & Surface Mount Technology, Vol. 9 No. 2,
July 1997, pp. 5-8.
NCMS, Lead-Free Solder Project Final Report,
NCMS Report 040IREi96, August 1997.
Mei, Z. F. Hua, J. Glazer, and C. Key, “Low
Temperature Soldering”, Proceedings of IEMTS,
October 1997, pp. 463-476.
Iida, A., Y. Kizaki, Y. Fukuda, and M. Mori, “The
Development of Repairable Au-A1 Solid Phase
Diffusion Flip-Chip Bonding”, Proceedings of IEEE
Electronic Components & Technology Conference,
May 1997, pp. 101-107.
Hua, F., Z. Mei, and J. Glazer, “Eutectic Sn-Bi as an
Alternative to Pb-Free Solder”, Proceedings of
Electronic Components & Technology Conference,
May 1998, pp. 277-283.
Grusd A., “Lead Free Solders in Electronics”,
Proceedings of Surface Mount International
Conference, August 1998, pp. 648-661.
Biocca, P., “Global Update on Lead-Free Solders”,
Proceedings of Surface Mount International
Conference, August 1998, pp. 705-709.
Wege, S . , G. Habenicht, and R. Bergmann,
“Manufacture and Reliability of Alternate Solder
Alloys”, Proceedings of Surface Mount International
Conference, August 1998, pp. 699-704.
Trumble, B. “Get the Lead Out”, IEEE SPECTRUM,
May 1998, pp. 55-60.
Smith 111, E., and L. Swanger, “Lead Free Solders - A
Push in the Wrong Directions?’, Proceedings of the
IPC technical Conference, March 1999, pp. F-10-1 F-10-6.
Kang, S., J. Horkans, P. Andricacos, R. Carruthers, J.
Cotte, M. Datta, P. Gruber, J. Harper, K. Kwietniak,
2000 lnt’l Symp on Electronic Materials & Packaging
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
C. Sambucetti, L. Shi, G. Brouillette, and D.
Danovitch, “Pb-Free Solder Alloys for Flip Chip
Applications”, Proceedings of IEEE Electronic
Components & Technology Conference, June 1999,
pp. pp. 283-288.
Lau, J. H., and C. Chang, “TMA, DMA, DSC, and
TGA of Lead Free Solders”, Soldering & Surface
Mount Technology, Vol. 11, No. 2, 1999, pp. 17-24.
Seelig, K., and D. Suraski, “The Status of Lead-Free
Solder Alloys”, Proceedings of IEEE Electronic
Components & Technology Conference, May 2000,
pp. 1405-1409.
Whitten, G., “Lead-free Solder Implementation for
Automotive Electronics”, Proceedings of IEEE
Electronic Components & Technology Conference,
May 2000, pp. 1410-1415.
Snowdon, K., C. Tanner, and J. Thompson, “Lead
Free Soldering Electronic Interconnect: Current Status
and Future Developments”, Proceedings of IEEE
Electronic Components & Technology Conference,
May 2000, pp. 1416-1419.
Butterfield, A., V. Visintainer, and V. Goudarzi,
“Lead Free Paste Flux Evaluation and Implementation
in Personal Commnuication Devices”, Proceedings of
IEEE Electronic Components & Technology
Conference, May 2000, pp. 1420-1425.
Nguty, T., S. Budiman, D. Rajkumar, R. Solomon,
and N. Ekere, and M. Currie, “Understanding the
Process Window for Printing Lead-Free Solder
Pastes”, Proceedings of IEEE Electronic Components
& Technology Conference, May 2000, pp. 1426-1435.
Ezawa, Hirokazu, M. Miyata, S . Honma, H. Inoue, T.
Tokuoka, J. Yoshioka, and M. Tsujimura, “Eutectic
Sn-Ag Solder Bump Process for ULSI Flip Chip
Technology”, Proceedings of IEEE Electronic
Components & Technology Conference, May 2000,
pp. 1095-1100.
Baynham, G., D. Baldwin, K. Boustedt, A. Johansson,
C. Wennerholm, D. Patterson, and P. Elenius, “Flip
Chip Processing of Lead-Free Solders and HalogenFree High Density Microvia Substrates”, Proceedings
of IEEE Electronic Components & Technology
Conference, May 2000, pp. 1101-1105.
Korhonen, T., P. Su, S. Hong, M. Korhonen, and C.
Li, “Under Bump Metallizations for Lead Free
Solders”, Proceedings
of IEEE
Electronic
Components & Technology Conference, May 2000,
pp. 1106-1110.
Zama, S . , D. Baldwin, T. Hikami, and H. Murata,
“Flip Chip Interconnect Systems Using Wire Stud
Bumps and Lead Free Solder”, Proceedings of IEEE
Electronic Components & Technology Conference,
May 2000, pp. 1111-1117.
Takeda, S . , and T. Masuko, “Novel Die Attach Films
Having High Reliability Performance for Lead-free
Solder and CSP”, Proceedings of IEEE Electronic
Components & Technology Conference, May 2000,
pp. 1616-1622.
Lau, J. H., and S. Pan, “Creep Behaviors of Flip Chip
on Board with 96.5Sn-3.5Ag and lOOIn Lead-Free
45.
46.
47.
48.
49.
50.
63
Solder
Joints”,
Proceedings
of
IMAPS
Microelectronics Conference, September 2000, pp.
866-873.
Lau, J. H., S. Pan, and C. Chang, “Creep Analysis of
Wafer Level Chip Scale Package (WLCSP) with
96.5Sn-3.5Ag and lOOIn Lead-Free Solder Joints and
Microvia Build-up Printed Circuit Board”, in
Packaging of Electronic and Photonic Devices,
ASME Book No. H01217, November 2000.
Lau, J. H., and C. Chang, “Overview of Microvia
Technologies”, Circuit World, Vol. 26, No. 2, January
2000, pp. 22-32.
Lau, J. H., and C. Chang, “Characteristics and
Reliability of Fast-Flow, Snap-Cure, and Reworkable
Underfills for Solder Bumped Flip Chip on Low-Cost
Substrates”, Proceedings of IEEE International
Electronics Manufacturing Technology Symposium,
October 2000, pp. 324-337.
Lau, J. H., “Critical Issues of Wafer Level Chip Scale
Package (WLCSP) with Emphasis on Cost Analysis
and Solder Joint Reliability”, Proceedings of IEEE
International Electronics Manufacturing Technology
Symposium, October 2000, pp. 33-46.
Lau, J. H., and S. W. R. Lee, “Effects of Build-up
Printed Circuit Board Thickness on the Solder Joint
Reliability of a Wafer Level Chip Scale Package
(WLCSP)”, IEEE Proceedings of Electronic
Materials and Packaging Conference, Hong Kong,
November 2000.
ANSYS User’s Manual, Release 5.6.1,2000.
2000 Int’l Symp on Electronic Materials & Packaging