ENABLING LOW-TEMPERATURE BONDING IN ADVANCED
PACKAGING USING ELECTRODEPOSITED INDIUM
Yi Qin, K. Flajslik, B. Sherzer, E. Banelis, I. Lee, R. Cho, L. Grippo, M. Imanari, M. Lefebvre, L. Wei,
W. Tachikawa, J. Dong, J. Calvert
Dow Electronic Materials
455 Forest Street, Marlborough, MA, USA, 01752
Dow.com
Potential Applications in Packaging
Chip package design concept courtesy of IMEC
3D IC
ETNA 3D chip stack with DRAM and Logic integration
Flexible Electronics
Potential low-T
solder application
Melting
Point
(ºC)
Electrical
Resistivity
(20ºC, nΩ·m)
Thermal
Conductivity
(W/m·K-1)
CTE
(25ºC,
µm/m·K-1)
In
156.6
83.7
81.8
32.1
Sn
231.9
115.0
66.9
22.2
New material requirements with fast
evolution of packaging
3D IC – Challenging thermal management
Indium for thermal interface materials
Unique physical and thermal properties of Indium
 Low melting point ( low assembly temp.)
Flexible electronics – sensitive to
assembly temperature
 Soft, flexible metal
 High thermal conductivity
 Potential to alloy with other solder metals
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
Indium for low temperature bonding
2
Potential Applications in Packaging
Case 1: C4 In bumps
Case 2: multi(thin)-layer bonding
Interconnect
Electrodeposited indium bumps
(as-plated)1
Reflowed indium bump array
(40 µm diameter, 100 µm pitch)2
In-including multilayer composite design for low-T bonding3
Materials
In & UBM (Ti/Pt/Au)
Materials
In/Sn/Au multilayer composite
Process
Electroplating and Sputtering
Process
Evaporation (e-beam and thermal)
Application
FC interconnection of FPAs (focal
plane arrays) and ROICs (read-out integrated
circuits)
Application
Photonic and fiber optic
device packaging
Properties
Enabled
Low temp. bonding; ductility at cryogenic
conditions; high reliability
Properties
Enabled
140ºC bonding temp.; low stress, fluxless
bonding
1Tian
et al, Journal of Electronic Materials, 2013
et al, Journal of Semiconductors, 2010
et al, Materials Science and Engineering A, 2002
2Huang
3Lee
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
3
Results & Discussion
Technical Approach
Indium capping on micro
copper pillar
Indium capping on standard
copper pillar
In
10µm
(INDOTHERM™)
8µm
PR 50 µm
PR 25 µm
30µm
Cu
18µm
(INTERVIA™ 8540)
20 µm
50 µm
Feature
Test wafer 1
Test wafer 2
Via diameter
20 µm
50 µm
Photoresist type
Dry film
Dry film
Photoresist height
25 µm
50 µm
Pitch
2:1~5:1
2:1~5:1
Open area
13%
9%
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
4
Results & Discussion
In-Ni equilibrium phase diagram*
Interfacial property investigation
FIB
Pt (Protection
Layer)
In
Ni/Cu
Si wafer
TEM
In-Ni IMC
 Void-free performance at the In-Ni interface.
*H. Okamoto et al, ‘Binary Alloy Phase Diagrams’ (ASM International, Metals Park, OH, 1990)
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
5
Results & Discussion
Indium capping on copper pillar
Sparse
Co-planarity
In
50 µm
10µm
(INDOTHERM™)
30µm
Cu
(INTERVIA™ 8540)
50 µm
8µm
18µm
25 µm
Height (µm)
WID%
DENSE
SPARSE
DENSE
SPARSE
Standard
pillars
48.3
55.6
7.3
5.6
Micro
pillars
22.3
24.0
5.3
1.4
20 µm
In
(INDOTHERM™)
WID(%) 
Cu
hmax  hmin
 100%
2havg
(INTERVIA™ 8540)
 Excellent co-planarity (WID) performance on the
test wafer of multiple pitches.
 Demonstration of Indium capping on both micro and
standard Copper pillars
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
6
Results & Discussion
Indium capping on copper pillar
DSC Analysis
In
50 µm
10µm
(INDOTHERM™)
30µm
Cu
(INTERVIA™ 8540)
50 µm
8µm
18µm
25 µm
156.8˚C
Heat flow
20 µm
In
(INDOTHERM™)
Cu
(INTERVIA™ 8540)
 Demonstration of Indium capping on both micro and
standard Copper pillars
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
Temperature (ºC)
 DSC (differential scanning calorimetry) analysis
showed a melting point of Indium at ~157ºC.
7
Results & Discussion
Indium capping on copper pillar
Reflow Trials
In
Reflow Profile
(INDOTHERM™)
Cu
Zone
Temperature
(˚C)
Time
(Seconds)
1
60
200
2
110
200
3
165
200
4
95
90
5
Cooling
60
(INTERVIA™ 8540)
Reflow
 Preliminary trials reflowed Indium caps at
a peak temperature as low as ~165ºC.
Void-free in X-ray
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
8
Results & Discussion
In-Sn equilibrium phase diagram*
Other low-T solder candidates
Solder Composition
Melting
temperature (oC)
52In 48Sn
118
50In 50Sn
125
58Bi 42Sn
138
58Sn 42In
145
100 In
157
60Sn 40Bi
170
96.5Sn 3.5Ag
221
100 Sn
232
160ºC
120ºC
Wide range of In-Sn solder
composition of low melting points
∆>110ºC
 In-Sn alloys, with a wide range of composition
window, could enable lower melting point than
pure Indium.
*H. Okamoto et al, ‘Binary Alloy Phase Diagrams’ (ASM International, Metals Park, OH, 1990)
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
9
Results & Discussion
Investigation Strategy
Strategy A: stacking of In and Sn
Sn
Strategy B: electrodeposition of In-Sn alloy
In-Sn
As-plated Alloy
Reflow
Reflow
IN
UBM
UBM
Current trials with INDOTHERM™
Indium plating chemistry
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
UBM
UBM
Future work of next generation
product development
10
Results & Discussion
SEM images of bump morphologies
Sn
In
Ni
Ni
In
Ni
PR residue
Nickel/Indium/Tin
Nickel/Indium
Nickel
Co-planarity
Step
Avg. Height
(um)
Range of height
(Max – Min) um
WID %
(Range)/(2*Avg. height)
Nickel
2.7
0.15
2.7
Nickel/Indium
5.5
1.10
10.0
Nickel/Indium/Tin
8.6
1.19
6.9
 Indium/Tin stacks on Nickel were prepared to form In-Sn alloys.
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
11
Results & Discussion
Reflow of In-Sn Stacks
DSC Analysis
Heat flow
Sn
In
Ni
As-plated
25 µm
Post reflow
Sn: 3µm
In: 3µm
Ni: 3 µm
 DSC (differential scanning calorimetry) analysis
showed a melting point of In-Sn alloy at ~119ºC.
20 µm
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
12
Development of Next-Gen Indium Chemistry
Optical images of Nickel and Nickel/Indium deposit on internal test wafer
72µm
72µm
75µm
72µm
Ni
75µm
In
Ni
75µm
In
Ni
25µm
•
•
Ni = NIKAL™ BP chemistry
(1 ASD, 55C, 60s)
Smooth Ni deposit
•
•
In = new electrolyte only, no
additive, 4ASD, 25C, 11s
Rough Indium deposit
•
•
In = next generation chemistry,
4ASD, 25C, 11s
Smooth Indium deposit
 Smooth nucleation of Indium on Ni
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
13
Development of Next-Gen Indium Chemistry
Characterization of Ni deposit
Optical Image
SEM Image
AFM Image
20000X
•
Ni only (NIKAL™ BP, 1 ASD, 55C, 60s); Area of AFM scan = 10µm X 10µm; Ra = ~ 4nm
Characterization of Ni/In deposit
20000X
•
•
Ni (NIKAL™ BP, 1 ASD, 55C, 60s) / In (next generation chemistry, 4ASD, 25C, 11s)
Area of AFM scan = 5µm X 5µm; Ra = ~ 13nm
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
14
Summary

INDOTHERM™ demonstrated capability of indium metallization for low-temperature solder in
advanced packaging applications.

Development of next-gen Indium chemistry is in progress to further improvement.
SOLDERON™ BP TS6000
SnAg Cap
Tmelt = ~221ºC
SnAg
Reflow
Temp.
INDOTHERM™
In Cap
In
Tmelt = ~157ºC
Cu
INTERVIA™ 8540 Cu
Cu
20 µm
20 µm
IEEE 66th ECTC – Las Vegas, NV, May 31 ~ June 3, 2016
15
Thank
You
Acknowledgement
Dow Core R&D – Analytical Science
® ™Trademark of The Dow Chemical Company ("Dow") or an affiliated company of Dow