WEEK 12 : RAM,ROMS, PLA’s
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The Johnson Counter

Johnson Counter
 The complement of the output of the last F/F is connected back to the D input
of the first F/F
 It produces a modulus of 2n, where n is the number of stages in the counter

Example: Truth Table of 4-bit Johnson Sequence
The Johnson Counter

Block Diagram of 4-bit Johnson Counter
Johnson Counters

We can add additional detection circuitry in order to generate the disjoint timing
signals like a ring counter.

This results in a Johnson Counter.

With a Johnson Counter, we can get 2n non-overlapping timing signals using n flipflops and some extra 2-input AND gates.
E&CE 223 Digital Circuits and Systems (Fall 2004 - A. Kennings)
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Textbook

Unused states are covered in Chapter 6, Section 6.5.

IMPORTANT: This section also describes some other types of counters (SwitchTail and Johnson Counters).

These are interesting examples…

They have unused states and are not self-correcting.
E&CE 223 Digital Circuits and Systems (Fall 2004 - A. Kennings)
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Read Only Memory (ROM)

Device that allows permanent storage of information.

Device has k input (address) lines and n output (data) lines.

We can store 2k £ n bits of information inside the device.

The address lines specify a memory location;

The data outputs at any time represents the value stored at the memory
location specified on the address lines.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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ROM Block Diagram

High level block diagram for a ROM:
k inputs
2^k x n
ROM
E&CE 223 Digital Circuits and Systems (A. Kennings)
n outputs
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ROM Block Diagram

Uses an address decoder such that the k address lines selects one word of the 2k
words of data stored in the ROM.
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
D(n-1)
D(2)
D(1)
D(0)
A(0)
A(1)
A(2)
A(k-1)
address
decoder
read
 Each of the 2k £ n bits inside of the ROM are programmable via opening and/or closing
switches.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Implementing Functions With ROM
 Can implement multi-input/multi-output logic functions inside of ROM.
 Data outputs are the logic functions and the address lines are the logic function
inputs.
 We create a ROM Table to store the logic functions.
 When an input (or address) is presented, the value stored in the specified
memory location appears at the data outputs.
 Each data output represents the correct value for its logic function.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Implementing Functions With ROM
 E.g., Implement the 3-input logics f0 =  (0,1,5,7), f1 =  (0,1,2,6) and f2 = 
(2,3,4) using a ROM.
c
b
a
1
A(0)
A(1)
A(2)
3-to-8 decoder
0
011 (3)
1
011 (3)
2
110 (6)
3
100(4)
4
100(4)
5
001 (1)
6
010 (2)
7
001 (1)
READ EN
8 x 3 ROM
D(2)
f2
E&CE 223 Digital Circuits and Systems (A. Kennings)
D(1)
f1
D(0)
f0
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Types of ROM
 Several technologies for implementing ROM:
 PROM (Programmable Read-Only Memory):
 PROM contains fuses giving logic value of 1 to all bits in device. Programming
means “blowing” fuses to give some bits a logic value of 0.
 Once programmed, that’s it – programming cannot be changed.
 EPROM (Electrically Programmable Read-Only Memory):
 Can be “erased” by exposure to UV light. Otherwise, same as PROM.
 EEPROM (Electrically Erasable Programmable Read-Only Memory):
 Can be “erased electrically”. Otherwise, same as a PROM.
 In programming, these devices all have an extra pin (or extra pins) where the
programming information (bit stream) is applied to do the programming.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Textbook
 ROM are described in Chapter 7, Section 7.5 of the textbook.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Random Access Memory (RAM)
 Storage device to which we can both read and write information.
data inputs
n
k
address
read
2^k x n
RAM
write
n
data outputs
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Random Access Memory (RAM)
 Internally, we need to be able to both read and write to bits of memory.
 Consider the following circuit that can function as a bit of memory:
select
select
input
S
Q
output
input
1 bit
memory
output
R
read/write
read/write
 Note: circuit is not really made like this, but this will function correctly to explain
the concept…
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Random Access Memory (RAM)
 Take 1-bit memory and connect them into an array:
data inputs
D(n-1)
D(2)
1 bit
memory
D(1)
1 bit
memory
D(0)
1 bit
memory
1 bit
memory
A(0)
select
A(1)
1 bit
memory
A(2)
1 bit
memory
1 bit
memory
1 bit
memory
input
1 bit
memory
output
read/write
A(k-1)
address
decoder
1 bit
memory
1 bit
memory
1 bit
memory
1 bit
memory
read/write
D(n-1)
D(2)
D(1)
D(0)
data outputs
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Random Access Memory (RAM)
data input
data input
data input
data ouput
data ouput
data ouput
data ouput
data input
 Can also share data lines with both input and output data using tri-state buffers
(enabled by the read/write signal):
select
input
read/write
D(n-1)
D(2)
E&CE 223 Digital Circuits and Systems (A. Kennings)
D(1)
D(0)
1 bit
memory
output
read/write
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Textbook
 RAM is described in Chapter 7, Sections 7.2 and 7.3 of the course textbook.
E&CE 223 Digital Circuits and Systems (A. Kennings)
Page 17
Programmable Logic Array (PLA)
 Programmable device capable of implementing functions expressed in SOP.
 Consists of input buffers and inverters followed by:
 Programmable AND plane, followed by
 Programmable OR plane.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Programmable Logic Array (PLA)
 Can implement m logic functions of n variables. Limit is the number of product terms
that can be generated inside of the device.
input buffers and inverters
AND plane
E&CE 223 Digital Circuits and Systems (A. Kennings)
OR plane
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Programmable Logic Array (PLA)
 Example implementing 2 logic functions of 3 inputs using a 3-5-2 PLA.
x1
x2
x3
f1 f2
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Programmable Array Logic (PAL)
 Similar to a PLA, but only has a programmable AND plane.
 The OR plane is fixed.
 Not as flexible as a PLA since only certain AND gates feed each OR gate, but has
fewer things that need programming.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Programmable Array Logic (PAL)
 Example of a PAL:
x1
x2
x3
f1
f2
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Programmable Array Logic (PAL)
 Sometimes the outputs are fed back internally and can be used to create product
terms.
x1
x2
x3
f1
f2
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Programmable Logic Array (PLA)
 PLA and PAL are described in Chapter 7, Sections 7.6 and 7.7 of the course
textbook.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Simple Programmable Logic Device (SPLD)
 To implement sequential circuits, take a PAL and add some flip-flops at the output of
the OR plane.
 For example…
from OR plane
D S Q
R
to AND plane
 Above circuit (plus SOP from the AND plane and OR gate) form a MacroCell.
 Several MacroCells together in the same IC is called an SPLD.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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