Die And Interconnect Considerations For Multi-Die Assemblies
DPBU - White Paper
Abstract
Handheld, portable and wireless products continue to be driven by the need for reduction in size and weight while at the same time meeting the demand for increased
functionality and performance. Component integration plays a key role in meeting these needs and demands. Multi-die assemblies, the combining of multiple components
in a single package or on a single substrate, provide an effective solution for advanced integration. These multi-die assemblies are not constrained by common wafer
fabrication processes and can integrate passive components to create self-contained systems. In this presentation the key attributes of multi-die assemblies are reviewed,
die interconnect technology selection issues and methods for assuring product quality will be discussed.
Introduction
Designers of handheld and small form factor applications are challenged by the need for
increased system functionality in a decreased amount of space. Some applications are
using system-on-chip (SOC) for increased integration, but often this approach cannot keep
pace with the timing of the market demand or the cost requirements. Conversion of current
standard packaged product designs to those incorporating bare die into multi-die
assemblies can result in footprint reductions and integration improvement providing an
alternative to SOC. The use of multi-die assemblies can be more cost effective since
current semiconductor technology is utilized and this results in reduced time-to-market.
The industry has historically met the size-functionality challenge through increased single
chip silicon integration and single component packaging miniaturization. The SOC
approach is a widely discussed and technically compelling approach to advanced
integration, however there are limitations in total cost and time-to-market. Multi-die
assemblies, the
Integration/size ¨C the level of integration will be highly dependent on the application
needs and cost structure. For multi-die assemblies
the ability to incorporate passives can have a significant impact, while packaging of the
SOC will effect the chip area to board use area ratio.
Time-to-market ¨C the multi-die design eliminates the need for a single, large, complex
chip. The more complex the needed solution, the greater the number of silicon design
cycles can be expected. Combining off-the-shelf die in a multi-die assembly will reduce
the design cycle and test development issues.
Design risk ¨C multi-die solutions are ideal for mixing fab process technologies or hard
to integrate functions. Off-the-shelf silicon functions result in lower risk, more cost
effective solutions. SOC risk will be highly dependent on design experience, available
process technology, IP and functional complexity.
Performance ¨C single chip integration provides the highest silicon performance
potential but can be diminished due to packaging and implementation. Multi-die
assemblies will provide greater than 2X improvement over individually packaged
components.
Development cost ¨C good multi-die
Addressing the requirements
The methodology and approach to development of an advanced integration solution is
unique for each application and system. Applications must consider the level of
integration, time-to-market, risk, performance, development costs, unit cost and testability.
The utility of an integration approach is not guaranteed without a thorough analysis of all
these demand aspects. Both SOC and multi-die assemblies can provide a solution for
advanced integration. Figure 1 provides an overview of the critical aspects involved in the
decision making process.
Neither SOC nor multi-die assemblies will meet all the requirements of the various
applications but each can offer benefits:
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combining of multiple components on a single substrate, can overcome these limitations
and provide an effective solution for advanced integration.
design methodology will result in cost predictability with marginally higher costs
compared to standard packaged product development. Due to the complexities
associated with SOC, higher development cost can be expected.
Unit cost ¨C run rate and NRE will be the determining factor. In general SOC will
provide the lowest unit cost in high volume applications.
Testability ¨C utilizing off-the-shelf die functions for multi-die assemblies means that
testability, reliability data and yield history exists. The simplified test of the individual
die will benefit the end application with less complex test requirements.
Both SOC and multi-die assemblies must be weighed against these criteria in determining
the approach most applicable to the design needs. Where rapid adoption of a solution is
paramount, multi-die is today¡¯s best choice and is clearly beneficial in capturing early
design-ins. It may be appropriate to consider SOC for the follow-on design to gain the
benefits of volume cost and the highest integration level.
Figure 1
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Technology considerations
Higher levels of integration and rapid time-to-market are required for a broad range of
small form factor applications. When evaluating the implementation of multi-die assemblies
special analysis should be given to the technical issues most likely to cause problems
during the development and introduction phase. The key considerations to be addressed
include:
- detailed understanding of the application requirements in terms of the priorities and the
trade-offs.
- understanding the complexity of the total solution.
- engineering experience in the various disciplines required to execute design thru assembly.
- resources availability not only internally but also from both component suppliers and
subcons
- capability requirements in the manufacturing processes and the determination if the
suppliers and subcons can support them.
- availability of each item on the bill-of-materials to support the volume needs,
performance requirements and cost.
Die interconnect
Planning the design of the multi-die assemblies requires selection of the die interconnect
technology. Analysis of the application¡¯s size requirements, variety of components,
process complexity, number of die I/O, performance, manufacturing capabilities and cost
are primary considerations. The most widely used approaches are chip-on-board (COB)
and flip chip. COB advantages include:
- existence of infrastructure
- knowledge base of the technology
- equipment availability
- process maturity
- manufacturing capacity in place
Flip Chip advantages include:
- smallest footprint
- improved electrical performance
- process integration with SMT
- high I/O efficiency
Comparison of these two interconnect methods is reviewed in Table 1. Each unique
application and design should dictate the appropriate interconnect technology to be
utilized.
High volume manufacturability of flip chip is still being refined. The same level of cost
stability does not exist for flip chip as compared to that of COB processing.
Development checklist
Each design needs to address and verify the items that can impact the quality, reliability or
cycletime of the manufactured assembly. These checklist items should be investigated
prior to initiating development:
- product availability in die form
- die format ability to meet interconnect requirements
- die supplier technical data sharing
- cost effects of manufacturing process
- substrate capabilities and match with components and interconnect method
- subcon manufacturing capabilities
- redesign/upgrade roadmap for the duration of the assembly lifetime
Special attention must be given to the needs to adopt redesigns, new technology and
material upgrades.
Applications effects
A well-developed plan and approach to multi-die assemblies development and
implementation will provide the end application advantages of:
- fast time to market due to less complex designs and improved testability
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- cost efficient solution due to optimized component use and processes
- lower risk implementation
- flexible design options and the ability to upgrade in timely manner
- improved performance over individually packaged die applications
Multi-die assemblies provide a compelling alternative to other approaches to advanced
integration.
Further development
Multi-die assemblies are being routinely used in a variety of small form factor application
to exploit the size, time-to-market and integration advantage they offer. Several new
issues will need to be addressed in the future for multi-die applications. Among these key
issues are:
- tighter bond pad pitches for COB die
- handling of thinner, more sensitive components
- incorporating lead-free alternatives
- improvement of die standards
- streamlining of manufacturing processes to reduce costs
- further cycle time reductions
The ability to provide adequate solutions to these issues will determine the propagation of
multi-die assemblies to broader use.
Summary
Improved integration and miniaturization techniques are critical for continued development
for a variety of small form factor applications. Use of multi-die assemblies can provide an
effective solution where the combination of time-to-market, size, performance, design risk,
and cost are the primary considerations.
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