Impact of single charge trapping in nano-MOSFETs: electrostatic vs. transport effects
C. Alexander*, A. R. Brown, J. R. Watling, and A. Asenov
Device Modelling Group
Department of Electronics and Electrical Engineering
University of Glasgow, Glasgow, G12 8LT, Scotland, UK
*
[email protected], Tel: +44 141 330 4792, Fax: +44 141 330 4907
Mass production MOSFETs will reach nanometre (sub-10nm) dimensions at the end of the ITRS.
Trapping of a single carrier charge in defect states near the Si/gate dielectric interface and the related local
modulation in carrier density and/or mobility will have a profound effect on the drain and gate current in
such devices. The problem will be exacerbated by the higher defect density in high-k dielectric materials
which are expected to replace SiO2 somewhere between the 65 nm and the 45 nm technology nodes. Current
fluctuations on such a scale will become a serious issue, not only as a source of excessive low frequency
(LF) noise in analogue and mixed-mode circuits, but also in dynamic and SRAM memories and other digital
applications. Depending on the device geometry a single or few discrete charges trapped in hot carrier or
radiation created defect states will be sufficient to cause a pronounced performance degradation in
decananometre MOSFETs.
Up to now the 3D simulation studies of the effects associated with trapping of a single charge in the
channel of decanano MOSFETs were carried out using the drift diffusion approximation, capturing only the
electrostatic effects [1, 2] which creates an inversion layer exclusion region around the trapped charge and
reduces the overall current flowing through the device. It is still debatable in the literature to what extent the
electrostatic reduction in the carrier density or the increased scattering in the channel is the dominant effect
reducing the current in response to the charge trapping. By using Monte Carlo (MC) simulations, featuring
ab-initio Coulomb scattering the impact of the increased scattering due to the trapped charge can be included
and separated from the local reduction in the carrier concentration observed in DD simulations.
In our Monte Carlo simulations the impurity scattering is removed from the conventional scattering rate
tables and introduced through the real space trajectories of the electrons in the mesh resolved potential of the
individual discrete dopants. This requires a correction to be applied at short range to the mesh calculated
force to account for the aliasing in the mesh solution of Poisson’s equation (see Fig. 1). Interpolating from
the mesh alone underestimates the magnitude of the Coulomb force and by diminishing the ability of the
charge to act as a scattering centre artificially increases mobility. As illustrated in Fig. 2 the ab-initio
approach reproduces the dopant concentration dependence of the mobility in Si.
We simulate three well scaled MOSFETs with channels of 3030, 2020 and 1010 nm with similar
relatively simple structure. In each case a single trapped charge is placed in the centre of the channel where
it’s effect is most pronounced. A low bias, 50mV, is applied between source and drain allowing Monte
Carlo simulation by means of a frozen field, thus reducing simulation time. This field is obtained from the
solution of the drift-diffusion equations. The current at a series of applied gate voltages is calculated with
and without the trapped charge present and the percentage reduction is obtained for both DD and MC
simulations (Figure 3-5).
The introduction of the trapped charge results in different reduction in the drain current in the DD and in
the MC simulations. In the DD simulations at low gate voltages the region in which the inversion layer
density is reduced by the trapped charge is large due to lesser screening resulting in large reduction in the
current. With the increase in the gate voltage and the corresponding increase in the inversion charge density
the region affected by the trapped charge becomes more localised as a result of screening by the mobile
charge in the channel, thus reducing it’s impact on the current. This results in a reduction in the relative
current change. Results from MC simulations show the same trend as DD, however the reduction in current
is consistently larger. In this case not only the electrostatics but the increased scattering by the screened
Coulomb potential of the trapped charge both play vital roles in reducing the current. The electrostatics plays
a more important role at gate voltages close to the subthreshold regime and for larger devices. This is evident
from the DD results being a larger fraction of the results obtained from MC under these conditions. At higher
gate voltages and smaller devices MC results show much greater reduction in current associated with the
scattering from the trapped charge. The impact the trapped charge within the MC simulation framework
becomes clear when analysing the average electron velocity in a 1010nm device illustrated in Figs6 and 7.
Note that the trapping of a single electron in a 1010 nm MOSFET reduces the drive current by 20%.
[1] A. Asenov, R. Balasubramaniam, A. R. Brown and J. H. Davies, IEEE Trans. Electron Dev., 50 839 (2003).
[2] A. R. Brown, A. Asenov and J. R. Watling, IEEE Trans. on Nanotechnology, 1 195 (2002)
1000
1500
750
1000
2
-1 -1
Moblity (cm V s )
500
500
250
Ensemble Average Temperature (K)
! "
0
1e+15
Figure 1: Force interpolated from Poisson mesh plotted
alongside the proposed short-range force.
0
1e+19
Figure 2: Concentration dependant mobility results using abinitio MC simulations compared with experimental values.
Also shown is the average temperature clearly showing the
increasing trend.
,
,
,
,
, 1 1 , 1 1 1e+17
1e+18
1e+16
-3
Doping Concentration (cm )
Figure 3: Percentage reduction in current upon introducing a
trapped charge in the centre of the channel. Results for driftdiffusion (DD) and Monte Carlo (MC) are shown for a channel
length of 30nm
0.4
-1
0.3
0.2
Velocity [ 10 cm s ]
7
,
0.5
,
Figure 4: Percentage reduction in current upon introducing a
trapped charge in the centre of the channel. Results for driftdiffusion (DD) and Monte Carlo (MC) are shown for a channel
length of 20nm
, 1 1 0.1
0
Trapped Charge
-0.1
-0.2
10
No Trapped Charge
15
20
30
25
35
Position [nm]
40
45
50
Figure 5: Percentage reduction in current upon introducing a
trapped charge in the centre of the channel. Results for driftdiffusion (DD) and Monte Carlo (MC) are shown for a channel
length of 10nm
Figure 6: Velocity profile though the position of the trapped
charge with and without it present for the 10nm device. The
effect of the charge extends beyond its electrostatic influence.
(a)
(b)
Figure 7: Velocity along the channel (a) without and (b) with trapped charge for the 10nm device with a gate voltage of 1.0V.