Chapter 4
Integer JAVA Virtual Machine
Processor Block Diagram
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ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
Register Definitions
PC
Program Counter: Access Data in Method Area
MBR
Memory Branch Register: Instruction and Instruction Parameter 8-bit register
MAR
Memory Address Register: Address for external data memory space
MDR
Memory Data Register: Data input and output to external memory
SP
Stack Pointer: Address pointer to the top of the system stack
LV
Local Variable: Address pointer to the bottom of the local variable frame
CPP
Constant Pool Pointer: Pointer to the bottom of the constant pool
TOS
Top Of Stack: The data value at the top of the stack
OPC
Old PC (?): A scratch or temporary register typically used for branching and the
temporary storage of old PC values in computations
H
Holding: A temporary register for holding one of the two ALU operands
Additional Register Definitions
MPC or PC
MicroProgram Counter: Internal microcode address register
MIR or IR
Microinstruction Register: Internal instruction used to control the IJVM
MAR addressing of 32-bit words
using an external Byte wide Memory Addressing Bus
Note: all external data memory is assumed to be perfectly aligned on 4-Byte boundaries.
2 of 14
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
MIR Content
B-Bus Selection 4:16 Decoder
B-Bus Register Selected
B-Bus Instruction
Field
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MDR
PC
MBR
MBRU
SP
LV
CPP
TOS
OPC
Unassigned
Unassigned
Unassigned
Unassigned
Unassigned
Unassigned
Unassigned
3 of 14
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
IJVM Programmer’ Model and Organization
Method Area
External Program Memory containing the IJVM program to be
executed. The internal PC is a pointer in the Method Area to the
next instruction to be executed. The method area is accessed using
the PC with 8-bit instructions and parameters loaded into the
MBR.
Constant Pool
External Data Memory containing compiled constants (e.g. values,
strings, pointers, etc.) required by the Methods to execute
programs.
Local Variable Frame
External Data Memory allocated for the storage of variables for the
method being executed. When a method is invoked, a local
variable frame of predefined size is established (allocated) for all
local variables used by the method
Operand Stack
External Data Memory used for the storage of temporary operands
that are placed on the stack. The Operand Stack maximum size is
known when a Method is invoked.
4 of 14
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
IJVM Instruction Set Architecture
Hex
0x10
0x13
0x15
0x36
0x57
0x59
0x5F
Mnemonic
Basic Stack Operations
BIPUSH byte
LDC_W index
ILOAD varnum
ISTORE varnum
POP
DUP
SWAP
Meaning
Data Movement Instructions
Push byte onto stack
Push constant from constant pool onto stack
Push local variable onto stack
Pop word from stack and store in local variable
Delete word on top of stack
Copy top word on stack and push onto stack
Swap the two top words on the stack
0x60
0x64
0x7E
0x80
0x84
Operand Arithmetic
IADD
ISUB
IAND
IOR
IINC varnum const
ALU Instructions
Pop two words from stack; push their sum
Pop two words from stack; push their difference
Pop two words from stack; push Boolean AND
Pop two words from stack; push Boolean OR
Add a constant to a local variable
0x99
0x9B
0x9F
0xA7
Branching
IFEQ offset
IFLT offset
IF_ICMPEQ offset
GOTO offset
Flow Control Instructions
Pop word from stack and branch if it is zero
Pop word from stack and branch if it is less than zero
Pop two words from stack; branch if equal
Unconditional branch
0x00
0xC4
Misc.
NOP
WIDE
Other Instructions
Do nothing
Prefix instruction; next instruction has a 16-bit index
Special Operations
0xB6 INVOKEVIRTUAL disp
0xAC IRETURN
Subroutine/ISR Control Instructions
Invoke a method
Return from method with integer value
5 of 14
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
Compiling JAVA to IJVM
6 of 14
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
Implementing IJVM Instructions
A sequence of microinstructions is required to execute each IJVM instruction or
macroinstruction. The sequence for each instruction is predefined and the microprogramming
code is stored in internal microcode memory. The microinstructions may be thought of as a
micro-assembly language (MAL).
The microcode is defined using a symbolic language or pseudo-code that identify every MIR
field required for each and every microinstruction. The microinstruction code must define every
internal CPU action that occurs during an internal microinstruction cycle.
The symbolic microcode consists of a label, an operation, and comments. The label is used to
assign the address of the microinstruction in the microcode space. The operation field
symbolically represents all MIR control functions. The comment field is used to describe the
code, machine state, or machine operations.
Allowed ALU Operations
Source and Destination include any allowable B-bus or C-bus registers in the MIR.
Note: this symbolic code defines the B-bus, C-bus, and ALU MIR fields. For a complete
instruction, we must also include fetch, memory read and write, the JAMX bits and the next
microinstruction field.
7 of 14
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
Instruction example
IADD (0x60h)
Pop two words from stack; push their sum
JAVA:
IADD
MAL:
main1 and iadd1(0x015) to iadd3
Things to do:
Increment the PC to the next instruction and fetch the next instruction.
Use the TOS register value (avoid reading the stack @SP) and move it to the H register.
Decrement the SP (SP=SP-1), request the data at the new SP (using MAR=SP) and read in the
data (to the MDR) at the new SP location.
Add the two registered values (H and MDR). Put the result into TOS register and write it to the
memory at the new SP address (MDR using MAR=SP).
Note: there are memory access delays that must also be accounted for!
Label
Operations
Comments
main1
PC = PC + 1; fetch; goto (MBR)
MBR holds opcode (0x60h);
get next byte; dispatch
iadd1
MAR = SP = SP-1; rd
Read in next-to-top word on stack
iadd2
H = TOS
H = top of stack
iadd3
MDR = TOS = MDR + H; wr;
goto main1
Add top two words; write to top of
stack
main1
PC = PC + 1; fetch; goto (MBR)
MBR holds opcode (0x60h);
get next byte; dispatch
8 of 14
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
Executing the JAVA IADD Instruction in Mic-1
Cycle
0
1
2
3
4
MPC
main1
iadd1
iadd2
iadd3
main1
INST
PC= PC+1;
fetch; goto
(MBR)
MAR= SP =
SP-1; rd
H= TOS
MDR= TOS=
MDR+H; wr;
goto main1
PC= PC+1;
fetch; goto
(MBR)
gt (iadd1)
iadd2
iadd3
main1
gt (MBR)
PC
fetch
PC
PC+1
fetch
MBR
iadd1
SP-1
SP-1
wr
(@SP-1)
MDR+H
Next MPC
MAR
rd/wr
INST
SP-1
rd
MDR
SP
SP
5
SP-1
LV
CPP
TOS
(@SP)
MDR+H
H
TOS (@SP)
9 of 14
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum,
Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
ECE 357
The IJVM MAL
IJVM Microinstruction 1 (MIC-1) Architecture Language (1 of 4)
main1
PC = PC + 1; fetch; goto (MBR)
nop1
iadd1
iadd2
iadd3
goto main1
MAR = SP = SP-1; rd
H = TOS
MDR = TOS = MDR + H; wr;
goto main1
MAR = SP = SP-1; rd
H = TOS
MDR = TOS = MDR
H; wr;
goto main1
MAR = SP = SP-1; rd
H = TOS
MDR= TOS = MDR AND H; wr;
goto main1
MAR = SP = SP-1; rd
H = TOS
MDR = TOS = MDR OR H; wr;
goto main1
MAR = SP = SP + 1
MDR = TOS; wr; goto main1
MAR = SP = SP-1; rd
isub1
isub2
isub3
iand1
iand2
iand3
ior1
ior2
ior3
dup1
dup2
pop1
pop2
pop3
swap1
TOS = MDR; goto main1
MAR = SP-1; rd
swap2
swap3
MAR = SP
H = MDR; wr
swap4
swap5
MDR = TOS
MAR = SP-1; wr
swap6
TOS = H; goto main1
10 of 14
MBR holds opcode; get next byte;
dispatch
Do nothing
Read in next-to-top word on stack
H = top of stack
Add top two words; write to top of
stack
Read in next-to-top word on stack
H = top of stack
Do subtraction; write to top of
stack
Read in next-to-top word on stack
H = top of stack
Do AND; write to new top of stack
Read in next-to-top word on stack
H = top of stack
Do OR; write to new top of stack
Increment SP and copy to MAR
Write new stack word
Read in next-to-top word on stack
Wait for new TOS to be read from
memory
Copy new word to TOS
Set MAR to SP-1; read 2nd word
from stack
Set MAR to top word
Save TOS in H; write 2nd word to
top of stack
Copy old TOS to MDR
Set MAR to SP-1; write as 2nd
word on stack
Update TOS
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
IJVM Microinstruction 1 (MIC-1) Architecture Language (2 of 4)
bipush1
bipush2
bipush3
iload1
SP = MAR = SP + 1
PC = PC + 1; fetch
MDR = TOS = MBR; wr; goto
main1
H = LV
iload2
MAR = MBRU + H; rd
iload3
MAR = SP = SP + 1
iload4
PC = PC + 1; fetch; wr
iload5
istore1
TOS = MDR; goto main1
H = LV
istore2
MAR = MBRU + H
istore3
istore4
istore5
istore6
wide1
wide_iload1
MDR = TOS; wr
SP = MAR = SP-1; rd
PC = PC + 1; fetch
TOS = MDR; goto main1
PC = PC+ 1; fetch; goto (MBR
OR 0x100)
PC = PC + 1; fetch
wide_iload2
H = MBRU << 8
wide_iload3
wide_iload4
H = MBRU OR H
MAR = LV + H; rd; goto iload3
wide_istore1
PC = PC + 1; fetch
wide_istore2
H = MBRU << 8
wide_istore3
wide_istore4
H = MBRU OR H
MAR = LV + H; goto istore3
ldc_w1
PC = PC + 1; fetch
ldc_w2
ldc_w3
ldc_w4
H = MBRU << 8
H = MBRU OR H
MAR = H + CPP; rd; goto iload3
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MBR = the byte to push onto stack
Increment PC, fetch next opcode
Sign-extend constant and push on
stack
MBR contains index; copy LV to
H
MAR = address of local variable
to push
SP points to new top of stack;
prepare write
Inc PC; get next opcode; write top
of stack
Update TOS
MBR contains index; Copy LV to
H
MAR = address of local variable
to store into
Copy TOS to MDR; write word
Read in next-to-top word on stack
Increment PC; fetch next opcode
Update TOS
Multiway branch with high bit set
MBR contains 1st index byte;
fetch 2nd
H = 1st index byte shifted left 8
bits
H = 16-bit index of local variable
MAR = address of local variable
to push
MBR contains 1st index byte;
fetch 2nd
H = 1st index byte shifted left 8
bits
H = 16-bit index of local variable
MAR = address of local variable
to store into
MBR contains 1st index byte;
fetch 2nd
H = 1st index byte << 8
H = 16-bit index into constant pool
MAR = address of constant in pool
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
IJVM Microinstruction 1 (MIC-1) Architecture Language (3 of 4)
iinc1
H = LV
iinc2
MAR = MBRU + H; rd
iinc3
iinc4
iinc5
iinc6
goto1
goto2
PC = PC + 1; fetch
H = MDR
PC = PC + 1; fetch
MDR = MBR + H; wr; goto main1
OPC = PC - 1
PC = PC + 1; fetch
goto3
H = MBR << 8
goto4
goto5
goto6
iflt1
iflt2
iflt3
iflt4
H = MBRU OR H
PC = OPC + H; fetch
goto main1
MAR = SP = SP - 1; rd
OPC = TOS
TOS = MDR
N = OPC; if (N) goto T; else goto
F
MAR = SP = SP - 1; rd
OPC = TOS
TOS = MDR
Z = OPC; if (Z) goto T; else goto F
MAR = SP = SP - 1; rd
MAR = SP = SP - 1
ifeq1
ifeq2
ifeq3
ifeq4
if_icmpeq1
if_icmpeq2
if_icmpeq3
if_icmpeq4
if_icmpeq5
if_icmpeq6
T
H = MDR; rd
OPC = TOS
TOS = MDR
Z = OPC - H; if (Z) goto T; else
goto F
OPC = PC - 1; fetch; goto goto2
F
F2
F3
PC = PC + 1
PC = PC + 1; fetch
goto main1
12 of 14
MBR contains index; Copy LV to
H
Copy LV + index to MAR; Read
variable
Fetch constant
Copy variable to H
Fetch next opcode
Put sum in MDR; update variable
Save address of opcode.
MBR = 1st byte of offset; fetch
2nd byte
Shift and save signed first byte in
H
H = 16-bit branch offset
Add offset to OPC
Wait for fetch of next opcode
Read in next-to-top word on stack
Save TOS in OPC temporarily
Put new top of stack in TOS
Branch on N bit
Read in next-to-top word of stack
Save TOS in OPC temporarily
Put new top of stack in TOS
Branch on Z bit
Read in next-to-top word of stack
Set MAR to read in new top-ofstack
Copy second stack word to H
Save TOS in OPC temporarily
Put new top of stack in TOS
If top 2 words are equal, goto T,
else goto F
Same as goto1; needed for target
address
Skip first offset byte
PC now points to next opcode
Wait for fetch of opcode
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
IJVM Microinstruction 1 (MIC-1) Architecture Language (4 of 4)
invokevirtual1
PC = PC + 1; fetch
invokevirtual2
invokevirtual3
H = MBRU << 8
H = MBRU OR H
invokevirtual4
MAR = CPP + H; rd
invokevirtual5
OPC = PC + 1
invokevirtual6
PC = MDR; fetch
invokevirtual7
invokevirtual8
invokevirtual9
invokevirtual10
invokevirtual11
invokevirtual12
PC = PC + 1; fetch
H = MBRU << 8
H = MBRU OR H
PC = PC + 1; fetch
TOS = SP - H
TOS = MAR = TOS + 1
invokevirtual13
invokevirtual14
invokevirtual15
invokevirtual16
PC = PC + 1; fetch
H = MBRU << 8
H = MBRU OR H
MDR = SP + H + 1; wr
invokevirtual17 MAR = SP = MDR;
invokevirtual18 MDR = OPC; wr
invokevirtual19 MAR = SP = SP + 1
invokevirtual20
invokevirtual21
invokevirtual22
ireturn1
ireturn2
ireturn3
ireturn4
ireturn5
ireturn6
ireturn7
ireturn8
MDR = LV; wr
PC = PC + 1; fetch
LV = TOS; goto main1
MAR = SP = LV; rd
LV = MAR = MDR; rd
MAR = LV + 1
PC = MDR; rd; fetch
MAR = SP
LV = MDR
MDR = TOS; wr; goto main1
13 of 14
MBR = index byte 1; inc. PC, get
2nd byte
Shift and save first byte in H
H = offset of method pointer from
CPP
Get pointer to method from CPP
area
Save Return PC in OPC
temporarily
PC points to new method; get
param count
Fetch 2nd byte of parameter count
Shift and save first byte in H
H = number of parameters
Fetch first byte of # locals
TOS = address of OBJREF - 1
TOS = address of OBJREF (new
LV)
Fetch second byte of # locals
Shift and save first byte in H
H = # locals
Overwrite OBJREF with link
pointer
Set SP, MAR to location to hold
old PC
Save old PC above the local
variables
SP points to location to hold old
LV
Save old LV above saved PC
Fetch first opcode of new method.
Set LV to point to LV Frame
Reset SP, MAR to get link pointer
Wait for read
Set LV to link ptr; get old PC
Set MAR to read old LV
Restore PC; fetch next opcode
Set MAR to write TOS
Restore LV
Save return value on original top
of stack
ECE 357
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
A blank instruction page for practice.
Executing the JAVA Instructions in Mic-1
Cycle
0
MPC
main1
INST
PC= PC+1;
fetch; goto
(MBR)
Next MPC
1
2
3
4
5
6
gt (MBR)
PC
fetch
PC
MBR
uInst
PC+1
fetch
Next Inst
MAR
rd/wr
MDR
SP
LV
CPP
TOS
H
14 of 14
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum,
Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.
ECE 357