SARASWAT et al.: RAPID THERMAL MULTIPROCESSING FOR A PROGRAMMABLE FACTORY
159
Rapid Thermal Multiprocessing for a Programmable
Factory for Adaptable Manufacturing of IC’s
Krishna C. Saraswat, Fellow, IEEE, Pushkar P. Apte, Leonard Booth, Yunzhong Chen, Paul C. P. Dankoski,
F. Levent Degertekin, Gene F. Franklin, Life Fellow, IEEE, B. T. Khuri-Yakub, Senior Member, IEEE,
M. M. Moslehi, Senior Member, IEEE, Charles Schaper, Paul J. Gyugyi,
Y. J. Lee, J. Pei, and Samuel C. Wood, Member, IEEE
Absfruct- This paper presents an overview of research at
Stanford University on the development of concepts of a programmable factory, based on a new generation of flexible multifunctional equipment implemented in a smaller flexible factory.
This approach is demonstrated through the development of a
novel single wafer Rapid Thermal Multiprocessing (RTM) reactor
with extensive integration of sensors, computers and related
technology for specification, communication, execution, monitoring, control, and diagnosis to demonstrate the programmable
nature of the RTM. The RTM combines rapid thermal processing
and several other process environments in a single chamber,
with applications for multilayer in-situ growth and deposition
of dielectrics, semiconductors and metals. Because it is highly instrumented, the RTM is very flexible for in-situ multiprocessing,
allowing rapid cycling of ambient gases, temperature, pressure,
etc. It allows several processing steps to be executed sequentially
in-situ, while providing sufficient flexibility to allow optimization
of each processing step. This flexibility is partially the result of
a new lamp system with three concentric rings each of which is
independently and dynamically controlled to provide for better
control over the spatial and temporal optical flux profile resulting
in excellent temperature uniformity over a wide range of process
conditions namely temperatures, pressures and gas flow rates.
The lamp system has been optimally designed through the use of
a newly developed thermal simulator. For equipment and process
control, a variety of sensors for real-time measurements and a
model based control system have been developed. The acoustic
sensors noninvasively allow a complete wafer temperature tomography under all process conditioncritically important
measurement never obtained before. In an exemplary demonstration of multiprocessing, we have integrated three different
processes with disparate process conditions-cleaning, thermal
oxidation and CVD of silicon-sequentially in-situ. This technology integrates an entire MOS capacitor stack into one process
chamber as opposed to three stand alone pieces of equipment
needed in conventional technology. This will result in reduced
cost of the factory, reduction in cycle time and may provide
better device characteristics, since the interfaces between the
semiconductor, gate dielectric and gate electrode are free of
contamination from the room ambient. In general, adaptable
Manuscript received October 5, 1993; revised December 3, 1993 and January 12, 1994. This work was supported by ARPA through the T.1.IM.M.S.T.
program and SRC.
K. C. Saraswat, L. Booth, Y. H. Chen, P. Dankoski, F. L. Degertekin, G.
Franklin, B. T. Khuri-Yakub, C. Schaper, P. Gyugyi, J. Pei, and S. C. Wood
are with the Center for Integrated Systems, Stanford University, Stanford, CA
94305 USA.
P. P. Apte and Y. J. Lee were with the Center for Integrated Systems,
Stanford University, Stanford, CA 94305 USA. They are now with Texas
Instruments, Inc., P. 0. Box 655012, MS 944, Dallas, TX 75265 USA.
M. M. Moslehi is with Texas Instruments, Inc., P. 0. Box 655012, MS 944,
Dallas, TX 75265 USA.
IEEE Log Number 9216486.
manufacturing systems (AMS) based on this approach may offer
more economical small or large scale production, higher flexibility
to accommodate many products on several processes, and faster
turnaround to hasten product innovation.
I. INTRODUCTION
A. Trends and Challenges
T
HE SEMICONDUCTOR industry is currently facing a
number of challenges. For companies to be successful
in the future will demand rapid innovation, rapid product
introduction and ability to react quickly to a change in the
technological and business climate of microelectronics. These
technological advances in integrated electronics will require
development of flexible manufacturing technology for electronic systems.
In the conventional Mass Manufacturing Systems (MMS)
approach the processing is optimized by performing each step
in the fabrication process on a separate piece of equipment,
by processing identical wafers in large batches. The variation
is reduced by in-process and end-of-process monitoring and
statistical process control by feeding the information to subsequent runs. Wafer batching inhibits the use of in-situ monitoring and real-time control. Since there are several process parameters to optimize, statistical techniques require hundreds of
wafers to be processed. In the MMS approach it is difficult to
accelerate the learning curve. In addition, there are difficulties
in efficiently tracking and scheduling wafers when the variety
of part numbers is very large. This is an impediment in the
production of small quantities of a large variety of chips fabricated using different technologies. It is also an impediment to
rapid prototyping of chips, where it is desirable to accelerate
the learning cycle for innovative devices and processes.
At Stanford University we have built a large interdisciplinary program aimed at exploring radically different semiconductor manufacturing opportunities. The approach [ 11-[3]
as shown in Fig. 1 is to build a highly flexible computer
controlled manufacturing facility-the Programmable Factory
and in parallel with this factory, a suite of simulation tools the
Virtual Factory which emulate all functions of the real factory.
B. Programmable Factory
This paper presents an overview of the research at Stanford University, on the development of concepts of a pro-
0894-6507/94$04.00 0 1994 IEEE
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Senson for in-situ measurements
Fig. 1. Programmable and virtual factory for design and adaptable IC
manufacturing of VLSI circuits.
grammable factory, an altemative Adaptable Manufacturing
Systems (AMS) approach to IC fabrication, which may offer
more economical small or large scale production, higher flexibility to accommodate many products on several processes,
and faster tumaround to hasten product innovation [4]-[9]. The
Programmable Factory is a concept which seeks to emulate
the enormous power of abstraction that is possible in a stored
program computer. If the factory can be made sufficiently
flexible and if that flexibility can be invoked by a stored
“program,” then we can build upon the considerable experience of computer science to multiply human productivity. The
approach is to develop the “program” that will build chips
largely by using the Virtual Factory.
This approach is based on a new generation of single wafer,
flexible, multifunctional equipment with extensive use of computer integrated manufacturing (CIM) to further enhance the
flexibility. In this approach shown conceptually in Fig. 2
the new type of multiprocessing equipment quickly processes
one semiconductor wafer at a time, performs several process
steps in-situ in contrast to the conventional altemative of
slowly processing many wafers simultaneously and one step
per equipment [2], [4]. Single wafer processing facilitates the
use of in-situ monitoring and real-time control. Extensive use
of CIM for specification, monitoring, control, and information
management should make switching between processes faster
and more reliable, should increase the ease by which large
numbers of different products could simultaneously be routed
and tracked through the factory, and maximize equipment
utilization.
Rapid thermal processing (RTP) technology is an ideal
vehicle to demonstrate the concepts of a programmable factory
with flexible equipment. Because of its low thermal budget it
is eminently suited for performing thermal steps in submicron
ULSI manufacturing. The temperature and process environment can be changed very quickly. Yet, defect introduction
and process variations commonly observed in conventional
RTP systems have impeded its widespread acceptance. This
problem is caused by inadequate equipment design, lack of
sensors and poor control methodology. In this paper we have
described a novel single wafer Rapid Thermal Multiprocessing
1
(RTM) reactor [lo]-[ 121 which circumvents these problems.
We have described a new thermal simulator and its use to
design an optimum RTF’ system, a new acoustic thermometer
for wafer temperature measurement and a multivariable control
system. The simulator with inputs specified by user, e.g.,
lamp structure, reflector geometry and process conditions,
etc., can calculate the temperature distribution on the wafer
by taking into account radiation, convection and conduction.
Through simulations we have shown that the conventional RTP
systems can not provide transient and steady state temperature
uniformity under all processing conditions since the radiative
and convective heat exchange at the wafer are functions of
the processing conditions, and that the resultant nonuniformity
can not be corrected since there is no dynamic control of
the spatial optical flux profile. We have demonstrated such
control through two key innovations: a new lamp system
in which tungsten-halogen point sources are configured in
concentric rings to provide a circularly symmetric flux profile,
and multivariable real-time control whereby each of the rings
are independently and dynamically controlled to provide for
control over the spatial flux profile. The RTM combines rapid
thermal processing with selected process environments in a
single chamber, leading to applications for multilayer insitu growth and deposition of dielectrics, semiconductors and
metals.
By doing extensive integration of sensors, computers and
related technology for specification, communication, execution, monitoring, control, and diagnosis we demonstrate the
programmable nature of the RTM [2]. For equipment and
process control a model based real-time control system has
been developed [3 1I, [ 131-1 151.
To facilitate control, a variety of new acoustic sensors for
real-time measurements of wafer temperature and thin film
thickness have been developed [ 171-[20]. The presently available techniques are either invasive or are seriously dependent
upon wafer surface conditions which changes during processing. The acoustic temperature sensor infers the temperature
by measuring the velocity of sound through the bulk of the
wafer and hence is insensitive to wafer surface conditions and
the process environment. Through the use of multiple acoustic
sensors wafer temperature tomography has been demonstrated.
The overall system is very flexible for in-situ multiprocessing because it allows rapid cycling of ambient gases,
temperature, pressure, etc. It allows several processing steps
SARASWAT et al.: RAPID THERMAL MULTIPROCESSING FOR A PROGRAMMABLE FACTORY
to be done sequentially in-situ, while providing sufficient
flexibility to allow optimization of each processing step. In
an exemplary demonstration of multiprocessing, we have
integrated three different processes with disparate process
conditions-cleaning, thermal oxidation and CVD of silicon-sequentially in-situ. This integrates an entire MOS capacitor stack into one process chamber as opposed to three
stand alone pieces of equipment needed in conventional technology. This will result in reduced cost of the factory, reduction in cycle time and may provide better device characteristics, since the interfaces between the semiconductor, gate
dielectric and gate electrode are free of contamination from
the room ambient.
Economic modeling has been done to compare the AMS
approach to the MMS approach using a newly developed simulator, Stanford Cost and Operations Performance Emulator
(SCOPE). The AMS approach may offer more economical
small or large scale production, higher flexibility to accommodate many products on several processes, and faster tumaround
to hasten product innovation.
11. RAPID THERMAL MULTIPROCESSOR
(RTM)
Rapid thermal processing (RTP) technology, offers the
possibility of processing at high temperatures for very short
times and rapidly changing the processing environment. With
its limited thermal budget and its compatibility to flexible
single-wafer processing, RTP is eminently suited for performing thermal steps in state-of-the-art IC manufacturing. Yet,
defect introduction because of temperature nonuniformity and
process variations commonly observed in conventional RTP
systems have impeded its widespread acceptance in IC manufacturing. This problem is caused by inadequate equipment
design, lack of sensors for wafer temperature measurement
and poor control methodology. The main problem with the
conventional equipment used in manufacturing today lies
with the approach where optimal steady-state temperature
uniformity at one set of processing conditions is used to fix the
hardware geometry, leaving only one input variable-the lamp
power-for control. This control methodology is inadequate,
since the radiative and convective heat exchange at the wafer
are functions of the processing conditions, and the resultant
nonuniformity can be corrected only by dynamic multivariable
control of the spatial optical flux profile.
The problems of RTP can be understood through modeling
and simulation of the thermal environment. The main goal
of any theoretical modeling of RTP systems is to predict the
change in temperature as a function of time and wafer position.
The relevant equation that must be solved is [21]
where m is the mass of the wafer, Cp is the specific heat of
the wafer, T is the wafer temperature, t is time, and Qrad,
qconv and qcond represent the heat exchange at the wafer by
radiation, convection and conduction respectively. The more
detailed expressions for each of the heat transfer terms are as
161
follows:
(4)
where Qabs is the heat absorbed by the wafer, E is the wafer
emissivity, o is the Stefan-Boltzmann constant, A is the
area of the wafer exposed to the process ambient, h is the
convective heat transfer coefficient of the gas, IC is the thermal
conductivity of the wafer, and a is the cross-sectional area
for radial heat transfer across the wafer. h depends on the
pressure and gas flow characteristics, and often needs to be
experimentally determined. Equation (2) shows the strong
nonlinear dependence of the radiative heat loss, while (3)
(through h) shows that the convective heat loss depends on the
ambient. These equations are of particular importance, since
they indicate that variations in the temperature profile can be
introduced by varying process conditions.
Most of the commercially available RTP equipment typically employs single or multiple linear lamps, providing photon flux which has to be transformed into circularly symmetric
flux by the use of a reflector, to heat a circular wafer. In this
environment, the uniformity depends critically upon reflections
from the walls of the reflector and the chamber. Extensive
theoretical [22]-[24] investigations have been conducted at
Stanford to point out the problems of the conventional RTP
systems. Thermal modeling involved calculations of optimized
optical flux profiles for specified temperature profiles (in space
and time). The simulations show that an optimum steadystate profile degrades in uniformity when the temperature
or pressure are varied, if the original profile was optimized
for one particular temperature and pressure. Good uniformity
can be only obtained for a limited set of conditions, because
radiative heat loss is a nonlinear function of temperature ((2)),
and convective heat loss depends on the pressure, type of gas
and gas flow rate ((3)). This problem becomes even more
severe during transients (ramp-up and ramp-down) and there
is no way of correcting for transient nonuniformity at any
processing condition. These findings were confirmed through
extensive experimental work [ 111, [ 121. This conventional
approach of controlling a single input (in this case the lamp
power) is referred to as “scalar control.”
Our simulations suggested a significant modification-the
substitution of a fixed lamp source with multiple circularly
symmetric concentric rings of lamps that are independently
controlled and illuminate separate parts of the wafer to a
different extent to provide control authority. By dynamically
varying the power to each ring the light flux incident on
the wafer could be altered dynamically to compensate the
heat loss due to radiation and convection. The system has
multiple inputs (the lamp power) and multiple outputs, and
hence it is a prime candidate for multivariable control. The
simulations predicted that steady-state and transient nonuniformity can be dramatically minimized using multivariable
dynamic control. These conclusions were conveyed to Texas
Instruments and new lamp systems were then constructed at
Texas Instruments in which tungsten-halogen point sources
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. I, NO. 2, MAY 1994
162
I
Fig. 3.
i
(lamp position, reflector and chamber geometry), and control
input (power supplied to each lamp ring). The process inputs
determine the convection loss and radiation loss of the wafer.
The design and control inputs determine the heat flux to the
wafer supplied by each of the lamp rings. Some of radiation
emitted by the wafer is reflected by the chamber walls and the
reflector and can be reabsorbed by the wafer. The total heat
loss by the wafer and heat flux pattems supplied by the heat
source are then compared. If they match, uniform temperature
distribution is achieved across the wafer. Otherwise, the power
ratios (multivariable control) or the lamp positions (optimal
design) should be adjusted to provide the necessary heat flux
pattems.
The convection loss flux can be expressed by (3). It has
been shown both experimentally [21] and numerically [25]
that the convection loss of the wafer in a typical RTP system
is nearly all through natural convection. Therefore h is a
function of wafer temperature, gas pressure, and other gas
characteristics. In this simulation, an analytical solution of
h is used, as suggested by Levy [34]. Due to the gas flow
induced by natural convection, the gas near the edge of the
wafer is cooler than that near the center. Therefore the edge
of wafer loses more heat than wafer center. The radiation loss
is expressed by (2). Due to its larger exposure area, the edge
of the wafer experiences more radiation loss than wafer center.
The radiant flux pattem provided by each lamp ring consists
of three terms: direct radiation from lamp, reflected radiation
from chamber wall, and the reflected radiation from reflector.
The inner surface of the chamber and the wafer are gray,
diffuse, and emissivity of 0.6 is assumed. The lamp zones
are modeled as concentric, flat, blackbody surfaces. To take
into account the reflections in an RTP system with reflector,
the images of each lamp in the reflector can be considered as
additional lamps. This approach allows taking into account of
complex reflector geometry in the simulation.
Results of a nonoptimized lamp developed primarily
through extensive experimentation at Texas Instruments and
Stanford University are compared to that of optimized design
using the simulator in Fig. 5. Fig. 5(a) shows the heat flux
profiles of a nonoptimized RTF' system. The radii of three
lamp rings are 0, 5, and 10 cm. The diameter of the wafer is
10 cm. The simulation is run for nitrogen at one atmosphere
pressure and the powers to each lamp are set to achieve best
temperature uniformity around 1OOOOC. Because the positions
of the three lamp rings are not optimized, both the second
and third rings provide the peak heat flux at the edge of the
wafer, while the center lamp heats the center of the wafer.
Thus the total heat flux supplied by lamp heating can not be
matched to the total heat loss (dashed line in Fig. 5(a)). This
results in a cooler spot at the intermediate region of the wafer
with a temperature uniformity of f12OC (Fig. 6). To improve
the temperature uniformity, the positions of three lamp rings
are optimized, with radii of 1.25, 3.5, and 7.5 cm. The other
process conditions remain the same. The heat flux profiles
for such lamp arrays are shown in Fig. 5(b). The total heat
pattem supplied by three lamp rings can be matched to the
total heat loss well so the temperature uniformity is improved
to floc(Fig. 6).
-
Schematic of the Rapid Thermal Multiprocessor (RTM).
were configured in three or four independent concentric rings
to provide a circularly symmetric flux profile. The 3 ring lamp
was tested at Stanford and the 4 ring lamp was tested at
T.I. A multivariable control system where each of the rings
are independently and dynamically controlled to provide for
control over the spatial flux profile (Fig. 3) was developed at
Stanford. Using the new lamp and the controller in the RTM
we have demonstrated experimentally [ 111, [ 121 excellent
temperature control for all processing conditions. Specifically,
each of the three concentric lamp rings in our system forms
an independent input, that can be controlled dynamically as
the time-temperature profile evolves. We have demonstrated
that controlling multiple lamp inputs allows dynamic control
of the spatial lamp flux profile and hence heat loss due to radiation, reflection, convection, or conduction can be dynamically
compensated. This provides good temperature uniformity over
a wide range of processing conditions, including transients,
thus improving reliability of individual processes. We have
also demonstrated good temperature uniformity for a wide
range of process conditions namely temperatures, pressures
and gas flow rates, thereby adding process flexibility. Thus
RTP emerges as an attractive candidate with applications in
several aspects of flexible IC manufacturing.
111. RTP SIMULATION
Most of the presently available RTP systems have been
developed through past experience, extensive experimentation
and intuition. This results in consumption of time and money.
Following the Virtual Factory approach we used simulations
to develop the new lamp. In this section we briefly describe
a design methodology using RTP simulator for optimizing
temperature uniformity of an RTP system with multivariable
control of a circularly symmetric three zone lamp. For such an
RTP system, the temperature nonuniformity is mainly affected
by lamp design and can be significantly reduced.
The RTP simulator is illustrated in Fig. 4. The inputs of
the simulator are specified by the user, which may include
process inputs (gas, pressure, temperature, etc.), design inputs
SARASWAT ef al.: RAPID THERMAL MULTIPROCESSINGFOR A PROGRAMMABLE FACTORY
Radiation Absorbed
I63
Conduction
in Wafer
Temperature
Distribution on Wafer
RadialDistance
Fig. 4. Schematic of the RTP simulator.
Lamp 3
Si Wafer
Non-Optimized Lamp
Lamp Optimized Through Simulation
n
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0
1
2
3
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5
A
0
Radial Position (cm)
Fig. 5. Heat flux pattem of (a) nonoptimized lamp and (b) optimized lamp.
1
2
3
4
Radial Position (cm;
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LABORATORY CIM SYSTEM
,
4
-
CONTROLSYSTEM
CONTROL SYSTEM
MONlToRlNG
DIAGNOSIS
Radial Position
(cm)
Fig. 6. Wafer temperature profiles for nonoptimized and optimized RTP
system.
The results above suggest that for the RTP system with
multizone lamp control, the temperature uniformity is predominantly affected by lamp heat flux pattern, which is determined
by individual lamp and its position. Using this methodology
a new lamp can be easily designed for a specific wafer size,
chamber, and process with excellent temperature uniformity.
IV. AUTOMATION
Implementation of a control scheme in RTM required a
variety of software tools. This section informs the reader
briefly about the existence of these tools, gives other references, and suggests their relation to the virtualfactory and the
programmable factory.
Before going into the specific details of Stanford's automation of the RTM system, we mention several reasons for its
necessity. First, process objectives require that we optimize
temperature uniformity over transients and different process
conditions. With feedback control, the lifetime performance
of an RTM system can be enhanced, without depending
exclusively upon statistical methods to assure process quality.
Additionally, recipe development becomes easier. In contrast
to the traditional trial-and-error approach where large sets
of experiments are needed to generate new process recipes,
process synthesis using software essentially represents a systematic way of recipe generation that optimally uses existing
process knowledge.
The highest level tools used to automate the RTM fall
under the laboratory computer integrated manufacturing (CIM)
system environment. This is shown at the top of Fig. 7.
An integrated process specification system (SPEC) [26] has
been developed, which allows the user to access data in several different manners. This includes interfaces to SUPREM
and PISCES. Additionally, Widgets and Metawidgets provide
complete error checking on user inputs into the Widgets,
protocols for data transfer into and out of the Widgets, and
context sensitive help. The Distributed Information Service
(DIS) [27] is the umbrella name for a collection of basic
computer services that together provide an information sharing
-I
~-
Fig. 7. Schematic of computer integrated manufacturing (CIh4) system
for specification, monitoring and real-time control of the Rapid Thermal
Multiprocessing reactor.
substrate within the Stanford Center for Integrated Systems.
DIS includes a Persistent Object Store that contains information about a wide range of objects in the manufacturing
domain plus various services that enable users to locate,
share, and distribute information as well as other services.
The information stored using DIS includes semiconductor
device and process information plus knowledge about work
in progress (WIP), users, and equipment. DIS can be used by
a wide range of applications to manipulate a consistent set
of shared data. This includes design, specification, simulation,
manufacturing, test, and diagnosis programs.
A standard SECS agent communication system [28] in a
networked lab environment connects the upper half of Figure
7 and the lower half (i.e., the implementation of the RTM).
An artificial intelligence (AIS) system [29] for monitoring and
diagnosis has also been developed and tested for feasibility but
not yet implemented in the running system. The discrete event
system (DES) research [14] focused on the theoretical aspects
of applying DES theory to real-time systems, where timing is a
critical issue in determining which actions are considered safe
and allowable at a given time. This theory has been applied
to check recipes for correctness.
While Fig. 7 gives a broad overview of automation applied to the RTM, Fig. 8 shows the details of the interface
implemented at Stanford University. Automation is achieved
through the synthesis of a host development system (i.e., a
UNIX workstation) and an embedded multiprocessing control
system.
At the highest level in Fig. 8, users can access the reactor
from graphical user interfaces, via X-terminals connected over
an ethemet network, to specify, run, and monitor processes.
The host system is a SUN sparcstation running UNIX and Xwindows. Control software is run under the V,Works operating
system on the embedded system. The SUN acts as a gateway
between the embedded system and the X-terminals on the
ethemet. We also point out that an assortment of tools is
SARASWAT er al.: RAPID THERMAL MULTIPROCESSING FOR A PROGRAMMABLE FACTORY
165
V.
Remota Clients
and X-terminals
; i
Lab Control and Monitoring
Hardware Interlock
Supplies
Fig. 8.
Controllers
Hierarchy of RTM software. organization.
available such as StethoscopeTMto view real-time variables,
MATLABTMto compute control actions, e.g., nominal feedforward trajectories, and to aid in system identification.
Fig. 8 next focuses on the embedded system. In terms of
hardware, it consists of a VME chassis and multiple 68020
processors, linked to a distributed I/O network. It is essential
to have a real-time operating system at the lowest level to
guarantee fixed response time to lamp power changes, etc.
The hardware interlock guarantees that critical signals will not
conflict when applied to the real-time system.
This CIM environment provides compute power for realtime control of the equipment and the processes, flexibility
for adding new sensors and control algorithms, power for
implementing and executing higher level process descriptions,
and an environment for studying issues in computer integrated
manufacturing (e.g., user interfaces for operators, process
designers, process analysts; programming interfaces for equipment diagnosis, statistical and adaptive process control; interfaces to data and knowledge bases; and communications
protocols for higher level functions). In summary, the architecture was designed to be both flexible and expandable to meet
the varying and changing needs of a research environment
[ 131. These qualities would also be appropriate for adaptable
manufacturing systems.
TM
M
StethoscopeTMis a trademark of Real-Time Innovations, Inc
MATHLABTMis a trademark of Mathworks, Inc.
REAL-TIME
CONTROL
Control design on a particular system involves many
choices. Five notable choices are specifications, sensors and
their placement, actuators and their placement, a model of the
system, and a control law. While all of these are important in
development of complete control system, not all are discussed
in this section. Section VI addresses the issue of sensor
development and Section 111 suggests a method of actuator
placement. Instead, this section points out a few of the design
decisions particular to the Stanford RTM and focuses on the
control law used to achieve spatial temperature uniformity.
Because of the summary nature of this paper, only a few of
the major points are highlighted. More explicit descriptions
can be found in 1331, 1241, [23].
Two control strategies are applied to the RTM. The first
strategy is based upon a physics based model and uses an
Internal Model Control design procedure. The IMC approach
is described in [15], [16]. The second strategy is based
on empirically determined models and a Linear Quadratic
Gaussian control strategy (to be described below). Although a
physically based model can be derived from first principles, the
resulting models can be highly nonlinear and contain a number
of unknowns, such as time-varying emissivities, which makes
identifying exact physical models challenging.
Linear Quadratic Gaussian (LQG) control methodology is
an optimal control design methodology minimizing a quadratic
cost function subject to linear constraints with Gaussian noise
on the inputs and outputs. Because the empirically based
models are linear, they can be applied directly. The radial
symmetry of the RTP chamber, which complements the radial
symmetry of the silicon wafer, simplifies the design. Controllers designed via LQG require the designer to specify
both the cost function and the strength of the corrupting
noise signals. See [31], [32] for suggestions on the selection
of these parameters for an RTP system. Reasons for the
selection of an LQG controller include the ease with which this
methodology handles the multivariable case and the relative
simplicity of using a linear model. Simulation studies revealed
that scalar control, as opposed to multivariable control, would
not produce uniform temperatures over the wide range of
processing conditions desired for an RTP reactor [22]-[24].
Our research shows that the LQG control design can produce
a controller capable of achieving the requirements of spatial
and temporal uniformity to within several degrees over a wide
temperature range.
Fig. 9 shows a block diagram configuration of the LQG
controller. Several key features are cataloged here, First of all,
the model of the controller we are using operates upon differential inputs (i.e., temperatures) and differential outputs (i.e.,
power settings). Second, the saturation function is included to
assure that the limitations of the lamp design are not exceeded.
Because the signal lines in the figure represent vector signals,
multivariable saturation is implied. Multivariable saturation
was investigated and proven stable under certain conditions
using modifications to Lyapunov’s original stability analysis.
This saturation scheme has been named Control Reduction
Using SVD Hueristics (CRUSH). A third feature of the
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166
Fig. 9. Block diagram model of the LQG controller.
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Temperature ("C)
Fig. 10. Temperature dependence of Lamb wave group velocity.
LQG implementation is the use of integral control along the
controllable directions as determined by the singular value
decomposition of the DC gain matrix. The integral control
is augmented to the nominal system. For clarity, Fig. 9
does not show the ability to switch between multiple distinct
controller designs, even though this has been implemented into
the system. These enhancements demonstrate standard LQG
control utilizing several novel ideas.
In summary, different methodologies for multivariable control of the RTM were investigated and satisfactory results were
achieved. Experience has lead to suggestions for improvements
in the next-generation of RTP system [24],[22].
VI. SENSORS
For equipment and process control a variety of new acoustic
sensors for real-time measurements of wafer temperature and
thin film thickness have been developed [17]-[20].Temperature is a very critical parameter to be accurately measured
and controlled in RTP. At present, most RTP systems use
optical pyrometers and thermocouples to measure the wafer
temperature. Pyrometers are non contacting, nondestructive
devices. Their reading depends on the thermal radiation from
the wafer and they are very sensitive to emissivity variations.
However, there are many other factors such as deposited films,
backside roughness, doping levels that alter emissivity during
processing. The radiation from the heating lamp and reflections
from chamber walls also affect the pyrometer reading, making
the measurement inaccurate. Thermocouples are accurate to
1.5"C in a wide temperature range, but they should be in
contact with the wafer, and at high temperatures thermocouple
materials can cause contamination. Also the considerable
thermal mass of thermocouples can be a source of temperature nonuniformity. Thermal expansion is another technique
applied to temperature measurement, but its sensitivity is low
especially at high temperatures.
The silicon wafer is an anisotropic solid plate in which
many acoustic wave modes can be excited. The effect of
temperature on these waves shows itself in the elastic constants
of silicon. Since acoustic wave velocity is a direct function
of elastic constants, measuring velocity becomes a convenient
way to monitor the temperature. Solving the basic equations of
motion and applying free boundary conditions, the variation
of velocity as a function of temperature can be calculated.
Fig. 10 depicts the group velocity of the zeroth order antisymmetric Lamb wave mode as a function of temperature in the
O-lOOO°C range. This calculation is performed for propagation
in (100) direction of a (100)silicon wafer of thickness 0.5 mm
and at a frequency of 200 kHz, which are typical values used in
our work. The group velocity decreases linearly with increasing temperature in the whole range. In addition to the high
sensitivity, since the acoustic energy is completely confined
to the wafer, the waves are insensitive to the gas flow and
pressure variations in the chamber. The backside roughness of
the wafer does not affect the acoustic waves either, because it
is very small as compared to the wavelength which is in the
order of centimeters. Within the constraints of signal to noise
ratio of the entire system, currently with this technique, it is
possible to measure wafer temperature in-situ in O-1OOO"C
range with 1°C accuracy. Theoretical limit is much finer.
The basic system configuration for the acoustic pin-to-pin
time of flight technique is shown in Fig. 11. The quartz pins
used to support the wafer in RTP are also used to excite
acoustic waves in the silicon wafer, and pin-to-pin time of
flight information is used to monitor temperature. One end
of the quartz pin is sharpened to a point and the top is
rounded with a radius of few hundred pm. This geometry
ensures a reproducible point contact with the wafer. To the
other end, a piezoelectric transducer material (ET-SH) with
the same diameter of the quartz pin is bonded to excite acoustic
waves in the quartz rod. The resonance frequency of the
transducers is measured to be around 200 kHz. To isolate
the transducers from the high temperature and reactive gases
in the process chamber, a vacuum-sealed, nitrogen cooled
housing is constructed. Also three additional quartz pins are
used to guide the wafer. To excite the Lamb wave mode in
the wafer, a short electrical pulse is applied to the transducer
terminals. This pulse generates an extensional acoustic wave in
the quartz rod. At the quartz pin-wafer contact, the extensional
mode is converted to a Lamb wave mode in the wafer. After
propagating in the wafer the Lamb wave is first converted to
extensional mode in the other pin and then to an electrical
signal in the transducer. The pin-to-pin time of flight can then
be measured using proper electronics. The acoustic waves
travel through the bulk of the wafer and hence are immune
to the surface variations and the process environment. The
technique is virtually insensitive to process parameters such
~
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SARASWAT et al.: RAPID THERMAL MULTIPROCESSING FOR A PROGRAMMABLE FACTORY
Wafer
7
Lamb Wave
Extensional
1
wave
Quam rods
Transmit
Pulse in
1
~
Sensor location
\
Extensional
Receive
transduce
Waveform out
Silicon Wafer
Temperature = f(Lamb wave velocity)
m
m
Fig. 1 1 . Time of flight measurement between quartz pins. The acoustic
transducer is placed outside the processing chamber.
as surface roughness and reactive gases in the chamber, and
requires no modification on the wafer.
The pin-to-pin time of flight technique provides average
temperature measurement along the line connecting the transmitter and receiver pin locations on the wafer. Using multiple
pins with both transmit and receive capability, one can obtain
average temperatures of different regions of the wafer. These
measurements then can be used to obtain thermal images. To
investigate this capability, an experimental setup for wafer
temperature mapping has been constructed. Fig. 12(a) shows
the principle of the technique where 8 quartz pins are placed
close to the edge of the wafer on a circular array. Each pin
is spring loaded to have a reproducible contact to the wafer.
The lines show the paths of Lamb waves propagating in the
wafer in case of transmitting from opposite pins and receiving
by the others. With 8 pins, temperature measurements along
28 different paths can be made. The electronics and computer
control is similar to the 2 pin setup except for the addition
of multiplexing and transmitheceive switching circuitry to
enable temperature mapping. For each thermal image, first the
temperature measurements are obtained by transmitting from
one pin and receiving by the others and repeating the procedure
for all pins. The data is then fed to a program which converts
the time of flight to temperature and calculates the image pixel
values using tomographic reconstruction. Thermal image of
a 4“ silicon wafer formed by the system is shown in Fig.
12(b). To test the system, three thermocouples are placed on
different regions of the wafer. The temperature mapping pixel
values and thermocouple readings are in very good agreement,
showing the accuracy of the technique. The resolution can be
further improved by increasing the number of pins.
277%
262°C
0252°C
0225°C
Temperature Map
(b)
Fig. 12. (a) Measurement paths for 8 pins and rectangular pixel grid used
in tomographic reconstruction, (b) Reconstructed temperature tomographic
image of a silicon wafer heated nonuniformly.
This minimizes interfacial contamination between films, and
could improve yield since wafer-handling is reduced. Both
these points are becoming increasingly important in the ULSI
domain--for instance, a thinner oxide has more stringent contaminant (metal, organic, etc.) tolerances, and multiple process
steps (such as nitridation) increase wafer-handling in the nonmultiprocessing environment. Additionally, multiprocessing
has the potential of reducing equipment costs if it can replace
two or more pieces of dedicated-process equipment. Besides
providing process improvement, multiprocessing technology
needs to satisfy some other requirements. First, the thermal
budget of the process should be low, since dopant profiles have
to be tightly controlled in ULSI devices. Second, the process
should be simple, in that it should not have special requirements such as ultra-high vacuum, corrosive ambients and corresponding special chamber materials etc., since this escalates
equipment costs and degrades equipment reliability. Finally,
VII. MULTIPROCESSING
multiprocessing should not introduce cross-contamination: one
The key idea behind multiprocessing is the reduction or step should not leave a “fingerprint” that affects the next step
elimination of wafer exposure to the ambient between succeed- adversely. The challenge of multiprocessing then is to meet
ing process steps, by performing multiple process steps in-situ. all these requirements and yet realize the advantages, which is
I
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 7, NO. 2, MAY 1994
precisely what is demonstrated in this work. Obviously a key
part of meeting this challenge is the equipment itself, and the
RTM is uniquely suited in this context.
The unit processes developed in the RTM were ion implant
annealing, in-situ anhydrous hydrogen fluoride (AHF) cleaning, thermal oxidation of Si, nitridation of the oxide in an N2O
ambient and CVD of silicon. The implant dosage and energy
of As were 10l6 ions/cm2 and 40 keV respectively, and the
anneal was performed at 600OC and 1 Torr with 100 sccm of
N2 flowing. The in-situ AHF cleaning was done at 300OC and
1 TQITwith 70 sccm each of H2 and AHF flowing, followed by
a 30 second spike to 950°C with the same pressure and gas
flows. The oxidation was done at 900OC and 1 atmosphere
with 1 lpm oxygen flowing, on high-resistivity (11-20 ohmcmj, p-type, (100) wafers that underwent a modified RCA wet
clean before being inserted into the RTM. The N20 anneal
was done at 1OOO”C and 1 atmosphere with 1 lpm pure N20
flowing. The CVD of Si was performed with SiH4: Hz =
5050 sccm flowing, 600OC temp., 1 Torr press. The sheet
resistance of the implanted-annealed wafers was measured
with a Prometrix Omnimap machine, the oxide thickness with
a Gaertner ellipsometer and the Si film thickness with a
Nanometrics Nanospec/A€T micro-area gauge.
Several unit processes were combined in the multiprocessing technologies that are discussed in this section. While in
the previous sections we described the RTM’s capability of
maintaining uniformity over a variety of process conditions,
it is important to confirm that this translates to Uniformity for
specific unit processes, and this is demonstrated in this section.
The sheet resistance of a wafer implanted with As, and annealed at 600°C using an optimized recipe had a low standard
deviation (a)of 0.7%. The 0 for the thermal oxide is 4.39%,
while that for the CVD Si film is less than 0.86%. All wafers
were examined for slip defects, but none were observed. The
wafers that underwent oxidation were processed at a relatively
high temperature (90O0C), and the fact that they do not show
any defects reflects favorably on our process uniformity.
Three multiprocessing technologies for growing more reliable dielectrics were demonstrated. One common feature of
all these technologies is the requirement to cycle through
multiple transients and through a disparate set of process
conditions while maintaining uniformity. This task can be
performed only by ‘‘flexible” equipment that can optimize
each of the disparate process conditions. The RTM has such
flexibility, as is demonstrated by its ability to execute the three
multiprocessing technologies described below.
A . Nitridation of Oxides
Here, the technique of growing more reliable dielectrics by
‘‘nitriding” the oxide, and its implementation in the RTM is
discussed. The basic principle behind nitrided oxides is the
incorporation of N to strengthen the weaker bonds in the
dielectric. A study of nitridation [38] revealed that N atoms
initially get incorporated at the Si-Si02 interface, and the
oxide surface. This makes sense thermodynamically, since this
is the best way to lower the free energy of the Si-0-N system.
In other words, the N atoms find it easier to form bonds at the
interface and surface than the bulk of the dielectric-where
they have to break S i 4 bonds and disrupt the local crystalline
structure to get incorporated. Thus, the N atoms segregate
to the interface and strengthen the structure by satisfying
dangling bonds, and possible relieving some interfacial strain.
This thermodynamic propensity of atoms such as N is fortuitous for reliability, since the interface is the weakest link
in the chain for the initiation of dielectric breakdown. It
is not surprising therefore that many workers have reported
reliability improvements in nitrided oxides [39]-[42]. It is clear
from their work that multiple process steps are required to
achieve incorporation of nitrogen at the interface. Nitridation
in ammonia requires a reoxidation step to remove the H
that is incorporated, since H degrades the device [391, [401.
References [41] and [42] use an N2O anneal that has no
hydrogen, and hence this was selected as a technology for
implementing nitridation in the RTM.
Figure 13(a) shows a process sequence implemented in the
RTM for oxidation in dry 0 2 at 900”C, followed by an anneal
in N20 at 1OOO”C. Figure 13(b) shows a constant-current
stress test using substrate injection that compares the NzO
annealed oxide to a pure oxide, both dielectrics grown 100
A thick. The nitrided oxide has lower dVg/dQinj (= 2 x
V-cm2/C) and higher Qbd (= 45 C/cm2), as compared
to pure oxides (dVg/dQinj = 3.3 x lod2 V-cm2/C and Qbd
= 20 C/cm2). This was not intended to be a process study
of nitrided oxides, and therefore the values obtained here are
not necessarily the most optimal values possible. However,
two key points need to be made. First, strengthening the
interface using N atoms does improve the reliability of the
dielectric. Second, the process recipe shown in Fig. 13(a) was
generated using the flexibility of the RTM and the success of
this approach is reflected in the fact that the results shown
in Fig. 13(b) were achieved in the first pass. In summary, a
nitrided oxide technology using N2O has been demonstrated in
the RTM as a viable multiprocessing technology that improves
reliability of ultrathin dielectrics.
B . In-Situ Cleaning Using AHF
Several contaminants, including metallic, organic, and a
“native oxide layer,” deposit on a wafer due to exposure
to the clean-room ambient, and due to exposure to wet
chemicals. The native oxide can incorporate contaminants that
degrade properties of the film that is growdeposited on the
surface-for example dielectric films are very sensitive to
metallic contamination. Also, for oxide films of 30-100 A,
a native oxide thickness of 3-10 A becomes a significant
percentage of the overall oxide thickness. Thus, it may become
important to eliminate this contaminant native-oxide layer
in-situ. This section describes an in-situ clean implemented
in the RTM specifically for removing native oxide, prior to
growtlddeposition of a film.
Even a Si surface which has been stripped of oxide with
an HF dip will regrow an ultrathin native oxide layer within a
short time. The key factor for native oxide growth is the partial
pressure of H20 and 0 2 in the ambient, and a threshold value
exists for the partial pressure for different temperatures [35].
Above this threshold, an oxide layer will form. The regrowth
of a native oxide layer during wafer storage allso has been
-
SARASWAT er al.: RAPID THERMAL MULTIPROCESSING FOR A PROGRAMMABLE FACTORY
20.04
2.000’
Nitrided Oxide
/div.
r-
.oood
.oooo
Pure Oxide
-
I
TIME
SO.OO/d?v
I 01
J
500.0
(b)
Fig. 13. (a) Time-temperature profile for oxidation followed by an N20
anneal. (b) Lower trap-generation rate and improved f&d for the NzO oxide
as compared to the pure oxide. (Both dielectrics were 100 8, thick).
169
tures in the range 3 W 0 O 0 C , and the deposition process is
performed in-situ. After an extensive study of the parameters
affecting the efficacy of the AHF clean, it was observed that
a short (30 second) high-temperature (90OOC) “spike” was
required after the 300-400”C step, and immediately preceding
deposition. Here again the flexible nature of the RTM allowed
swift testing of multiple process conditions, and therefore
enabled swift process optimization. The wafers underwent a
modified RCA clean before being introduced into the RTM
chamber, and Fig. 14(a) shows the process sequence for the
in-situ AHF clean, followed by deposition of a Si film in
the RTM. The Si film was chosen rather than an oxide film,
because native oxide elimination is difficult to measure directly
if the film itself is an oxide. Auger analysis was performed
by depth profiling through the Si film into the Si substrate,
so that the native oxide (if any) would show up as an oxygen
peak. Fig. 14(b) shows the comparison between Auger profiles
for three samples, each with a different process condition: the
“AHF sample” with the exact process profile of Fig. 14(a), the
“Hz sample” with the same thermal profile of Fig. 14(a) but
using only HI instead of AHF, and the “control sample” where
only the deposition module from Fig. 14(a) as performed
with no in-situ cleaning step. As expected, the control sample
shows a sharp peak corresponding to an active oxide of
7-8 8, from the last wet clean (HCL:H202). This peak is
somewhat reduced for the Ha-sample, but it is the AHF-sample
that shows a complete elimination of the oxide peak, and
hence of the native oxide. Fig. 14 thus demonstrates a viable
multiprocessing technology in the RTM for the in-situ removal
of contaminant native oxide prior to film deposition/growth.
The salient features of the technology are that it is simple
and has a relatively low thermal budget. As discussed earlier,
native-oxide elimination may be an important contributor to
oxide reliability, and hence this multiprocessing technology is
potentially important for dielectrics. An experiment combining
in-situ AHF and dielectric growth will be described next in the
context of an in-situ MOS capacitor.
studied by several workers. Time for growth of a monolayer
of oxide ranges from one hour for the clean-room ambient, C. In-Situ MOS Capacitor
to a few weeks for specialized wafer-storage either in a single
The final exemplary demonstration of a multiprocessing
wafer polycarbonate package [36] or in an ambient with mois- sequence in this work is the integration of three different proture restricted to less than 0.1 ppm [37]. Thus, while the native cesses with disparate ambient conditions in the RTM-in-situ
oxide can be controlled using special facilities, the complete AHF clean, thermal oxidation and CVD of silicon-to form an
ex-situ elimination of oxide contamination is difficult, and an MOS capacitor. These processes were performed sequentially
in-situ native-oxide removal technique is imperative.
in-situ, according to the schematic time-temperature profile
Several techniques have been tried for in-situ native-oxide shown in Fig. 15. The optimization of the profile shown in Fig.
removal, including ultra-high vacuum, Ar ion plasma, Ultra- 15 in its entirety, and the successful integration of this process
violet (UV) light irradiation in an H2 ambient, GeH4, NF3, sequence demonstrates the feasibility of fabricating an entire
vapor-phase HF. Most of these techniques require complex MOS capacitor in-situ in the RTM-a unique achievement.
equipment and long set-up times, and fail the simplicity In principle, this should yield better device characteristics,
requirement of multiprocessing. Hence, the technique inves- since the interfaces between the semiconductor, gate dielectric
tigated for the RTM was a novel one using thermally-driven and gate electrode are free of ambient contamination. At
AHF. This technique is distinct from vapor-phase HF cleaning, a current density of 1 A/cm2 and oxide thickness of 70
which requires a condensed layer of HF to form on the wafer A, the integration of in-situ AHF clean and oxide growth
surface, and requires special chamber material (Sic) to contain yielded Q b d = 6.2 C/cm2, which is at least comparable to
the corrosive ambient. Here, the basic idea is a thermally a standard gate oxide (Qbd = 6.9 C/cm2). Since this is the
driven process, where AHF and H2 are flowed at tempera- first demonstration of such a sequence, it is believed that
~
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 7, NO. 2, MAY 1994
170
1000
I
{
E
0 800
I
~~~ofsilicon
Flow = 100 sccm
Q)
92
fiUJ
600
v
2
3 400
Ea
0.
E
I-
200
O
0
10
Time (min)
20
Fig. 15. Schematic time-temperature profile for in-situ fabrication of MOS
capacitors.
1400
VIII. ECONOMIC
MODELING
OF ADAPTABLE
MANUFACTURING
SYSTEMS
1200
loo0
800
600
400
200
0
0
20
40
60
Sputtering time [min]
80
(b)
Fig. 14. (a) Time-temperature profile for in-situ AHF clean, followed by a
high-temperature “spike” with AHF and HZ flowing, followed by deposition
of Si. The process includes a 15 second overlap between AHF and S i b .
(b) Auger analysis comparing native oxide peaks for in-siru AHF clean, for
in-situ Hz clean, and control sample with no in-situ clean. Clearly, the in-situ
AHF clean is able to eliminate the native oxide peak.
these preliminary results can be improved upon considerably
with process maturity. Thus, while the in-situ MOS capacitor
process is far from optimized based on the results presented
here, a sound foundation has been laid for this idea both on
scientific and technological fronts. Scientifically, a “stronger”
interface would be achieved by contaminant elimination in
the in-situ capacitor, and thus would enable better reliability.
Technologically, the RTM provides the tool for fabricating
such an in-situ capacitor. Further, the process feasibility and
preliminary results demonstrated here indicate the potential
for using this multiprocessing technology for growing more
reliable dielectrics.
To determine the potential economic significance of equipment developed in the MMST program, models of fabs
based on conventional technology and the MMST technology
were developed. The choice of what economic performance
parameters to consider was motivated by the typical life cycle
of a semiconductor circuit. The lifecycle can be divided into
three stages as follows. At the earliest or “pilot” stage, new unit
processes are being developed in an R&D environment, and
the capital cost of a minimum efficient scale is the strongest
determinant of economic success. In the next stage, which
we refer to as “fast cycle,” the unit processes are integrated
together and the product is then ramped up to full volume.
In this stage, fast throughput times determine critical time
to market and yield learning, and is thus the most important
determinant of economic success. In the third stage, which
we refer to as “mature,” high volume manufacturing and
yields are maintained, and parts are generally manufactured
to inventory rather than order. In this stage, cost per wafer is
the most important determinant of economic success. Note that
university R&D labs are perpetually in the first stage, ASIC
fabs running standard flows are perpetually in the second stage,
and DRAM fabs evolve through all three stages.
The qualitative vision of an Adaptable Manufacturing System (AMS) was developed based on the determinants of
success in the different stages of the product life cycle. The
goal of the AMS is to allow very small scale production
for pilot fabs, very fast production for fast cycle fabs, and
cost-competitive production for mature fabs. This contrasts to
the traditional Mass Manufacturing System (MMS), where the
goal has mainly been cost-competitive production for mature
fabs at the expense of economic viability in the previous two
stages. Table I compares the qualitative features of the MMS
and AMs.
As the table shows, the single-wafer processing and closedloop control are seen as critical developments in achieving
171
SARASWAT et al.: RAPID THERMAL MULTIPROCESSING FOR A PROGRAMMABLE FACTORY
TABLE I
Q U A L ~ A T ICOMPARISON
VE
OF SEMICONDUCTOR
MASS
AND ADAPTABLE
MANFUACTURING
SYSTEM
MANUFACTURING
SYSTEM
Operations Goal
Equipment
cycle n n c
Dominant Configuration
Raxss Control
Dominant Architecture
Lm Size
Typical Capacity
Number of products
Typical WJP Inventory
Produa
MMS
Minimize Cast
batch I single wafer
weeks
stand-alone
open loop, in-line SPC
closed
large
large
small
higher
commodity
AM§
Optimize Cost-Time Tradeoff
single wafer
&Y s
clustercd
closed loop, real time
open
small or large
small or large
large
lower
value-added I commodity
O;
SUMMARY
DATAFOR MMS
process ilow
technology basis
capacity (wafer outs)
capital cost
annual operatingcost
clean room area
clean m m class
vacuum cluster tools
wet tools
integrated lithography tools
masking layers
process step
1 wafer minimum cycle time
24 wafer minimum cycle time
TABLE I1
AMs FABSIN NATURE
CONFIGURATION
AND
MMS
0.35 km logic
uaditimal
MMST
l0,oOO wafers pcr month
$261 million
$76 million
16,426 square feet
10,OOO wafers per month
$318 million
$77 million
15,430 square feet
1oOO I minienvironment
34
42 single-wafer tools
10 uv + 16 i-line
17
10
9 wet benches
10 uv
16
325
7.6 days
12.0 days
.
. .5...
io.
-
'1'5'
..
'20'
.
.
'25'
. .
o:-
cycle time (days)
Fig. 16. Simulated performance curves for fabs inmature configuration.
AM§
0.35 pn logic
3
'
454
2.3 days
7.2 days
an AMs. We also believed the flexibility obtained through
the MMST CIM system as critical to an AMS [43]. Another feature of MMST technology were standard interfaces,
which would allow open architecture clustering of singlewafer vacuum processors [U]. Integration of lithography tools
was also demonstrated by TI early in the MMST program.
Surveys of MMST and conventional process technology and
equipment were performed to gather data for models of
AMs's and MMS's. The most extensive of these surveys
took place in 1992. From these surveys, hypothetical specific
implementations of loo00 wafer (200 mm) per month AMS
and MMS fabs running a simplified 0.35 micron logic flow
were developed. A document detailing the data in these models
has been created. The resulting models (in this case of the
mature configured fabs) are summarized in Table 11. The
models and results presented here are based more heavily on
the equipment used in Texas Instruments' MMST fab, relative
to similar AMS models presented previously [7]-[9]. In the
table, annual operating cost does not include depreciation. A
"process step" is a visit to a machine, one wet bath, or a
cluster module.
Because both cost per wafer and throughput time can be
critical to the success of semiconductor manufacturers, both
performance parameters had to be considered. Since there is a
trade-off between these two parameters, the most commonly
used performance measures were plots of throughput time and
wafer costs achievable by given fabs. A set of software modules, named the Stanford Cost and Operations Performance
Evaluator (SCOPE) were developed to model these tradeoffs between cost and time [5], [7], [SI. The most important
module in SCOPE is a discrete event monte carlo simulator.
SCOPE demonstrated three innovations in semiconductor fab
simulation which were critical for the economic performance
evaluation of AMS and MMS models: 1) integration of cost
calculations with simulation; 2) simultaneous simulation of
fab level and cluster level events; and 3) easy implementation
of complex scheduling and routing algorithms. SCOPE was
written in Unix/C at Stanford building on older simulators at
Stanford and Texas Instruments.
Modeling results was to verify that cluster tool and lithography tool integration is critical to obtaining the benefits of fabs
based on single-wafer processors [5]-[8]. This in tum requires
advanced, closed-loop process control. Furthermore, obtaining
the benefits of clustering depends on sophisticated scheduling
and other fab operations policies.
Fig. 16 shows the simulation results of an MMS and AMS
in mature configurations. Each point on the curves represents
the fab running at a different loading or work in process
inventory level. Details of the generation of these types of
curves have been presented previously [6]. For the mature
configuration, the modeled AMS minimum achievable cost
per wafer is 7% higher than the MMS's. Sources of this
higher wafer cost include the cost of capacity of single wafer
rapid thermal processors compared to fumaces, single wafer
cleaning systems compared to wet benches, and extra resist
coat and develop equipment to integrate lithography systems.
These costs are offset somewhat by decreased clean room
requirements (assuming the MMST sealed wafer containers
are used).
Fig. 17 shows the simulation results of an MMS and AMS in
fast cycle configurations. Relative to the mature configurations,
the cost per wafer of both fabs increased by about 15%,
although the MMS cost degraded slightly more than the AMS.
It is expected that the benefits of early market entry and
fast yield leaming would more than compensate for this. In
the fast cycle configuration, median throughput times of five
days could apparently be economically achieved by the AMs,
relative to about 2.5 weeks for the MMS fab.
The minimum efficient scale of fabs in the pilot configuration depend heavily on assumptions of the costs of fab
facilities. Thus, a critical part of cost modeling of very small
fabs (< 2000 wafers per month) are understanding the extent to
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 7, NO. 2, MAY 1994
cycle time (days)
Fig. 17. Simulated performance curves for fabs in fast cycle configuration.
which the pilot fabs can piggyback on larger fabs’ facilities.
The degree of multiprocessing achievable by rapid thermal
processors is another key assumption. More work clearly needs
to be done in this area.
In summary, the semiconductor industry is not immune
to the emerging requirements of faster and more flexible
manufacturing that have been shaking up other industries such
as the automobile industry. We have developed a vision of an
Adaptable Manufacturing System (AMS) for semiconductor
manufacturing, and a specific hypothetical implementation
of an AMS using MMST technology. Comparison of the
performance of the AMS model, relative to a model of a more
conventional fab showed that the AMS could indeed be used to
accelerate process development and production economically,
relative to conventional technology.
on the surface unlike pyrometry. We have shown that RTM
offers good transient and steady state temperature uniformity
over a wide range of process conditions namely temperatures,
pressures and gas flow rates enabling rapid thermal multiprocessing, i.e., several diverse processes performed in sequence
in the same chamber. To demonstrate the programmability of
the RTM, we have integrated three different processes with
disparate process conditions--cleaning, thermal oxidation and
CVD of silicon-sequentially in-situ to fabricate an MOS
capacitor in one process chamber as opposed to three stand
alone pieces of equipment needed in conventional technology.
This could result in reduced cost of the factory, reduction
in cycle time and may provide better device characteristics,
since the interfaces between the semiconductor, gate dielectric
and gate electrode are free of contamination from the room
ambient. In general, our simulations show that the adaptable manufacturing systems (AMS) based on this approach
may offer more economical small or large scale production,
higher flexibility to accommodate many products on several
processes, and faster turnaround to hasten product innovation.
ACKNOWLEDGMENT
The authors are thankful to Y. M. Cho, S. A. Norman, D.
Grossman, R. Hartzell, T. Kailath, P. Losleben, M. Tenenbaum, and E. Wood for making valuable contributions to this
work.
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IX. CONCLUSION
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Krishna C. Saraswat (M’704’71-M’75-SM’85F’89) received the B.E. degree in electronics and
telecommunications in 1968 from Birla Institute of
Technology and Science, Pilani, India, and the M.S.
and Ph.D degrees in electrical engineering in 1969
and 1974, respectively, from Stanford University,
Stanford, CA.
From June 1969 to December 1970, he worked on
microwave transistors at Texas Instruments, Dallas,
TX and since January 1971, he has been with
Stanford University, Califomia, where presently he
is Professor of Electrical Engineering. Prof. Saraswat is working on a variety
of problems related to new and innovative materials, device structures, and
manufacturing technology of silicon devices and integrated circuits. Special
areas of his interest are process and equipment modeling; IC process design
automation; rapid thermal processing; ultrathin MOS gate dielectrics; thin
film transistor (TFT) on insulator technology for memories and large area
displays: concepts of flexible manufacturing of ICs; and development of tools
and methodology for simulation and control of a VLSI manufacturing line.
Prof. Saraswat is a member of Electrochemical Society and Sigma Xi.
ON ELECTRONDEVICES
during
He was co-editor of the IEEE TRANSACTIONS
1988-1990. He has authored or coauthored over 230 technical papers.
Pushkar P. Apte received the B. Tech. degree in
ceramic engineering from the Institute of Technology, Banaras Hindu University, Varanasi, India, in
1987, and the M.S. and Ph.D. degrees in materials
science and electrical engineering from Stanford
University, Stanford, Califomia in 1989 and 1993,
respectively. His Ph.D. thesis focussed on the science and technology of ultrathin dielectnc films
for integrated circuit technology: he developed a
new physical-damage model for the reliability of
ultrathin dielectric films under high-field stress, and
he led the development of a prototype flexible single-wafer equipment, namely
the Rapid Thermal Multiprocessor (RTM), that can perform multiple processes
in-situ. The RTM was used to validate the physical-damage model, and to grow
reliable composite dielectnc films. Additionally, he has worked on in-situ film
thickness sensors, and novel in-situ pre-cleaning techniques.
Currently, he is working for the Texas Instruments Inc., Dallas in their
Semiconductor Process and Design Center, where his work involves building
process models with the goal of enabling high-value, fast cycle-time process
research and development.
174
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 7, NO. 2, MAY 1994
Leonard Booth was bom in San Mateo, CA in
1947.
He has been with the Stanford Integrated Circuits
Lab since 1982 working on repair and upgrade of
semiconductor process equipment. Since 1988, he
has worked in the ‘Stanford Center for Integrated
Systems as project engineer/coordinator for equipment development, process, and sensor integration
on the Rapid Thermal Multiprocessor.
Yunzhong Chen received the B.S. degree in engineering mechanics at Tsinghua University, China, in
1990 and the M.S. degree in mechanical engineering
at Stanford University in 1992. He is currently
studying electrical engineering at Stanford.
He has worked in several areas including charging of particle in MHD channel and diamond deposition in RF plasma. His current reserch interest
is computer- aided design of new rapid thermal
processor.
Paul C. P. Dankoski was bom in Midland, MI
on Nov. 5, 1967. He received the B.S. degree in
electrical engineering from the University of Notre
Dame in 1990 and the M.S. degree in electrical
engineering from Stanford University in 1991. He
is currently working toward the Ph.D. degree in
electrical engineering at Stanford University.
He received the Achievement Rewards for College Scientists (ARCS), Northem Califomia Chapter in 1992 and the Centennial Teaching Assistant
award at Stanford University in 1991. His current
interest is in the areaof applying multivariable control theory to semiconductor
manufacturing processes, specifically Rapid Thermal Multiprocessing.
F. Levent Degertekin was bom in Diyarbakir,
Turkey, in 1968. He received the B.S. degree
from the Middle East Technical University,
Ankara, Turkey, and the M.S. degree from Bilkent
University, Ankara, Turkey, in 1989 and 1991,
respectively, both in electrical engineering.
He was a research assistant at Bilkent University
from 1989 to 1992. In 1992, he worked at Stanford
University as a visiting scholar. Currently, he is a
Ph.D. candidate at Stanford University. His research
interests include acoustic sensors for semiconductor
processing, nondestructive testing and acoustic imaging.
Gene F. Franklin (S’SO-M’52-SM’6GF’78LF’93) received degrees at Georgia Tech, MIT,
and Columbia University, completing the doctorate
in 1955.
He has been at Stanford University, Stanford,
CA since 1957, where he is currently Professor of
Electrical Engineering. His research and teaching
interests are in the area of digital control, with
current emphasis on model order reduction, adaptive
control, including algorithms for implementation on
microprocessors, and development of computeraided design tools for control.
Dr. Franklin is the coauthor of three books on control, including Digitul
Conrrol of Dynamic Systems ( second ed., Addison-Wesley, 1990). with J.
D. Powell and M. L. Workman and Feedback Control of Dynamic Systems
(third ed., Addison-Wesley, 1994) with J. D. Powell and A. Emami-Naeini.
He is was vice-president for technical affairs of the IEEE Control Society in
1986 and 1987. In 1985, he received the Education Award of the American
Automatic Control Council, and in 1990 he and his coauthors received the
IFAC Award for the best textbook for Feedbuck Control of Dynamic Systems.
Butrus T. Khuri-Yakuh (S’7O-M’76-SM’87) was
bom in Beirut, Lebanon. He received the B.S.
degree in 1970 from the American University of
Beirut, the M.S. degree in 1972 from Dartmouth
College, and the Ph.D. degree in 1975 from Stanford
University, all in electrical engineering.
He joined the research staff at the E. L. Ginzton
Laboratory of Stanford University in 1976 as a
research associate. He was promoted to a Senior
Research Associate in 1978, and to a Professor of
Electrical Engineering (Research) in 1982. He has
served on many university committees and is presently Associate Chairman
for graduate admissions in the EE department at Stanford for the academic
year 93-94. Prof. Khuri-Yakub has been teaching both at the graduate and
undergraduate levels for over 10 years, and his current research interests
include acoustic flui d ejection, silicon micromachining and its applications
to ultrasonic materials, sensors for in-situ process monitoring and control,
nondestructive evaluati on, and acoustic imaging and microscopy. Professor
Khuri-Yakub is a senior member of the Acoustical Society of America, and a
member of Tau Beta Pi. He is associate editor of Research in Nondestructive
Evaluation, a Joumal of the American Society for Nondestructive Testing;
and a member of the Ad-Com of the IEEE group on Ultrasonics Ferroelectr
ics and Frequency Control.
Prof. Khuri-Yakub has authored more than 250 publications and has been
principal inventor or co-inventor on over 30 patents. He received the Stanford
University School of Engineering Distinguished Advisor Award, June 1987,
and the Medal of the City of Bordeaux for contributions to NDE, 1983.
Mehrdad M. Moslehi (S’82-M’86SM’92) was
bom in Tehran, Iran, on October 21, 1959 (Naturalized U.S. citizen as of July, 1993). He completed his
undergraduate studies towards the B.S.E.E. degree
at Arya-Mehr University of Technology, Tehran,
Iran, in 1980. He received the M.S. and Ph.D.
degrees both in electrical engineering from Stanford
University, Stanford, CA. His dissertation work was
on thermal and plasma nitridation of silicon and
silicon dioxide for ultrathin gate insulators of MOS
VLSI.
During his undergraduate years, he worked as a Design Engineer at Sarah
Electric Co. and developed several commercial electronic systems. He was
also a founder of ”Donyayeh-Electronic” (Electronics World) Co. in Tehran
(1980) where he developed commercial power inverter systems. During the
period of 1980-1981, he was a Research Engineer at Iran Telecommunication
Research Center (ITRC) where he designed several telecommunication systems including a PCM CODEC system with fiber-optic transmission interface
and a voice compression system. Following his Ph.D. studies, he joined the
the Center for Integrated Systems at Stanford University in October 1985
as a Research Associate. His work at Stanford included graduate teaching
and research in the areas of ultrathin dielectrics, rapid thermal processing,
microwave plasma processing, in-situ multiprocessing, sensor fusion, and
microelectronics manufacturing science and technology. He has also worked
in several companies (Xerox PARC, General ElectricDntersil, and Honeywell/
Synertek) on nonvolatile memories and low-temperature plasma processing.
He has also been a technical consultant in the areas of semiconductor
devices and technologies, processing equipment, and analoddigital system
design. He joined the Semiconductor Process and Design Center at Texas
Instruments in May 1988 where he has been a Branch Manager responsible
for various projects including agile IC manufacturing, process synthesis, rapid
thermal processing technology, metal depositions, sensor fusion for ULSI
manufacturing process control, and advanced process development for 0.35
um and 0.25 um CMOS/BiCMOS technologies. He is also a Consulting
Faculty with the Eelectrical Engineering Department and Center for Integrated
Systems at Stanford University. Dr. Moslehi has joined CVC Products, Inc. as
CVC’s Senior Vice President and Chief Technical Officer in charge of Product
Research, Development, and Engineering (PRDE) organizations. In his new
position, he will be responsible for all CVC’s product development programs
in support of the semiconductor IC manufacturing, flat-panel display, and
data storage industries.
Dr. Moslehi has published over 80 joumal and conference papers and owns
over 80 inventions (40+ issued patents). He was recognized as a Technologist/
Inventor of the year by American Electronics Association (AEA) in May 1993.
He has also been a member of the VLSI Technology Symposium Technical
Program Committee. Dr. Moslehi is a member of APS, ECS, MRS, and SPIE.
SARASWAT el U/.: RAPID THERMAL MULTIPROCESSING FOR A PROGRAMMABLE FACTORY
Charles Schaper received the B.S. degree in chemical and materials engineering in 1985 and the M.S.
degree in chemical engineering in 1986,from the
University of Connecticut, and the Ph.D. degree in
chemical engineering, 1990,from the University of
Califomia, Santa Barbara. He was a postdoctoral
scholar in electncal engineering, 1990,at Stanford
University.
He is on the academic staff at Stanford University, since 1991, as a research scientist in the
electrical engineeringdepartment where he conducts
research on semiconductor manufacturing. Additional experience includes
development engineer for Engineering MicroSimulations, Inc., 1984-1985;
research engineer for the NSF Center for Robotic Systems and Microelectronics, 1986-1988; consulatant for Computational Engineering, Inc.,
1989-1990. He has worked, on assignment from Stanford University, at the
Semiconductor Process and Design Center at Texas Instruments, 1992-1993,
on the development and implementation of control systems for rapid thermal
processing equipment used in the Microelectronics Manufacturing Science
and Technology program.
Dr. Schaper has published several technical papers. He is co-founder and
president of Microelectronics Control & Sensing, Inc.
Paul J. Gyugyi was bom in Pittsburgh, PA in 1966. He received the B.S.
in electrical engineering from Pennsylvania State University in 1988,and the
M.S. and Ph.D: degreei in electricalengineering from Stanford University in
1989 and 1993,respectively.
He received a National Science Foundation Fellowship award in 1988,the
Van Dyke/Class of 1921 Penn State Memorial Scholarship and a Westinghouse
Family Scholarshipin 1984.He is currently a Senior Systems Engineer at ESL,
Inc., a TRW company, designing signal processing systems.
Dr. Gyugyi is a member of Eta Kappa Nu and Tau Beta Pi.
175
Y. J. Lee photograph a~nd biography not available at the time of publication.
Jun Pei was bom in Beijing, P.R.China, in 1968.He
received the B.A. degree in physics and computer
science from Brandeis University, and is continuing
his study as a Ph.D. student in electrical engineering
at Stanford University.
His research interests include acoustic sensing in
semiconductor processing and nondestructive test.
.
Samuel C. Wood (S’85-M’91-S’91-M’92)received the B.S. degree in economics, with a
concentration in the management of technological
innovation from the Wharton School of Business,
University of Pennsylvania, and received the B.S.
degree in electrical engineering, from the Moore
School, University of Pennsylvania. His Masters
and Ph.D. degrees in electrical engineering were
done at Stanford University.
In September 1992, he joined the faculty in the
Operations, Information, and Technology group in
the Stanford Graduate School of Business, as an Assistant Professor of
Manufacturing and Technology. He is also the Robert M. and Anne T. Bass
Faculty Fellow for 1993-94.His research and teaching interests are in product
development systems and manufacturing systems, with an emphasis on those
systems’ technologies, architectures, and management. He is focusing on the
semiconductor industry as a vehicle of study, with the primary method of
analysis being mathematical and computer modeling.